[ARM] add tests for alternate forms of select-of-constants; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296178 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/ARM/select_const.ll b/test/CodeGen/ARM/select_const.ll
index 9f4cb6fa4d521d1dcc000a55f83551f3baeb7ffb..50c36310b2cea8b7e3d14648bf2e9ac7a84f67a1 100644 (file)
--- a/test/CodeGen/ARM/select_const.ll
+++ b/test/CodeGen/ARM/select_const.ll
@@ -95,6 +95,39 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) {
   ret i32 %sel
 }
 
+define i32 @select_0_or_neg1_alt(i1 %cond) {
+; CHECK-LABEL: select_0_or_neg1_alt:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    mov r1, #1
+; CHECK-NEXT:    bic r0, r1, r0
+; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    mov pc, lr
+  %z = zext i1 %cond to i32
+  %add = add i32 %z, -1
+  ret i32 %add
+}
+
+define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) {
+; CHECK-LABEL: select_0_or_neg1_alt_zeroext:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    eor r0, r0, #1
+; CHECK-NEXT:    rsb r0, r0, #0
+; CHECK-NEXT:    mov pc, lr
+  %z = zext i1 %cond to i32
+  %add = add i32 %z, -1
+  ret i32 %add
+}
+
+define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) {
+; CHECK-LABEL: select_0_or_neg1_alt_signext:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    mvn r0, r0
+; CHECK-NEXT:    mov pc, lr
+  %z = zext i1 %cond to i32
+  %add = add i32 %z, -1
+  ret i32 %add
+}
+
 ; select Cond, -1, 0 --> sext (Cond)
 
 define i32 @select_neg1_or_0(i1 %cond) {