const TargetRegisterInfo *TRI) {
return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
- MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || MI.isDebugValue();
+ MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
+ MI.isMetaInstruction();
}
static unsigned UseReg(const MachineOperand& MO) {
return 0u;
unsigned T = std::count_if(B->begin(), B->getFirstTerminator(),
[](const MachineInstr &MI) {
- return !MI.isDebugValue();
+ return !MI.isMetaInstruction();
});
if (T < HEXAGON_PACKET_SIZE)
Spare += HEXAGON_PACKET_SIZE-T;
MachineBasicBlock::iterator MIE = MBB.end();
while (MII != MIE) {
InstOffset += HII->getSize(*MII);
- if (MII->isDebugValue()) {
+ if (MII->isMetaInstruction()) {
++MII;
continue;
}