ret i32 %z
}
+; (X >>u,exact C1) << C2 --> X << (C2-C1) when C2 > C1
+
define i32 @test48(i32 %x) {
; CHECK-LABEL: @test48(
; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2
ret i32 %B
}
+; Verify that wrap flags are preserved from the original 'shl'.
+
+define i32 @test48_nuw_nsw(i32 %x) {
+; CHECK-LABEL: @test48_nuw_nsw(
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = lshr exact i32 %x, 1
+ %B = shl nuw nsw i32 %A, 3
+ ret i32 %B
+}
+
+; (X >>u,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1
+
+define <2 x i32> @test48_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test48_splat_vec(
+; CHECK-NEXT: [[A:%.*]] = lshr exact <2 x i32> %x, <i32 1, i32 1>
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[A]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = lshr exact <2 x i32> %x, <i32 1, i32 1>
+ %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
+; (X >>s,exact C1) << C2 --> X << (C2-C1) when C2 > C1
+
define i32 @test49(i32 %x) {
; CHECK-LABEL: @test49(
; CHECK-NEXT: [[B:%.*]] = shl i32 %x, 2
ret i32 %B
}
+; Verify that wrap flags are preserved from the original 'shl'.
+
+define i32 @test49_nuw_nsw(i32 %x) {
+; CHECK-LABEL: @test49_nuw_nsw(
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw i32 %x, 2
+; CHECK-NEXT: ret i32 [[B]]
+;
+ %A = ashr exact i32 %x, 1
+ %B = shl nuw nsw i32 %A, 3
+ ret i32 %B
+}
+
+; (X >>s,exact C1) << C2 --> X << (C2-C1) when splatted C2 > C1
+
+define <2 x i32> @test49_splat_vec(<2 x i32> %x) {
+; CHECK-LABEL: @test49_splat_vec(
+; CHECK-NEXT: [[A:%.*]] = ashr exact <2 x i32> %x, <i32 1, i32 1>
+; CHECK-NEXT: [[B:%.*]] = shl nuw nsw <2 x i32> [[A]], <i32 3, i32 3>
+; CHECK-NEXT: ret <2 x i32> [[B]]
+;
+ %A = ashr exact <2 x i32> %x, <i32 1, i32 1>
+ %B = shl nsw nuw <2 x i32> %A, <i32 3, i32 3>
+ ret <2 x i32> %B
+}
+
define i32 @test50(i32 %x) {
; CHECK-LABEL: @test50(
; CHECK-NEXT: [[B:%.*]] = ashr i32 %x, 2
define i64 @test_64(i32 %t) {
; CHECK-LABEL: @test_64(
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 %t, 8
-; CHECK-NEXT: [[EXT:%.*]] = zext i32 [[SHL]] to i64
-; CHECK-NEXT: ret i64 [[EXT]]
-
+; CHECK-NEXT: [[TMP1:%.*]] = shl i32 %t, 8
+; CHECK-NEXT: [[SHL:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT: ret i64 [[SHL]]
+;
%and = and i32 %t, 16777215
%ext = zext i32 %and to i64
%shl = shl i64 %ext, 8