PROVIDE ( RTCCNTL = 0x3ff48000 );
PROVIDE ( RTCIO = 0x3ff48400 );
PROVIDE ( SENS = 0x3ff48800 );
+PROVIDE ( HINF = 0x3ff4B000 );
PROVIDE ( UHCI1 = 0x3ff4C000 );
PROVIDE ( I2S0 = 0x3ff4F000 );
PROVIDE ( UART1 = 0x3ff50000 );
PROVIDE ( I2C0 = 0x3ff53000 );
PROVIDE ( UHCI0 = 0x3ff54000 );
+PROVIDE ( HOST = 0x3ff55000 );
PROVIDE ( RMT = 0x3ff56000 );
PROVIDE ( RMTMEM = 0x3ff56800 );
PROVIDE ( PCNT = 0x3ff57000 );
+PROVIDE ( SLC = 0x3ff58000 );
PROVIDE ( LEDC = 0x3ff59000 );
PROVIDE ( MCPWM0 = 0x3ff5E000 );
PROVIDE ( TIMERG0 = 0x3ff5F000 );
--- /dev/null
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HINF_REG_H_
+#define _SOC_HINF_REG_H_
+
+
+#include "soc.h"
+#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
+/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
+/*description: */
+#define HINF_DEVICE_ID_FN1 0x0000FFFF
+#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
+#define HINF_DEVICE_ID_FN1_V 0xFFFF
+#define HINF_DEVICE_ID_FN1_S 16
+/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
+/*description: */
+#define HINF_USER_ID_FN1 0x0000FFFF
+#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
+#define HINF_USER_ID_FN1_V 0xFFFF
+#define HINF_USER_ID_FN1_S 0
+
+#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
+/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
+/*description: */
+#define HINF_SDIO20_CONF1 0x00000007
+#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
+#define HINF_SDIO20_CONF1_V 0x7
+#define HINF_SDIO20_CONF1_S 29
+/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define HINF_FUNC2_EPS (BIT(28))
+#define HINF_FUNC2_EPS_M (BIT(28))
+#define HINF_FUNC2_EPS_V 0x1
+#define HINF_FUNC2_EPS_S 28
+/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
+/*description: */
+#define HINF_SDIO_VER 0x00000FFF
+#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
+#define HINF_SDIO_VER_V 0xFFF
+#define HINF_SDIO_VER_S 16
+/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
+/*description: */
+#define HINF_SDIO20_CONF0 0x0000000F
+#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
+#define HINF_SDIO20_CONF0_V 0xF
+#define HINF_SDIO20_CONF0_S 12
+/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HINF_IOENABLE1 (BIT(11))
+#define HINF_IOENABLE1_M (BIT(11))
+#define HINF_IOENABLE1_V 0x1
+#define HINF_IOENABLE1_S 11
+/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HINF_EMP (BIT(10))
+#define HINF_EMP_M (BIT(10))
+#define HINF_EMP_V 0x1
+#define HINF_EMP_S 10
+/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HINF_FUNC1_EPS (BIT(9))
+#define HINF_FUNC1_EPS_M (BIT(9))
+#define HINF_FUNC1_EPS_V 0x1
+#define HINF_FUNC1_EPS_S 9
+/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HINF_CD_DISABLE (BIT(8))
+#define HINF_CD_DISABLE_M (BIT(8))
+#define HINF_CD_DISABLE_V 0x1
+#define HINF_CD_DISABLE_S 8
+/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HINF_IOENABLE2 (BIT(7))
+#define HINF_IOENABLE2_M (BIT(7))
+#define HINF_IOENABLE2_V 0x1
+#define HINF_IOENABLE2_S 7
+/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_INT_MASK (BIT(6))
+#define HINF_SDIO_INT_MASK_M (BIT(6))
+#define HINF_SDIO_INT_MASK_V 0x1
+#define HINF_SDIO_INT_MASK_S 6
+/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_IOREADY2 (BIT(5))
+#define HINF_SDIO_IOREADY2_M (BIT(5))
+#define HINF_SDIO_IOREADY2_V 0x1
+#define HINF_SDIO_IOREADY2_S 5
+/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define HINF_SDIO_CD_ENABLE (BIT(4))
+#define HINF_SDIO_CD_ENABLE_M (BIT(4))
+#define HINF_SDIO_CD_ENABLE_V 0x1
+#define HINF_SDIO_CD_ENABLE_S 4
+/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HINF_HIGHSPEED_MODE (BIT(3))
+#define HINF_HIGHSPEED_MODE_M (BIT(3))
+#define HINF_HIGHSPEED_MODE_V 0x1
+#define HINF_HIGHSPEED_MODE_S 3
+/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HINF_HIGHSPEED_ENABLE (BIT(2))
+#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
+#define HINF_HIGHSPEED_ENABLE_V 0x1
+#define HINF_HIGHSPEED_ENABLE_S 2
+/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_IOREADY1 (BIT(1))
+#define HINF_SDIO_IOREADY1_M (BIT(1))
+#define HINF_SDIO_IOREADY1_V 0x1
+#define HINF_SDIO_IOREADY1_S 1
+/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define HINF_SDIO_ENABLE (BIT(0))
+#define HINF_SDIO_ENABLE_M (BIT(0))
+#define HINF_SDIO_ENABLE_V 0x1
+#define HINF_SDIO_ENABLE_S 0
+
+#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
+/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define HINF_SDIO_IOREADY0 (BIT(17))
+#define HINF_SDIO_IOREADY0_M (BIT(17))
+#define HINF_SDIO_IOREADY0_V 0x1
+#define HINF_SDIO_IOREADY0_S 17
+/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_RST (BIT(16))
+#define HINF_SDIO_RST_M (BIT(16))
+#define HINF_SDIO_RST_V 0x1
+#define HINF_SDIO_RST_S 16
+/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: */
+#define HINF_CHIP_STATE 0x000000FF
+#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
+#define HINF_CHIP_STATE_V 0xFF
+#define HINF_CHIP_STATE_S 8
+/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define HINF_PIN_STATE 0x000000FF
+#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
+#define HINF_PIN_STATE_V 0xFF
+#define HINF_PIN_STATE_S 0
+
+#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
+/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W0 0xFFFFFFFF
+#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
+#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W0_S 0
+
+#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
+/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W1 0xFFFFFFFF
+#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
+#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W1_S 0
+
+#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
+/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W2 0xFFFFFFFF
+#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
+#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W2_S 0
+
+#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
+/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W3 0xFFFFFFFF
+#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
+#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W3_S 0
+
+#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
+/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W4 0xFFFFFFFF
+#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
+#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W4_S 0
+
+#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
+/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W5 0xFFFFFFFF
+#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
+#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W5_S 0
+
+#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
+/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W6 0xFFFFFFFF
+#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
+#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W6_S 0
+
+#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
+/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W7 0xFFFFFFFF
+#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
+#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
+#define HINF_CIS_CONF_W7_S 0
+
+#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
+/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
+/*description: */
+#define HINF_DEVICE_ID_FN2 0x0000FFFF
+#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
+#define HINF_DEVICE_ID_FN2_V 0xFFFF
+#define HINF_DEVICE_ID_FN2_S 16
+/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
+/*description: */
+#define HINF_USER_ID_FN2 0x0000FFFF
+#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
+#define HINF_USER_ID_FN2_V 0xFFFF
+#define HINF_USER_ID_FN2_S 0
+
+#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
+/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
+/*description: */
+#define HINF_SDIO_DATE 0xFFFFFFFF
+#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
+#define HINF_SDIO_DATE_V 0xFFFFFFFF
+#define HINF_SDIO_DATE_S 0
+
+
+
+
+#endif /*_SOC_HINF_REG_H_ */
+
+
--- /dev/null
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HINF_STRUCT_H_
+#define _SOC_HINF_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+ union {
+ struct {
+ uint32_t user_id_fn1: 16;
+ uint32_t device_id_fn1:16;
+ };
+ uint32_t val;
+ } cfg_data0;
+ union {
+ struct {
+ uint32_t sdio_enable: 1;
+ uint32_t sdio_ioready1: 1;
+ uint32_t highspeed_enable: 1;
+ uint32_t highspeed_mode: 1;
+ uint32_t sdio_cd_enable: 1;
+ uint32_t sdio_ioready2: 1;
+ uint32_t sdio_int_mask: 1;
+ uint32_t ioenable2: 1;
+ uint32_t cd_disable: 1;
+ uint32_t func1_eps: 1;
+ uint32_t emp: 1;
+ uint32_t ioenable1: 1;
+ uint32_t sdio20_conf0: 4;
+ uint32_t sdio_ver: 12;
+ uint32_t func2_eps: 1;
+ uint32_t sdio20_conf1: 3;
+ };
+ uint32_t val;
+ } cfg_data1;
+ uint32_t reserved_8;
+ uint32_t reserved_c;
+ uint32_t reserved_10;
+ uint32_t reserved_14;
+ uint32_t reserved_18;
+ union {
+ struct {
+ uint32_t pin_state: 8;
+ uint32_t chip_state: 8;
+ uint32_t sdio_rst: 1;
+ uint32_t sdio_ioready0: 1;
+ uint32_t reserved18: 14;
+ };
+ uint32_t val;
+ } cfg_data7;
+ uint32_t cis_conf0; /**/
+ uint32_t cis_conf1; /**/
+ uint32_t cis_conf2; /**/
+ uint32_t cis_conf3; /**/
+ uint32_t cis_conf4; /**/
+ uint32_t cis_conf5; /**/
+ uint32_t cis_conf6; /**/
+ uint32_t cis_conf7; /**/
+ union {
+ struct {
+ uint32_t user_id_fn2: 16;
+ uint32_t device_id_fn2:16;
+ };
+ uint32_t val;
+ } cfg_data16;
+ uint32_t reserved_44;
+ uint32_t reserved_48;
+ uint32_t reserved_4c;
+ uint32_t reserved_50;
+ uint32_t reserved_54;
+ uint32_t reserved_58;
+ uint32_t reserved_5c;
+ uint32_t reserved_60;
+ uint32_t reserved_64;
+ uint32_t reserved_68;
+ uint32_t reserved_6c;
+ uint32_t reserved_70;
+ uint32_t reserved_74;
+ uint32_t reserved_78;
+ uint32_t reserved_7c;
+ uint32_t reserved_80;
+ uint32_t reserved_84;
+ uint32_t reserved_88;
+ uint32_t reserved_8c;
+ uint32_t reserved_90;
+ uint32_t reserved_94;
+ uint32_t reserved_98;
+ uint32_t reserved_9c;
+ uint32_t reserved_a0;
+ uint32_t reserved_a4;
+ uint32_t reserved_a8;
+ uint32_t reserved_ac;
+ uint32_t reserved_b0;
+ uint32_t reserved_b4;
+ uint32_t reserved_b8;
+ uint32_t reserved_bc;
+ uint32_t reserved_c0;
+ uint32_t reserved_c4;
+ uint32_t reserved_c8;
+ uint32_t reserved_cc;
+ uint32_t reserved_d0;
+ uint32_t reserved_d4;
+ uint32_t reserved_d8;
+ uint32_t reserved_dc;
+ uint32_t reserved_e0;
+ uint32_t reserved_e4;
+ uint32_t reserved_e8;
+ uint32_t reserved_ec;
+ uint32_t reserved_f0;
+ uint32_t reserved_f4;
+ uint32_t reserved_f8;
+ uint32_t date; /**/
+} hinf_dev_t;
+extern hinf_dev_t HINF;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_HINF_STRUCT_H_ */
--- /dev/null
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HOST_REG_H_
+#define _SOC_HOST_REG_H_
+
+
+#include "soc.h"
+#define HOST_SLCHOST_FUNC2_0_REG (DR_REG_SLCHOST_BASE + 0x10)
+/* HOST_SLC_FUNC2_INT : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_FUNC2_INT (BIT(24))
+#define HOST_SLC_FUNC2_INT_M (BIT(24))
+#define HOST_SLC_FUNC2_INT_V 0x1
+#define HOST_SLC_FUNC2_INT_S 24
+
+#define HOST_SLCHOST_FUNC2_1_REG (DR_REG_SLCHOST_BASE + 0x14)
+/* HOST_SLC_FUNC2_INT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_FUNC2_INT_EN (BIT(0))
+#define HOST_SLC_FUNC2_INT_EN_M (BIT(0))
+#define HOST_SLC_FUNC2_INT_EN_V 0x1
+#define HOST_SLC_FUNC2_INT_EN_S 0
+
+#define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20)
+/* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define HOST_SLC_FUNC1_MDSTAT (BIT(0))
+#define HOST_SLC_FUNC1_MDSTAT_M (BIT(0))
+#define HOST_SLC_FUNC1_MDSTAT_V 0x1
+#define HOST_SLC_FUNC1_MDSTAT_S 0
+
+#define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34)
+/* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT0 0xFFFFFFFF
+#define HOST_GPIO_SDIO_INT0_M ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S))
+#define HOST_GPIO_SDIO_INT0_V 0xFFFFFFFF
+#define HOST_GPIO_SDIO_INT0_S 0
+
+#define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38)
+/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT1 0x000000FF
+#define HOST_GPIO_SDIO_INT1_M ((HOST_GPIO_SDIO_INT1_V)<<(HOST_GPIO_SDIO_INT1_S))
+#define HOST_GPIO_SDIO_INT1_V 0xFF
+#define HOST_GPIO_SDIO_INT1_S 0
+
+#define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C)
+/* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_IN0 0xFFFFFFFF
+#define HOST_GPIO_SDIO_IN0_M ((HOST_GPIO_SDIO_IN0_V)<<(HOST_GPIO_SDIO_IN0_S))
+#define HOST_GPIO_SDIO_IN0_V 0xFFFFFFFF
+#define HOST_GPIO_SDIO_IN0_S 0
+
+#define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40)
+/* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_IN1 0x000000FF
+#define HOST_GPIO_SDIO_IN1_M ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S))
+#define HOST_GPIO_SDIO_IN1_V 0xFF
+#define HOST_GPIO_SDIO_IN1_S 0
+
+#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44)
+/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_EOF 0x0000000F
+#define HOST_SLC0_RX_PF_EOF_M ((HOST_SLC0_RX_PF_EOF_V)<<(HOST_SLC0_RX_PF_EOF_S))
+#define HOST_SLC0_RX_PF_EOF_V 0xF
+#define HOST_SLC0_RX_PF_EOF_S 28
+/* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_TOKEN1 0x00000FFF
+#define HOST_HOSTSLC0_TOKEN1_M ((HOST_HOSTSLC0_TOKEN1_V)<<(HOST_HOSTSLC0_TOKEN1_S))
+#define HOST_HOSTSLC0_TOKEN1_V 0xFFF
+#define HOST_HOSTSLC0_TOKEN1_S 16
+/* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID (BIT(12))
+#define HOST_SLC0_RX_PF_VALID_M (BIT(12))
+#define HOST_SLC0_RX_PF_VALID_V 0x1
+#define HOST_SLC0_RX_PF_VALID_S 12
+/* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0 0x00000FFF
+#define HOST_SLC0_TOKEN0_M ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S))
+#define HOST_SLC0_TOKEN0_V 0xFFF
+#define HOST_SLC0_TOKEN0_S 0
+
+#define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48)
+/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define HOST_SLC0_PF_DATA 0xFFFFFFFF
+#define HOST_SLC0_PF_DATA_M ((HOST_SLC0_PF_DATA_V)<<(HOST_SLC0_PF_DATA_S))
+#define HOST_SLC0_PF_DATA_V 0xFFFFFFFF
+#define HOST_SLC0_PF_DATA_S 0
+
+#define HOST_SLC1_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x4C)
+/* HOST_SLC1_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define HOST_SLC1_PF_DATA 0xFFFFFFFF
+#define HOST_SLC1_PF_DATA_M ((HOST_SLC1_PF_DATA_V)<<(HOST_SLC1_PF_DATA_S))
+#define HOST_SLC1_PF_DATA_V 0xFFFFFFFF
+#define HOST_SLC1_PF_DATA_S 0
+
+#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50)
+/* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_RAW (BIT(25))
+#define HOST_GPIO_SDIO_INT_RAW_M (BIT(25))
+#define HOST_GPIO_SDIO_INT_RAW_V 0x1
+#define HOST_GPIO_SDIO_INT_RAW_S 25
+/* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24
+/* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23
+/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_RAW (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_RAW_M (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_RAW_V 0x1
+#define HOST_SLC0_EXT_BIT3_INT_RAW_S 22
+/* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_RAW (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_RAW_M (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_RAW_V 0x1
+#define HOST_SLC0_EXT_BIT2_INT_RAW_S 21
+/* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_RAW (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_RAW_M (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_RAW_V 0x1
+#define HOST_SLC0_EXT_BIT1_INT_RAW_S 20
+/* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_RAW_M (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_RAW_V 0x1
+#define HOST_SLC0_EXT_BIT0_INT_RAW_S 19
+/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_M (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_V 0x1
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_S 18
+/* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_RAW (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_RAW_M (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_RAW_V 0x1
+#define HOST_SLC0_TX_OVF_INT_RAW_S 17
+/* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_RAW (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_RAW_M (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_RAW_V 0x1
+#define HOST_SLC0_RX_UDF_INT_RAW_S 16
+/* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_RAW (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_RAW_M (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_RAW_V 0x1
+#define HOST_SLC0HOST_TX_START_INT_RAW_S 15
+/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_RAW (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_RAW_M (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_RAW_V 0x1
+#define HOST_SLC0HOST_RX_START_INT_RAW_S 14
+/* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_M (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_V 0x1
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_S 13
+/* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_M (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_V 0x1
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_S 12
+/* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11
+/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10
+/* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9
+/* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8
+/* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7
+/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S 6
+/* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S 5
+/* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S 4
+/* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3
+/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S 2
+/* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S 1
+/* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S 0
+
+#define HOST_SLC1HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x54)
+/* HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x1
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25
+/* HOST_SLC1_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_M (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x1
+#define HOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24
+/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x1
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23
+/* HOST_SLC1_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT3_INT_RAW (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_RAW_M (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_RAW_V 0x1
+#define HOST_SLC1_EXT_BIT3_INT_RAW_S 22
+/* HOST_SLC1_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT2_INT_RAW (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_RAW_M (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_RAW_V 0x1
+#define HOST_SLC1_EXT_BIT2_INT_RAW_S 21
+/* HOST_SLC1_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT1_INT_RAW (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_RAW_M (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_RAW_V 0x1
+#define HOST_SLC1_EXT_BIT1_INT_RAW_S 20
+/* HOST_SLC1_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT0_INT_RAW (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_RAW_M (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_RAW_V 0x1
+#define HOST_SLC1_EXT_BIT0_INT_RAW_S 19
+/* HOST_SLC1_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_RAW_M (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_RAW_V 0x1
+#define HOST_SLC1_RX_PF_VALID_INT_RAW_S 18
+/* HOST_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TX_OVF_INT_RAW (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_RAW_M (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_RAW_V 0x1
+#define HOST_SLC1_TX_OVF_INT_RAW_S 17
+/* HOST_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_UDF_INT_RAW (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_RAW_M (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_RAW_V 0x1
+#define HOST_SLC1_RX_UDF_INT_RAW_S 16
+/* HOST_SLC1HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TX_START_INT_RAW (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_RAW_M (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_RAW_V 0x1
+#define HOST_SLC1HOST_TX_START_INT_RAW_S 15
+/* HOST_SLC1HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_START_INT_RAW (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_RAW_M (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_RAW_V 0x1
+#define HOST_SLC1HOST_RX_START_INT_RAW_S 14
+/* HOST_SLC1HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_RAW_M (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_RAW_V 0x1
+#define HOST_SLC1HOST_RX_EOF_INT_RAW_S 13
+/* HOST_SLC1HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_RAW_M (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_RAW_V 0x1
+#define HOST_SLC1HOST_RX_SOF_INT_RAW_S 12
+/* HOST_SLC1_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_M (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x1
+#define HOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11
+/* HOST_SLC1_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_M (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x1
+#define HOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10
+/* HOST_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_M (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x1
+#define HOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9
+/* HOST_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_M (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x1
+#define HOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8
+/* HOST_SLC1_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_RAW_M (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT7_INT_RAW_S 7
+/* HOST_SLC1_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_RAW_M (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT6_INT_RAW_S 6
+/* HOST_SLC1_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_RAW_M (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT5_INT_RAW_S 5
+/* HOST_SLC1_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_RAW_M (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT4_INT_RAW_S 4
+/* HOST_SLC1_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_RAW_M (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT3_INT_RAW_S 3
+/* HOST_SLC1_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_RAW_M (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT2_INT_RAW_S 2
+/* HOST_SLC1_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_RAW_M (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT1_INT_RAW_S 1
+/* HOST_SLC1_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_RAW_M (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x1
+#define HOST_SLC1_TOHOST_BIT0_INT_RAW_S 0
+
+#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58)
+/* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_ST (BIT(25))
+#define HOST_GPIO_SDIO_INT_ST_M (BIT(25))
+#define HOST_GPIO_SDIO_INT_ST_V 0x1
+#define HOST_GPIO_SDIO_INT_ST_S 25
+/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S 24
+/* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S 23
+/* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_ST (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ST_M (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ST_V 0x1
+#define HOST_SLC0_EXT_BIT3_INT_ST_S 22
+/* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_ST (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ST_M (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ST_V 0x1
+#define HOST_SLC0_EXT_BIT2_INT_ST_S 21
+/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_ST (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ST_M (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ST_V 0x1
+#define HOST_SLC0_EXT_BIT1_INT_ST_S 20
+/* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_ST (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ST_M (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ST_V 0x1
+#define HOST_SLC0_EXT_BIT0_INT_ST_S 19
+/* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_ST (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ST_M (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ST_V 0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ST_S 18
+/* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_ST (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ST_M (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ST_V 0x1
+#define HOST_SLC0_TX_OVF_INT_ST_S 17
+/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_ST (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ST_M (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ST_V 0x1
+#define HOST_SLC0_RX_UDF_INT_ST_S 16
+/* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_ST (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ST_M (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ST_V 0x1
+#define HOST_SLC0HOST_TX_START_INT_ST_S 15
+/* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_ST (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ST_M (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ST_V 0x1
+#define HOST_SLC0HOST_RX_START_INT_ST_S 14
+/* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ST_M (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ST_V 0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ST_S 13
+/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ST_M (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ST_V 0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ST_S 12
+/* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S 11
+/* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S 10
+/* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9
+/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S 8
+/* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_M (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_S 7
+/* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_M (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_S 6
+/* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_M (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_S 5
+/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_M (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_S 4
+/* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_M (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_S 3
+/* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_M (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_S 2
+/* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_M (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_S 1
+/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_M (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_V 0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_S 0
+
+#define HOST_SLC1HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x5C)
+/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x1
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25
+/* HOST_SLC1_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_ST_M (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x1
+#define HOST_SLC1_HOST_RD_RETRY_INT_ST_S 24
+/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x1
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23
+/* HOST_SLC1_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT3_INT_ST (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_ST_M (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_ST_V 0x1
+#define HOST_SLC1_EXT_BIT3_INT_ST_S 22
+/* HOST_SLC1_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT2_INT_ST (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_ST_M (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_ST_V 0x1
+#define HOST_SLC1_EXT_BIT2_INT_ST_S 21
+/* HOST_SLC1_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT1_INT_ST (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_ST_M (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_ST_V 0x1
+#define HOST_SLC1_EXT_BIT1_INT_ST_S 20
+/* HOST_SLC1_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT0_INT_ST (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_ST_M (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_ST_V 0x1
+#define HOST_SLC1_EXT_BIT0_INT_ST_S 19
+/* HOST_SLC1_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_VALID_INT_ST (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_ST_M (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_ST_V 0x1
+#define HOST_SLC1_RX_PF_VALID_INT_ST_S 18
+/* HOST_SLC1_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TX_OVF_INT_ST (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_ST_M (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_ST_V 0x1
+#define HOST_SLC1_TX_OVF_INT_ST_S 17
+/* HOST_SLC1_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_UDF_INT_ST (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_ST_M (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_ST_V 0x1
+#define HOST_SLC1_RX_UDF_INT_ST_S 16
+/* HOST_SLC1HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TX_START_INT_ST (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_ST_M (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_ST_V 0x1
+#define HOST_SLC1HOST_TX_START_INT_ST_S 15
+/* HOST_SLC1HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_START_INT_ST (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_ST_M (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_ST_V 0x1
+#define HOST_SLC1HOST_RX_START_INT_ST_S 14
+/* HOST_SLC1HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_EOF_INT_ST (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_ST_M (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_ST_V 0x1
+#define HOST_SLC1HOST_RX_EOF_INT_ST_S 13
+/* HOST_SLC1HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_SOF_INT_ST (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_ST_M (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_ST_V 0x1
+#define HOST_SLC1HOST_RX_SOF_INT_ST_S 12
+/* HOST_SLC1_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_ST_M (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x1
+#define HOST_SLC1_TOKEN1_0TO1_INT_ST_S 11
+/* HOST_SLC1_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_ST_M (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x1
+#define HOST_SLC1_TOKEN0_0TO1_INT_ST_S 10
+/* HOST_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_ST_M (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x1
+#define HOST_SLC1_TOKEN1_1TO0_INT_ST_S 9
+/* HOST_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_ST_M (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x1
+#define HOST_SLC1_TOKEN0_1TO0_INT_ST_S 8
+/* HOST_SLC1_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_ST_M (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT7_INT_ST_S 7
+/* HOST_SLC1_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_ST_M (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT6_INT_ST_S 6
+/* HOST_SLC1_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_ST_M (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT5_INT_ST_S 5
+/* HOST_SLC1_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_ST_M (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT4_INT_ST_S 4
+/* HOST_SLC1_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_ST_M (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT3_INT_ST_S 3
+/* HOST_SLC1_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_ST_M (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT2_INT_ST_S 2
+/* HOST_SLC1_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_ST_M (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT1_INT_ST_S 1
+/* HOST_SLC1_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_ST_M (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_ST_V 0x1
+#define HOST_SLC1_TOHOST_BIT0_INT_ST_S 0
+
+#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60)
+/* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN_CHECK 0x00000FFF
+#define HOST_HOSTSLC0_LEN_CHECK_M ((HOST_HOSTSLC0_LEN_CHECK_V)<<(HOST_HOSTSLC0_LEN_CHECK_S))
+#define HOST_HOSTSLC0_LEN_CHECK_V 0xFFF
+#define HOST_HOSTSLC0_LEN_CHECK_S 20
+/* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN 0x000FFFFF
+#define HOST_HOSTSLC0_LEN_M ((HOST_HOSTSLC0_LEN_V)<<(HOST_HOSTSLC0_LEN_S))
+#define HOST_HOSTSLC0_LEN_V 0xFFFFF
+#define HOST_HOSTSLC0_LEN_S 0
+
+#define HOST_SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64)
+/* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE3 0x000000FF
+#define HOST_SLCHOST_STATE3_M ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S))
+#define HOST_SLCHOST_STATE3_V 0xFF
+#define HOST_SLCHOST_STATE3_S 24
+/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE2 0x000000FF
+#define HOST_SLCHOST_STATE2_M ((HOST_SLCHOST_STATE2_V)<<(HOST_SLCHOST_STATE2_S))
+#define HOST_SLCHOST_STATE2_V 0xFF
+#define HOST_SLCHOST_STATE2_S 16
+/* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE1 0x000000FF
+#define HOST_SLCHOST_STATE1_M ((HOST_SLCHOST_STATE1_V)<<(HOST_SLCHOST_STATE1_S))
+#define HOST_SLCHOST_STATE1_V 0xFF
+#define HOST_SLCHOST_STATE1_S 8
+/* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE0 0x000000FF
+#define HOST_SLCHOST_STATE0_M ((HOST_SLCHOST_STATE0_V)<<(HOST_SLCHOST_STATE0_S))
+#define HOST_SLCHOST_STATE0_V 0xFF
+#define HOST_SLCHOST_STATE0_S 0
+
+#define HOST_SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68)
+/* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE7 0x000000FF
+#define HOST_SLCHOST_STATE7_M ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S))
+#define HOST_SLCHOST_STATE7_V 0xFF
+#define HOST_SLCHOST_STATE7_S 24
+/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE6 0x000000FF
+#define HOST_SLCHOST_STATE6_M ((HOST_SLCHOST_STATE6_V)<<(HOST_SLCHOST_STATE6_S))
+#define HOST_SLCHOST_STATE6_V 0xFF
+#define HOST_SLCHOST_STATE6_S 16
+/* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE5 0x000000FF
+#define HOST_SLCHOST_STATE5_M ((HOST_SLCHOST_STATE5_V)<<(HOST_SLCHOST_STATE5_S))
+#define HOST_SLCHOST_STATE5_V 0xFF
+#define HOST_SLCHOST_STATE5_S 8
+/* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE4 0x000000FF
+#define HOST_SLCHOST_STATE4_M ((HOST_SLCHOST_STATE4_V)<<(HOST_SLCHOST_STATE4_S))
+#define HOST_SLCHOST_STATE4_V 0xFF
+#define HOST_SLCHOST_STATE4_S 0
+
+#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
+
+#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C)
+/* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF3 0x000000FF
+#define HOST_SLCHOST_CONF3_M ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S))
+#define HOST_SLCHOST_CONF3_V 0xFF
+#define HOST_SLCHOST_CONF3_S 24
+/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF2 0x000000FF
+#define HOST_SLCHOST_CONF2_M ((HOST_SLCHOST_CONF2_V)<<(HOST_SLCHOST_CONF2_S))
+#define HOST_SLCHOST_CONF2_V 0xFF
+#define HOST_SLCHOST_CONF2_S 16
+/* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF1 0x000000FF
+#define HOST_SLCHOST_CONF1_M ((HOST_SLCHOST_CONF1_V)<<(HOST_SLCHOST_CONF1_S))
+#define HOST_SLCHOST_CONF1_V 0xFF
+#define HOST_SLCHOST_CONF1_S 8
+/* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF0 0x000000FF
+#define HOST_SLCHOST_CONF0_M ((HOST_SLCHOST_CONF0_V)<<(HOST_SLCHOST_CONF0_S))
+#define HOST_SLCHOST_CONF0_V 0xFF
+#define HOST_SLCHOST_CONF0_S 0
+
+#define HOST_SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70)
+/* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF7 0x000000FF
+#define HOST_SLCHOST_CONF7_M ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S))
+#define HOST_SLCHOST_CONF7_V 0xFF
+#define HOST_SLCHOST_CONF7_S 24
+/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF6 0x000000FF
+#define HOST_SLCHOST_CONF6_M ((HOST_SLCHOST_CONF6_V)<<(HOST_SLCHOST_CONF6_S))
+#define HOST_SLCHOST_CONF6_V 0xFF
+#define HOST_SLCHOST_CONF6_S 16
+/* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF5 0x000000FF
+#define HOST_SLCHOST_CONF5_M ((HOST_SLCHOST_CONF5_V)<<(HOST_SLCHOST_CONF5_S))
+#define HOST_SLCHOST_CONF5_V 0xFF
+#define HOST_SLCHOST_CONF5_S 8
+/* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF4 0x000000FF
+#define HOST_SLCHOST_CONF4_M ((HOST_SLCHOST_CONF4_V)<<(HOST_SLCHOST_CONF4_S))
+#define HOST_SLCHOST_CONF4_V 0xFF
+#define HOST_SLCHOST_CONF4_S 0
+
+#define HOST_SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74)
+/* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF11 0x000000FF
+#define HOST_SLCHOST_CONF11_M ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S))
+#define HOST_SLCHOST_CONF11_V 0xFF
+#define HOST_SLCHOST_CONF11_S 24
+/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF10 0x000000FF
+#define HOST_SLCHOST_CONF10_M ((HOST_SLCHOST_CONF10_V)<<(HOST_SLCHOST_CONF10_S))
+#define HOST_SLCHOST_CONF10_V 0xFF
+#define HOST_SLCHOST_CONF10_S 16
+/* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF9 0x000000FF
+#define HOST_SLCHOST_CONF9_M ((HOST_SLCHOST_CONF9_V)<<(HOST_SLCHOST_CONF9_S))
+#define HOST_SLCHOST_CONF9_V 0xFF
+#define HOST_SLCHOST_CONF9_S 8
+/* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF8 0x000000FF
+#define HOST_SLCHOST_CONF8_M ((HOST_SLCHOST_CONF8_V)<<(HOST_SLCHOST_CONF8_S))
+#define HOST_SLCHOST_CONF8_V 0xFF
+#define HOST_SLCHOST_CONF8_S 0
+
+#define HOST_SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78)
+/* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF15 0x000000FF
+#define HOST_SLCHOST_CONF15_M ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S))
+#define HOST_SLCHOST_CONF15_V 0xFF
+#define HOST_SLCHOST_CONF15_S 24
+/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF14 0x000000FF
+#define HOST_SLCHOST_CONF14_M ((HOST_SLCHOST_CONF14_V)<<(HOST_SLCHOST_CONF14_S))
+#define HOST_SLCHOST_CONF14_V 0xFF
+#define HOST_SLCHOST_CONF14_S 16
+/* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF13 0x000000FF
+#define HOST_SLCHOST_CONF13_M ((HOST_SLCHOST_CONF13_V)<<(HOST_SLCHOST_CONF13_S))
+#define HOST_SLCHOST_CONF13_V 0xFF
+#define HOST_SLCHOST_CONF13_S 8
+/* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF12 0x000000FF
+#define HOST_SLCHOST_CONF12_M ((HOST_SLCHOST_CONF12_V)<<(HOST_SLCHOST_CONF12_S))
+#define HOST_SLCHOST_CONF12_V 0xFF
+#define HOST_SLCHOST_CONF12_S 0
+
+#define HOST_SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7C)
+/* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: Interrupt to target CPU*/
+#define HOST_SLCHOST_CONF19 0x000000FF
+#define HOST_SLCHOST_CONF19_M ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S))
+#define HOST_SLCHOST_CONF19_V 0xFF
+#define HOST_SLCHOST_CONF19_S 24
+/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF18 0x000000FF
+#define HOST_SLCHOST_CONF18_M ((HOST_SLCHOST_CONF18_V)<<(HOST_SLCHOST_CONF18_S))
+#define HOST_SLCHOST_CONF18_V 0xFF
+#define HOST_SLCHOST_CONF18_S 16
+/* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: SLC timeout enable*/
+#define HOST_SLCHOST_CONF17 0x000000FF
+#define HOST_SLCHOST_CONF17_M ((HOST_SLCHOST_CONF17_V)<<(HOST_SLCHOST_CONF17_S))
+#define HOST_SLCHOST_CONF17_V 0xFF
+#define HOST_SLCHOST_CONF17_S 8
+/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */
+/*description: SLC timeout value*/
+#define HOST_SLCHOST_CONF16 0x000000FF
+#define HOST_SLCHOST_CONF16_M ((HOST_SLCHOST_CONF16_V)<<(HOST_SLCHOST_CONF16_S))
+#define HOST_SLCHOST_CONF16_V 0xFF
+#define HOST_SLCHOST_CONF16_S 0
+
+#define HOST_SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80)
+/* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF23 0x000000FF
+#define HOST_SLCHOST_CONF23_M ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S))
+#define HOST_SLCHOST_CONF23_V 0xFF
+#define HOST_SLCHOST_CONF23_S 24
+/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF22 0x000000FF
+#define HOST_SLCHOST_CONF22_M ((HOST_SLCHOST_CONF22_V)<<(HOST_SLCHOST_CONF22_S))
+#define HOST_SLCHOST_CONF22_V 0xFF
+#define HOST_SLCHOST_CONF22_S 16
+/* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF21 0x000000FF
+#define HOST_SLCHOST_CONF21_M ((HOST_SLCHOST_CONF21_V)<<(HOST_SLCHOST_CONF21_S))
+#define HOST_SLCHOST_CONF21_V 0xFF
+#define HOST_SLCHOST_CONF21_S 8
+/* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF20 0x000000FF
+#define HOST_SLCHOST_CONF20_M ((HOST_SLCHOST_CONF20_V)<<(HOST_SLCHOST_CONF20_S))
+#define HOST_SLCHOST_CONF20_V 0xFF
+#define HOST_SLCHOST_CONF20_S 0
+
+#define HOST_SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84)
+
+#define HOST_SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88)
+/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF27 0x000000FF
+#define HOST_SLCHOST_CONF27_M ((HOST_SLCHOST_CONF27_V)<<(HOST_SLCHOST_CONF27_S))
+#define HOST_SLCHOST_CONF27_V 0xFF
+#define HOST_SLCHOST_CONF27_S 24
+/* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF26 0x000000FF
+#define HOST_SLCHOST_CONF26_M ((HOST_SLCHOST_CONF26_V)<<(HOST_SLCHOST_CONF26_S))
+#define HOST_SLCHOST_CONF26_V 0xFF
+#define HOST_SLCHOST_CONF26_S 16
+/* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF25 0x000000FF
+#define HOST_SLCHOST_CONF25_M ((HOST_SLCHOST_CONF25_V)<<(HOST_SLCHOST_CONF25_S))
+#define HOST_SLCHOST_CONF25_V 0xFF
+#define HOST_SLCHOST_CONF25_S 8
+/* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF24 0x000000FF
+#define HOST_SLCHOST_CONF24_M ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S))
+#define HOST_SLCHOST_CONF24_V 0xFF
+#define HOST_SLCHOST_CONF24_S 0
+
+#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C)
+/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF31 0x000000FF
+#define HOST_SLCHOST_CONF31_M ((HOST_SLCHOST_CONF31_V)<<(HOST_SLCHOST_CONF31_S))
+#define HOST_SLCHOST_CONF31_V 0xFF
+#define HOST_SLCHOST_CONF31_S 24
+/* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF30 0x000000FF
+#define HOST_SLCHOST_CONF30_M ((HOST_SLCHOST_CONF30_V)<<(HOST_SLCHOST_CONF30_S))
+#define HOST_SLCHOST_CONF30_V 0xFF
+#define HOST_SLCHOST_CONF30_S 16
+/* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF29 0x000000FF
+#define HOST_SLCHOST_CONF29_M ((HOST_SLCHOST_CONF29_V)<<(HOST_SLCHOST_CONF29_S))
+#define HOST_SLCHOST_CONF29_V 0xFF
+#define HOST_SLCHOST_CONF29_S 8
+/* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF28 0x000000FF
+#define HOST_SLCHOST_CONF28_M ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S))
+#define HOST_SLCHOST_CONF28_V 0xFF
+#define HOST_SLCHOST_CONF28_S 0
+
+#define HOST_SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90)
+/* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN0 0x000FFFFF
+#define HOST_HOSTSLC0_LEN0_M ((HOST_HOSTSLC0_LEN0_V)<<(HOST_HOSTSLC0_LEN0_S))
+#define HOST_HOSTSLC0_LEN0_V 0xFFFFF
+#define HOST_HOSTSLC0_LEN0_S 0
+
+#define HOST_SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94)
+/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN1 0x000FFFFF
+#define HOST_HOSTSLC0_LEN1_M ((HOST_HOSTSLC0_LEN1_V)<<(HOST_HOSTSLC0_LEN1_S))
+#define HOST_HOSTSLC0_LEN1_V 0xFFFFF
+#define HOST_HOSTSLC0_LEN1_S 0
+
+#define HOST_SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98)
+/* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN2 0x000FFFFF
+#define HOST_HOSTSLC0_LEN2_M ((HOST_HOSTSLC0_LEN2_V)<<(HOST_HOSTSLC0_LEN2_S))
+#define HOST_HOSTSLC0_LEN2_V 0xFFFFF
+#define HOST_HOSTSLC0_LEN2_S 0
+
+#define HOST_SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9C)
+/* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF35 0x000000FF
+#define HOST_SLCHOST_CONF35_M ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S))
+#define HOST_SLCHOST_CONF35_V 0xFF
+#define HOST_SLCHOST_CONF35_S 24
+/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF34 0x000000FF
+#define HOST_SLCHOST_CONF34_M ((HOST_SLCHOST_CONF34_V)<<(HOST_SLCHOST_CONF34_S))
+#define HOST_SLCHOST_CONF34_V 0xFF
+#define HOST_SLCHOST_CONF34_S 16
+/* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF33 0x000000FF
+#define HOST_SLCHOST_CONF33_M ((HOST_SLCHOST_CONF33_V)<<(HOST_SLCHOST_CONF33_S))
+#define HOST_SLCHOST_CONF33_V 0xFF
+#define HOST_SLCHOST_CONF33_S 8
+/* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF32 0x000000FF
+#define HOST_SLCHOST_CONF32_M ((HOST_SLCHOST_CONF32_V)<<(HOST_SLCHOST_CONF32_S))
+#define HOST_SLCHOST_CONF32_V 0xFF
+#define HOST_SLCHOST_CONF32_S 0
+
+#define HOST_SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xA0)
+/* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF39 0x000000FF
+#define HOST_SLCHOST_CONF39_M ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S))
+#define HOST_SLCHOST_CONF39_V 0xFF
+#define HOST_SLCHOST_CONF39_S 24
+/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF38 0x000000FF
+#define HOST_SLCHOST_CONF38_M ((HOST_SLCHOST_CONF38_V)<<(HOST_SLCHOST_CONF38_S))
+#define HOST_SLCHOST_CONF38_V 0xFF
+#define HOST_SLCHOST_CONF38_S 16
+/* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF37 0x000000FF
+#define HOST_SLCHOST_CONF37_M ((HOST_SLCHOST_CONF37_V)<<(HOST_SLCHOST_CONF37_S))
+#define HOST_SLCHOST_CONF37_V 0xFF
+#define HOST_SLCHOST_CONF37_S 8
+/* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF36 0x000000FF
+#define HOST_SLCHOST_CONF36_M ((HOST_SLCHOST_CONF36_V)<<(HOST_SLCHOST_CONF36_S))
+#define HOST_SLCHOST_CONF36_V 0xFF
+#define HOST_SLCHOST_CONF36_S 0
+
+#define HOST_SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xA4)
+/* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF43 0x000000FF
+#define HOST_SLCHOST_CONF43_M ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S))
+#define HOST_SLCHOST_CONF43_V 0xFF
+#define HOST_SLCHOST_CONF43_S 24
+/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF42 0x000000FF
+#define HOST_SLCHOST_CONF42_M ((HOST_SLCHOST_CONF42_V)<<(HOST_SLCHOST_CONF42_S))
+#define HOST_SLCHOST_CONF42_V 0xFF
+#define HOST_SLCHOST_CONF42_S 16
+/* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF41 0x000000FF
+#define HOST_SLCHOST_CONF41_M ((HOST_SLCHOST_CONF41_V)<<(HOST_SLCHOST_CONF41_S))
+#define HOST_SLCHOST_CONF41_V 0xFF
+#define HOST_SLCHOST_CONF41_S 8
+/* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF40 0x000000FF
+#define HOST_SLCHOST_CONF40_M ((HOST_SLCHOST_CONF40_V)<<(HOST_SLCHOST_CONF40_S))
+#define HOST_SLCHOST_CONF40_V 0xFF
+#define HOST_SLCHOST_CONF40_S 0
+
+#define HOST_SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xA8)
+/* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF47 0x000000FF
+#define HOST_SLCHOST_CONF47_M ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S))
+#define HOST_SLCHOST_CONF47_V 0xFF
+#define HOST_SLCHOST_CONF47_S 24
+/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF46 0x000000FF
+#define HOST_SLCHOST_CONF46_M ((HOST_SLCHOST_CONF46_V)<<(HOST_SLCHOST_CONF46_S))
+#define HOST_SLCHOST_CONF46_V 0xFF
+#define HOST_SLCHOST_CONF46_S 16
+/* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF45 0x000000FF
+#define HOST_SLCHOST_CONF45_M ((HOST_SLCHOST_CONF45_V)<<(HOST_SLCHOST_CONF45_S))
+#define HOST_SLCHOST_CONF45_V 0xFF
+#define HOST_SLCHOST_CONF45_S 8
+/* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF44 0x000000FF
+#define HOST_SLCHOST_CONF44_M ((HOST_SLCHOST_CONF44_V)<<(HOST_SLCHOST_CONF44_S))
+#define HOST_SLCHOST_CONF44_V 0xFF
+#define HOST_SLCHOST_CONF44_S 0
+
+#define HOST_SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xAC)
+/* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF51 0x000000FF
+#define HOST_SLCHOST_CONF51_M ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S))
+#define HOST_SLCHOST_CONF51_V 0xFF
+#define HOST_SLCHOST_CONF51_S 24
+/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF50 0x000000FF
+#define HOST_SLCHOST_CONF50_M ((HOST_SLCHOST_CONF50_V)<<(HOST_SLCHOST_CONF50_S))
+#define HOST_SLCHOST_CONF50_V 0xFF
+#define HOST_SLCHOST_CONF50_S 16
+/* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF49 0x000000FF
+#define HOST_SLCHOST_CONF49_M ((HOST_SLCHOST_CONF49_V)<<(HOST_SLCHOST_CONF49_S))
+#define HOST_SLCHOST_CONF49_V 0xFF
+#define HOST_SLCHOST_CONF49_S 8
+/* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF48 0x000000FF
+#define HOST_SLCHOST_CONF48_M ((HOST_SLCHOST_CONF48_V)<<(HOST_SLCHOST_CONF48_S))
+#define HOST_SLCHOST_CONF48_V 0xFF
+#define HOST_SLCHOST_CONF48_S 0
+
+#define HOST_SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xB0)
+/* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF55 0x000000FF
+#define HOST_SLCHOST_CONF55_M ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S))
+#define HOST_SLCHOST_CONF55_V 0xFF
+#define HOST_SLCHOST_CONF55_S 24
+/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF54 0x000000FF
+#define HOST_SLCHOST_CONF54_M ((HOST_SLCHOST_CONF54_V)<<(HOST_SLCHOST_CONF54_S))
+#define HOST_SLCHOST_CONF54_V 0xFF
+#define HOST_SLCHOST_CONF54_S 16
+/* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF53 0x000000FF
+#define HOST_SLCHOST_CONF53_M ((HOST_SLCHOST_CONF53_V)<<(HOST_SLCHOST_CONF53_S))
+#define HOST_SLCHOST_CONF53_V 0xFF
+#define HOST_SLCHOST_CONF53_S 8
+/* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF52 0x000000FF
+#define HOST_SLCHOST_CONF52_M ((HOST_SLCHOST_CONF52_V)<<(HOST_SLCHOST_CONF52_S))
+#define HOST_SLCHOST_CONF52_V 0xFF
+#define HOST_SLCHOST_CONF52_S 0
+
+#define HOST_SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xB4)
+/* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF59 0x000000FF
+#define HOST_SLCHOST_CONF59_M ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S))
+#define HOST_SLCHOST_CONF59_V 0xFF
+#define HOST_SLCHOST_CONF59_S 24
+/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF58 0x000000FF
+#define HOST_SLCHOST_CONF58_M ((HOST_SLCHOST_CONF58_V)<<(HOST_SLCHOST_CONF58_S))
+#define HOST_SLCHOST_CONF58_V 0xFF
+#define HOST_SLCHOST_CONF58_S 16
+/* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF57 0x000000FF
+#define HOST_SLCHOST_CONF57_M ((HOST_SLCHOST_CONF57_V)<<(HOST_SLCHOST_CONF57_S))
+#define HOST_SLCHOST_CONF57_V 0xFF
+#define HOST_SLCHOST_CONF57_S 8
+/* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF56 0x000000FF
+#define HOST_SLCHOST_CONF56_M ((HOST_SLCHOST_CONF56_V)<<(HOST_SLCHOST_CONF56_S))
+#define HOST_SLCHOST_CONF56_V 0xFF
+#define HOST_SLCHOST_CONF56_S 0
+
+#define HOST_SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xB8)
+/* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF63 0x000000FF
+#define HOST_SLCHOST_CONF63_M ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S))
+#define HOST_SLCHOST_CONF63_V 0xFF
+#define HOST_SLCHOST_CONF63_S 24
+/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF62 0x000000FF
+#define HOST_SLCHOST_CONF62_M ((HOST_SLCHOST_CONF62_V)<<(HOST_SLCHOST_CONF62_S))
+#define HOST_SLCHOST_CONF62_V 0xFF
+#define HOST_SLCHOST_CONF62_S 16
+/* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF61 0x000000FF
+#define HOST_SLCHOST_CONF61_M ((HOST_SLCHOST_CONF61_V)<<(HOST_SLCHOST_CONF61_S))
+#define HOST_SLCHOST_CONF61_V 0xFF
+#define HOST_SLCHOST_CONF61_S 8
+/* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF60 0x000000FF
+#define HOST_SLCHOST_CONF60_M ((HOST_SLCHOST_CONF60_V)<<(HOST_SLCHOST_CONF60_S))
+#define HOST_SLCHOST_CONF60_V 0xFF
+#define HOST_SLCHOST_CONF60_S 0
+
+#define HOST_SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xBC)
+/* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM0_M ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S))
+#define HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM0_S 0
+
+#define HOST_SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xC0)
+/* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLCHOST_CHECK_SUM1 0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM1_M ((HOST_SLCHOST_CHECK_SUM1_V)<<(HOST_SLCHOST_CHECK_SUM1_S))
+#define HOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM1_S 0
+
+#define HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0xC4)
+/* HOST_SLC1_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_EOF 0x0000000F
+#define HOST_SLC1_RX_PF_EOF_M ((HOST_SLC1_RX_PF_EOF_V)<<(HOST_SLC1_RX_PF_EOF_S))
+#define HOST_SLC1_RX_PF_EOF_V 0xF
+#define HOST_SLC1_RX_PF_EOF_S 28
+/* HOST_HOSTSLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define HOST_HOSTSLC1_TOKEN1 0x00000FFF
+#define HOST_HOSTSLC1_TOKEN1_M ((HOST_HOSTSLC1_TOKEN1_V)<<(HOST_HOSTSLC1_TOKEN1_S))
+#define HOST_HOSTSLC1_TOKEN1_V 0xFFF
+#define HOST_HOSTSLC1_TOKEN1_S 16
+/* HOST_SLC1_RX_PF_VALID : RO ;bitpos:[12] ;default: 1'h0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_VALID (BIT(12))
+#define HOST_SLC1_RX_PF_VALID_M (BIT(12))
+#define HOST_SLC1_RX_PF_VALID_V 0x1
+#define HOST_SLC1_RX_PF_VALID_S 12
+/* HOST_SLC1_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0 0x00000FFF
+#define HOST_SLC1_TOKEN0_M ((HOST_SLC1_TOKEN0_V)<<(HOST_SLC1_TOKEN0_S))
+#define HOST_SLC1_TOKEN0_V 0xFFF
+#define HOST_SLC1_TOKEN0_S 0
+
+#define HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xC8)
+/* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN1_WD 0x00000FFF
+#define HOST_SLC0HOST_TOKEN1_WD_M ((HOST_SLC0HOST_TOKEN1_WD_V)<<(HOST_SLC0HOST_TOKEN1_WD_S))
+#define HOST_SLC0HOST_TOKEN1_WD_V 0xFFF
+#define HOST_SLC0HOST_TOKEN1_WD_S 16
+/* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN0_WD 0x00000FFF
+#define HOST_SLC0HOST_TOKEN0_WD_M ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S))
+#define HOST_SLC0HOST_TOKEN0_WD_V 0xFFF
+#define HOST_SLC0HOST_TOKEN0_WD_S 0
+
+#define HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xCC)
+/* HOST_SLC1HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC1HOST_TOKEN1_WD 0x00000FFF
+#define HOST_SLC1HOST_TOKEN1_WD_M ((HOST_SLC1HOST_TOKEN1_WD_V)<<(HOST_SLC1HOST_TOKEN1_WD_S))
+#define HOST_SLC1HOST_TOKEN1_WD_V 0xFFF
+#define HOST_SLC1HOST_TOKEN1_WD_S 16
+/* HOST_SLC1HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC1HOST_TOKEN0_WD 0x00000FFF
+#define HOST_SLC1HOST_TOKEN0_WD_M ((HOST_SLC1HOST_TOKEN0_WD_V)<<(HOST_SLC1HOST_TOKEN0_WD_S))
+#define HOST_SLC1HOST_TOKEN0_WD_V 0xFFF
+#define HOST_SLC1HOST_TOKEN0_WD_S 0
+
+#define HOST_SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xD0)
+/* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_LEN_WR (BIT(8))
+#define HOST_SLC0HOST_LEN_WR_M (BIT(8))
+#define HOST_SLC0HOST_LEN_WR_V 0x1
+#define HOST_SLC0HOST_LEN_WR_S 8
+/* HOST_SLC1HOST_TOKEN1_WR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TOKEN1_WR (BIT(7))
+#define HOST_SLC1HOST_TOKEN1_WR_M (BIT(7))
+#define HOST_SLC1HOST_TOKEN1_WR_V 0x1
+#define HOST_SLC1HOST_TOKEN1_WR_S 7
+/* HOST_SLC1HOST_TOKEN0_WR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TOKEN0_WR (BIT(6))
+#define HOST_SLC1HOST_TOKEN0_WR_M (BIT(6))
+#define HOST_SLC1HOST_TOKEN0_WR_V 0x1
+#define HOST_SLC1HOST_TOKEN0_WR_S 6
+/* HOST_SLC1HOST_TOKEN1_DEC : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TOKEN1_DEC (BIT(5))
+#define HOST_SLC1HOST_TOKEN1_DEC_M (BIT(5))
+#define HOST_SLC1HOST_TOKEN1_DEC_V 0x1
+#define HOST_SLC1HOST_TOKEN1_DEC_S 5
+/* HOST_SLC1HOST_TOKEN0_DEC : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TOKEN0_DEC (BIT(4))
+#define HOST_SLC1HOST_TOKEN0_DEC_M (BIT(4))
+#define HOST_SLC1HOST_TOKEN0_DEC_V 0x1
+#define HOST_SLC1HOST_TOKEN0_DEC_S 4
+/* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN1_WR (BIT(3))
+#define HOST_SLC0HOST_TOKEN1_WR_M (BIT(3))
+#define HOST_SLC0HOST_TOKEN1_WR_V 0x1
+#define HOST_SLC0HOST_TOKEN1_WR_S 3
+/* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN0_WR (BIT(2))
+#define HOST_SLC0HOST_TOKEN0_WR_M (BIT(2))
+#define HOST_SLC0HOST_TOKEN0_WR_V 0x1
+#define HOST_SLC0HOST_TOKEN0_WR_S 2
+/* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN1_DEC (BIT(1))
+#define HOST_SLC0HOST_TOKEN1_DEC_M (BIT(1))
+#define HOST_SLC0HOST_TOKEN1_DEC_V 0x1
+#define HOST_SLC0HOST_TOKEN1_DEC_S 1
+/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN0_DEC (BIT(0))
+#define HOST_SLC0HOST_TOKEN0_DEC_M (BIT(0))
+#define HOST_SLC0HOST_TOKEN0_DEC_V 0x1
+#define HOST_SLC0HOST_TOKEN0_DEC_S 0
+
+#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4)
+/* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_CLR (BIT(25))
+#define HOST_GPIO_SDIO_INT_CLR_M (BIT(25))
+#define HOST_GPIO_SDIO_INT_CLR_V 0x1
+#define HOST_GPIO_SDIO_INT_CLR_S 25
+/* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24
+/* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23
+/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_CLR (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_CLR_M (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_CLR_V 0x1
+#define HOST_SLC0_EXT_BIT3_INT_CLR_S 22
+/* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_CLR (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_CLR_M (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_CLR_V 0x1
+#define HOST_SLC0_EXT_BIT2_INT_CLR_S 21
+/* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_CLR (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_CLR_M (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_CLR_V 0x1
+#define HOST_SLC0_EXT_BIT1_INT_CLR_S 20
+/* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_CLR_M (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_CLR_V 0x1
+#define HOST_SLC0_EXT_BIT0_INT_CLR_S 19
+/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_M (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_V 0x1
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_S 18
+/* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_CLR (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_CLR_M (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_CLR_V 0x1
+#define HOST_SLC0_TX_OVF_INT_CLR_S 17
+/* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_CLR (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_CLR_M (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_CLR_V 0x1
+#define HOST_SLC0_RX_UDF_INT_CLR_S 16
+/* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_CLR (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_CLR_M (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_CLR_V 0x1
+#define HOST_SLC0HOST_TX_START_INT_CLR_S 15
+/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_CLR (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_CLR_M (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_CLR_V 0x1
+#define HOST_SLC0HOST_RX_START_INT_CLR_S 14
+/* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_M (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_V 0x1
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_S 13
+/* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_M (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_V 0x1
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_S 12
+/* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11
+/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10
+/* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9
+/* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8
+/* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7
+/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S 6
+/* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S 5
+/* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S 4
+/* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3
+/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S 2
+/* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S 1
+/* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S 0
+
+#define HOST_SLC1HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD8)
+/* HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x1
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25
+/* HOST_SLC1_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_M (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x1
+#define HOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24
+/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x1
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23
+/* HOST_SLC1_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT3_INT_CLR (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_CLR_M (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_CLR_V 0x1
+#define HOST_SLC1_EXT_BIT3_INT_CLR_S 22
+/* HOST_SLC1_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT2_INT_CLR (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_CLR_M (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_CLR_V 0x1
+#define HOST_SLC1_EXT_BIT2_INT_CLR_S 21
+/* HOST_SLC1_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT1_INT_CLR (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_CLR_M (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_CLR_V 0x1
+#define HOST_SLC1_EXT_BIT1_INT_CLR_S 20
+/* HOST_SLC1_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT0_INT_CLR (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_CLR_M (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_CLR_V 0x1
+#define HOST_SLC1_EXT_BIT0_INT_CLR_S 19
+/* HOST_SLC1_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_CLR_M (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_CLR_V 0x1
+#define HOST_SLC1_RX_PF_VALID_INT_CLR_S 18
+/* HOST_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TX_OVF_INT_CLR (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_CLR_M (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_CLR_V 0x1
+#define HOST_SLC1_TX_OVF_INT_CLR_S 17
+/* HOST_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_UDF_INT_CLR (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_CLR_M (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_CLR_V 0x1
+#define HOST_SLC1_RX_UDF_INT_CLR_S 16
+/* HOST_SLC1HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TX_START_INT_CLR (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_CLR_M (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_CLR_V 0x1
+#define HOST_SLC1HOST_TX_START_INT_CLR_S 15
+/* HOST_SLC1HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_START_INT_CLR (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_CLR_M (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_CLR_V 0x1
+#define HOST_SLC1HOST_RX_START_INT_CLR_S 14
+/* HOST_SLC1HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_CLR_M (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_CLR_V 0x1
+#define HOST_SLC1HOST_RX_EOF_INT_CLR_S 13
+/* HOST_SLC1HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_CLR_M (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_CLR_V 0x1
+#define HOST_SLC1HOST_RX_SOF_INT_CLR_S 12
+/* HOST_SLC1_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_M (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x1
+#define HOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11
+/* HOST_SLC1_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_M (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x1
+#define HOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10
+/* HOST_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_M (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x1
+#define HOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9
+/* HOST_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_M (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x1
+#define HOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8
+/* HOST_SLC1_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_CLR_M (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT7_INT_CLR_S 7
+/* HOST_SLC1_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_CLR_M (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT6_INT_CLR_S 6
+/* HOST_SLC1_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_CLR_M (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT5_INT_CLR_S 5
+/* HOST_SLC1_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_CLR_M (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT4_INT_CLR_S 4
+/* HOST_SLC1_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_CLR_M (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT3_INT_CLR_S 3
+/* HOST_SLC1_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_CLR_M (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT2_INT_CLR_S 2
+/* HOST_SLC1_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_CLR_M (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT1_INT_CLR_S 1
+/* HOST_SLC1_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_CLR_M (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x1
+#define HOST_SLC1_TOHOST_BIT0_INT_CLR_S 0
+
+#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC)
+/* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25))
+#define HOST_FN1_GPIO_SDIO_INT_ENA_M (BIT(25))
+#define HOST_FN1_GPIO_SDIO_INT_ENA_V 0x1
+#define HOST_FN1_GPIO_SDIO_INT_ENA_S 25
+/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24))
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24))
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24
+/* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23))
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23))
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23
+/* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22))
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (BIT(22))
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22
+/* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21))
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (BIT(21))
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21
+/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20))
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (BIT(20))
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20
+/* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19))
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (BIT(19))
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19
+/* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18))
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18))
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18
+/* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17))
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M (BIT(17))
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17
+/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16))
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M (BIT(16))
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S 16
+/* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15))
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M (BIT(15))
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x1
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15
+/* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14))
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M (BIT(14))
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x1
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14
+/* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13))
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13))
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x1
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13
+/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12))
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12))
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x1
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12
+/* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11))
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11))
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11
+/* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10))
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10))
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10
+/* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9))
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9))
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9
+/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8))
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8))
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8
+/* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7))
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7))
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7
+/* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6))
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6))
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6
+/* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5))
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5))
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5
+/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4))
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4))
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4
+/* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3))
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3))
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3
+/* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2))
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2))
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2
+/* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1))
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1))
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1
+/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0))
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0))
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x1
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0
+
+#define HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xE0)
+/* HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25))
+#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (BIT(25))
+#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25
+/* HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24))
+#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (BIT(24))
+#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24
+/* HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23))
+#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (BIT(23))
+#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23
+/* HOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22))
+#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (BIT(22))
+#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22
+/* HOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21))
+#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (BIT(21))
+#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21
+/* HOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20))
+#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (BIT(20))
+#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20
+/* HOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19))
+#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (BIT(19))
+#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19
+/* HOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18))
+#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (BIT(18))
+#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18
+/* HOST_FN1_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17))
+#define HOST_FN1_SLC1_TX_OVF_INT_ENA_M (BIT(17))
+#define HOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TX_OVF_INT_ENA_S 17
+/* HOST_FN1_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16))
+#define HOST_FN1_SLC1_RX_UDF_INT_ENA_M (BIT(16))
+#define HOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_RX_UDF_INT_ENA_S 16
+/* HOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15))
+#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_M (BIT(15))
+#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x1
+#define HOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15
+/* HOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14))
+#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_M (BIT(14))
+#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x1
+#define HOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14
+/* HOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13))
+#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (BIT(13))
+#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x1
+#define HOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13
+/* HOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12))
+#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (BIT(12))
+#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x1
+#define HOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12
+/* HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11))
+#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (BIT(11))
+#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11
+/* HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10))
+#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (BIT(10))
+#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10
+/* HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9))
+#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(9))
+#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9
+/* HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8))
+#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(8))
+#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8
+/* HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7))
+#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (BIT(7))
+#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7
+/* HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6))
+#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (BIT(6))
+#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6
+/* HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5))
+#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (BIT(5))
+#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5
+/* HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4))
+#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (BIT(4))
+#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4
+/* HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3))
+#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (BIT(3))
+#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3
+/* HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2))
+#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (BIT(2))
+#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2
+/* HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1))
+#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (BIT(1))
+#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1
+/* HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0))
+#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (BIT(0))
+#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x1
+#define HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0
+
+#define HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xE4)
+/* HOST_FN2_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_GPIO_SDIO_INT_ENA (BIT(25))
+#define HOST_FN2_GPIO_SDIO_INT_ENA_M (BIT(25))
+#define HOST_FN2_GPIO_SDIO_INT_ENA_V 0x1
+#define HOST_FN2_GPIO_SDIO_INT_ENA_S 25
+/* HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24))
+#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24))
+#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24
+/* HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23))
+#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23))
+#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23
+/* HOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22))
+#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (BIT(22))
+#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22
+/* HOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21))
+#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (BIT(21))
+#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21
+/* HOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20))
+#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (BIT(20))
+#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20
+/* HOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19))
+#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (BIT(19))
+#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19
+/* HOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18))
+#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18))
+#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18
+/* HOST_FN2_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17))
+#define HOST_FN2_SLC0_TX_OVF_INT_ENA_M (BIT(17))
+#define HOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TX_OVF_INT_ENA_S 17
+/* HOST_FN2_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16))
+#define HOST_FN2_SLC0_RX_UDF_INT_ENA_M (BIT(16))
+#define HOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_RX_UDF_INT_ENA_S 16
+/* HOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15))
+#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_M (BIT(15))
+#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x1
+#define HOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15
+/* HOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14))
+#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_M (BIT(14))
+#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x1
+#define HOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14
+/* HOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13))
+#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13))
+#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x1
+#define HOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13
+/* HOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12))
+#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12))
+#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x1
+#define HOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12
+/* HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11))
+#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11))
+#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11
+/* HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10))
+#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10))
+#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10
+/* HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9))
+#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9))
+#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9
+/* HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8))
+#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8))
+#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8
+/* HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7))
+#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7))
+#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7
+/* HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6))
+#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6))
+#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6
+/* HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5))
+#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5))
+#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5
+/* HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4))
+#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4))
+#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4
+/* HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3))
+#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3))
+#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3
+/* HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2))
+#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2))
+#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2
+/* HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1))
+#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1))
+#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1
+/* HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0))
+#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0))
+#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x1
+#define HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0
+
+#define HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xE8)
+/* HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25))
+#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (BIT(25))
+#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25
+/* HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24))
+#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (BIT(24))
+#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24
+/* HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23))
+#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (BIT(23))
+#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23
+/* HOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22))
+#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (BIT(22))
+#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22
+/* HOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21))
+#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (BIT(21))
+#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21
+/* HOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20))
+#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (BIT(20))
+#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20
+/* HOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19))
+#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (BIT(19))
+#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19
+/* HOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18))
+#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (BIT(18))
+#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18
+/* HOST_FN2_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17))
+#define HOST_FN2_SLC1_TX_OVF_INT_ENA_M (BIT(17))
+#define HOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TX_OVF_INT_ENA_S 17
+/* HOST_FN2_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16))
+#define HOST_FN2_SLC1_RX_UDF_INT_ENA_M (BIT(16))
+#define HOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_RX_UDF_INT_ENA_S 16
+/* HOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15))
+#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_M (BIT(15))
+#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x1
+#define HOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15
+/* HOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14))
+#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_M (BIT(14))
+#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x1
+#define HOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14
+/* HOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13))
+#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (BIT(13))
+#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x1
+#define HOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13
+/* HOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12))
+#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (BIT(12))
+#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x1
+#define HOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12
+/* HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11))
+#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (BIT(11))
+#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11
+/* HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10))
+#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (BIT(10))
+#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10
+/* HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9))
+#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(9))
+#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9
+/* HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8))
+#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(8))
+#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8
+/* HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7))
+#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (BIT(7))
+#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7
+/* HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6))
+#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (BIT(6))
+#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6
+/* HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5))
+#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (BIT(5))
+#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5
+/* HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4))
+#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (BIT(4))
+#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4
+/* HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3))
+#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (BIT(3))
+#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3
+/* HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2))
+#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (BIT(2))
+#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2
+/* HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1))
+#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (BIT(1))
+#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1
+/* HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0))
+#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (BIT(0))
+#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x1
+#define HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0
+
+#define HOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xEC)
+/* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_ENA (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA_M (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA_V 0x1
+#define HOST_GPIO_SDIO_INT_ENA_S 25
+/* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24
+/* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23
+/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_ENA (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA_M (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA_V 0x1
+#define HOST_SLC0_EXT_BIT3_INT_ENA_S 22
+/* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_ENA (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA_M (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA_V 0x1
+#define HOST_SLC0_EXT_BIT2_INT_ENA_S 21
+/* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_ENA (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA_M (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA_V 0x1
+#define HOST_SLC0_EXT_BIT1_INT_ENA_S 20
+/* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA_M (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA_V 0x1
+#define HOST_SLC0_EXT_BIT0_INT_ENA_S 19
+/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_V 0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_S 18
+/* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_ENA (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA_M (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA_V 0x1
+#define HOST_SLC0_TX_OVF_INT_ENA_S 17
+/* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_ENA (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA_M (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA_V 0x1
+#define HOST_SLC0_RX_UDF_INT_ENA_S 16
+/* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_ENA (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA_M (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA_V 0x1
+#define HOST_SLC0HOST_TX_START_INT_ENA_S 15
+/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_ENA (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA_M (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA_V 0x1
+#define HOST_SLC0HOST_RX_START_INT_ENA_S 14
+/* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_V 0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_S 13
+/* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_V 0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_S 12
+/* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11
+/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10
+/* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9
+/* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8
+/* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7
+/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S 6
+/* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S 5
+/* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S 4
+/* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3
+/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S 2
+/* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S 1
+/* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S 0
+
+#define HOST_SLC1HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xF0)
+/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25
+/* HOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_M (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x1
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24
+/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x1
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23
+/* HOST_SLC1_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT3_INT_ENA (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_ENA_M (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_ENA_V 0x1
+#define HOST_SLC1_EXT_BIT3_INT_ENA_S 22
+/* HOST_SLC1_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT2_INT_ENA (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_ENA_M (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_ENA_V 0x1
+#define HOST_SLC1_EXT_BIT2_INT_ENA_S 21
+/* HOST_SLC1_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT1_INT_ENA (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_ENA_M (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_ENA_V 0x1
+#define HOST_SLC1_EXT_BIT1_INT_ENA_S 20
+/* HOST_SLC1_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT0_INT_ENA (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_ENA_M (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_ENA_V 0x1
+#define HOST_SLC1_EXT_BIT0_INT_ENA_S 19
+/* HOST_SLC1_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_ENA_M (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_ENA_V 0x1
+#define HOST_SLC1_RX_PF_VALID_INT_ENA_S 18
+/* HOST_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TX_OVF_INT_ENA (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_ENA_M (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_ENA_V 0x1
+#define HOST_SLC1_TX_OVF_INT_ENA_S 17
+/* HOST_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_UDF_INT_ENA (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_ENA_M (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_ENA_V 0x1
+#define HOST_SLC1_RX_UDF_INT_ENA_S 16
+/* HOST_SLC1HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TX_START_INT_ENA (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_ENA_M (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_ENA_V 0x1
+#define HOST_SLC1HOST_TX_START_INT_ENA_S 15
+/* HOST_SLC1HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_START_INT_ENA (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_ENA_M (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_ENA_V 0x1
+#define HOST_SLC1HOST_RX_START_INT_ENA_S 14
+/* HOST_SLC1HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_ENA_M (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_ENA_V 0x1
+#define HOST_SLC1HOST_RX_EOF_INT_ENA_S 13
+/* HOST_SLC1HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_ENA_M (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_ENA_V 0x1
+#define HOST_SLC1HOST_RX_SOF_INT_ENA_S 12
+/* HOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_M (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x1
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11
+/* HOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_M (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x1
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10
+/* HOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9
+/* HOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8
+/* HOST_SLC1_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA_M (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA_S 7
+/* HOST_SLC1_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA_M (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA_S 6
+/* HOST_SLC1_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA_M (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA_S 5
+/* HOST_SLC1_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA_M (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA_S 4
+/* HOST_SLC1_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA_M (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA_S 3
+/* HOST_SLC1_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA_M (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA_S 2
+/* HOST_SLC1_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA_M (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA_S 1
+/* HOST_SLC1_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA_M (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x1
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA_S 0
+
+#define HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF4)
+/* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_INFOR 0x000FFFFF
+#define HOST_SLC0HOST_RX_INFOR_M ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S))
+#define HOST_SLC0HOST_RX_INFOR_V 0xFFFFF
+#define HOST_SLC0HOST_RX_INFOR_S 0
+
+#define HOST_SLC1HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF8)
+/* HOST_SLC1HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_INFOR 0x000FFFFF
+#define HOST_SLC1HOST_RX_INFOR_M ((HOST_SLC1HOST_RX_INFOR_V)<<(HOST_SLC1HOST_RX_INFOR_S))
+#define HOST_SLC1HOST_RX_INFOR_V 0xFFFFF
+#define HOST_SLC1HOST_RX_INFOR_S 0
+
+#define HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xFC)
+/* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_LEN_WD 0xFFFFFFFF
+#define HOST_SLC0HOST_LEN_WD_M ((HOST_SLC0HOST_LEN_WD_V)<<(HOST_SLC0HOST_LEN_WD_S))
+#define HOST_SLC0HOST_LEN_WD_V 0xFFFFFFFF
+#define HOST_SLC0HOST_LEN_WD_S 0
+
+#define HOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100)
+/* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_WDATA 0xFFFFFFFF
+#define HOST_SLC_APBWIN_WDATA_M ((HOST_SLC_APBWIN_WDATA_V)<<(HOST_SLC_APBWIN_WDATA_S))
+#define HOST_SLC_APBWIN_WDATA_V 0xFFFFFFFF
+#define HOST_SLC_APBWIN_WDATA_S 0
+
+#define HOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104)
+/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_START (BIT(29))
+#define HOST_SLC_APBWIN_START_M (BIT(29))
+#define HOST_SLC_APBWIN_START_V 0x1
+#define HOST_SLC_APBWIN_START_S 29
+/* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_WR (BIT(28))
+#define HOST_SLC_APBWIN_WR_M (BIT(28))
+#define HOST_SLC_APBWIN_WR_V 0x1
+#define HOST_SLC_APBWIN_WR_S 28
+/* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_ADDR 0x0FFFFFFF
+#define HOST_SLC_APBWIN_ADDR_M ((HOST_SLC_APBWIN_ADDR_V)<<(HOST_SLC_APBWIN_ADDR_S))
+#define HOST_SLC_APBWIN_ADDR_V 0xFFFFFFF
+#define HOST_SLC_APBWIN_ADDR_S 0
+
+#define HOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108)
+/* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_RDATA 0xFFFFFFFF
+#define HOST_SLC_APBWIN_RDATA_M ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S))
+#define HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFF
+#define HOST_SLC_APBWIN_RDATA_S 0
+
+#define HOST_SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10C)
+/* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */
+/*description: */
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FF
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT6_CLRADDR_S))
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x1FF
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9
+/* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */
+/*description: */
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FF
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT7_CLRADDR_S))
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x1FF
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0
+
+#define HOST_SLCHOST_RDCLR1_REG (DR_REG_SLCHOST_BASE + 0x110)
+/* HOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */
+/*description: */
+#define HOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FF
+#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC1_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC1_BIT6_CLRADDR_S))
+#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x1FF
+#define HOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9
+/* HOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h1e0 ; */
+/*description: */
+#define HOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FF
+#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC1_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC1_BIT7_CLRADDR_S))
+#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x1FF
+#define HOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0
+
+#define HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114)
+/* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_ENA1 (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA1_M (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA1_V 0x1
+#define HOST_GPIO_SDIO_INT_ENA1_S 25
+/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24
+/* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23
+/* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_M (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_V 0x1
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_S 22
+/* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_M (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x1
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_S 21
+/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_M (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_V 0x1
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_S 20
+/* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_M (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_V 0x1
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_S 19
+/* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S 18
+/* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA1_M (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA1_V 0x1
+#define HOST_SLC0_TX_OVF_INT_ENA1_S 17
+/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA1_M (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA1_V 0x1
+#define HOST_SLC0_RX_UDF_INT_ENA1_S 16
+/* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA1_M (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA1_V 0x1
+#define HOST_SLC0HOST_TX_START_INT_ENA1_S 15
+/* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA1_M (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA1_V 0x1
+#define HOST_SLC0HOST_RX_START_INT_ENA1_S 14
+/* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13
+/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S 12
+/* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11
+/* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10
+/* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9
+/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8
+/* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7
+/* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6
+/* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5
+/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4
+/* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3
+/* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2
+/* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1
+/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0
+
+#define HOST_SLC1HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x118)
+/* HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (BIT(25))
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x1
+#define HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25
+/* HOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (BIT(24))
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x1
+#define HOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24
+/* HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (BIT(23))
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x1
+#define HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23
+/* HOST_SLC1_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_ENA1_M (BIT(22))
+#define HOST_SLC1_EXT_BIT3_INT_ENA1_V 0x1
+#define HOST_SLC1_EXT_BIT3_INT_ENA1_S 22
+/* HOST_SLC1_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_ENA1_M (BIT(21))
+#define HOST_SLC1_EXT_BIT2_INT_ENA1_V 0x1
+#define HOST_SLC1_EXT_BIT2_INT_ENA1_S 21
+/* HOST_SLC1_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_ENA1_M (BIT(20))
+#define HOST_SLC1_EXT_BIT1_INT_ENA1_V 0x1
+#define HOST_SLC1_EXT_BIT1_INT_ENA1_S 20
+/* HOST_SLC1_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_ENA1_M (BIT(19))
+#define HOST_SLC1_EXT_BIT0_INT_ENA1_V 0x1
+#define HOST_SLC1_EXT_BIT0_INT_ENA1_S 19
+/* HOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_ENA1_M (BIT(18))
+#define HOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x1
+#define HOST_SLC1_RX_PF_VALID_INT_ENA1_S 18
+/* HOST_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TX_OVF_INT_ENA1 (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_ENA1_M (BIT(17))
+#define HOST_SLC1_TX_OVF_INT_ENA1_V 0x1
+#define HOST_SLC1_TX_OVF_INT_ENA1_S 17
+/* HOST_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_RX_UDF_INT_ENA1 (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_ENA1_M (BIT(16))
+#define HOST_SLC1_RX_UDF_INT_ENA1_V 0x1
+#define HOST_SLC1_RX_UDF_INT_ENA1_S 16
+/* HOST_SLC1HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_ENA1_M (BIT(15))
+#define HOST_SLC1HOST_TX_START_INT_ENA1_V 0x1
+#define HOST_SLC1HOST_TX_START_INT_ENA1_S 15
+/* HOST_SLC1HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_ENA1_M (BIT(14))
+#define HOST_SLC1HOST_RX_START_INT_ENA1_V 0x1
+#define HOST_SLC1HOST_RX_START_INT_ENA1_S 14
+/* HOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_ENA1_M (BIT(13))
+#define HOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x1
+#define HOST_SLC1HOST_RX_EOF_INT_ENA1_S 13
+/* HOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_ENA1_M (BIT(12))
+#define HOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x1
+#define HOST_SLC1HOST_RX_SOF_INT_ENA1_S 12
+/* HOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (BIT(11))
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x1
+#define HOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11
+/* HOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (BIT(10))
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x1
+#define HOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10
+/* HOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (BIT(9))
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x1
+#define HOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9
+/* HOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (BIT(8))
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x1
+#define HOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8
+/* HOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_M (BIT(7))
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7
+/* HOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_M (BIT(6))
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6
+/* HOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_M (BIT(5))
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5
+/* HOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_M (BIT(4))
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4
+/* HOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_M (BIT(3))
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3
+/* HOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_M (BIT(2))
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2
+/* HOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_M (BIT(1))
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1
+/* HOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_M (BIT(0))
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x1
+#define HOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0
+
+#define HOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178)
+/* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */
+/*description: */
+#define HOST_SLCHOST_DATE 0xFFFFFFFF
+#define HOST_SLCHOST_DATE_M ((HOST_SLCHOST_DATE_V)<<(HOST_SLCHOST_DATE_S))
+#define HOST_SLCHOST_DATE_V 0xFFFFFFFF
+#define HOST_SLCHOST_DATE_S 0
+
+#define HOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17C)
+/* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */
+/*description: */
+#define HOST_SLCHOST_ID 0xFFFFFFFF
+#define HOST_SLCHOST_ID_M ((HOST_SLCHOST_ID_V)<<(HOST_SLCHOST_ID_S))
+#define HOST_SLCHOST_ID_V 0xFFFFFFFF
+#define HOST_SLCHOST_ID_S 0
+
+#define HOST_SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1F0)
+/* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define HOST_HSPEED_CON_EN (BIT(27))
+#define HOST_HSPEED_CON_EN_M (BIT(27))
+#define HOST_HSPEED_CON_EN_V 0x1
+#define HOST_HSPEED_CON_EN_S 27
+/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SDIO_PAD_PULLUP (BIT(26))
+#define HOST_SDIO_PAD_PULLUP_M (BIT(26))
+#define HOST_SDIO_PAD_PULLUP_V 0x1
+#define HOST_SDIO_PAD_PULLUP_S 26
+/* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SDIO20_INT_DELAY (BIT(25))
+#define HOST_SDIO20_INT_DELAY_M (BIT(25))
+#define HOST_SDIO20_INT_DELAY_V 0x1
+#define HOST_SDIO20_INT_DELAY_S 25
+/* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_QUICK_IN 0x0000001F
+#define HOST_FRC_QUICK_IN_M ((HOST_FRC_QUICK_IN_V)<<(HOST_FRC_QUICK_IN_S))
+#define HOST_FRC_QUICK_IN_V 0x1F
+#define HOST_FRC_QUICK_IN_S 20
+/* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_POS_SAMP 0x0000001F
+#define HOST_FRC_POS_SAMP_M ((HOST_FRC_POS_SAMP_V)<<(HOST_FRC_POS_SAMP_S))
+#define HOST_FRC_POS_SAMP_V 0x1F
+#define HOST_FRC_POS_SAMP_S 15
+/* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_NEG_SAMP 0x0000001F
+#define HOST_FRC_NEG_SAMP_M ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S))
+#define HOST_FRC_NEG_SAMP_V 0x1F
+#define HOST_FRC_NEG_SAMP_S 10
+/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_SDIO20 0x0000001F
+#define HOST_FRC_SDIO20_M ((HOST_FRC_SDIO20_V)<<(HOST_FRC_SDIO20_S))
+#define HOST_FRC_SDIO20_V 0x1F
+#define HOST_FRC_SDIO20_S 5
+/* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_SDIO11 0x0000001F
+#define HOST_FRC_SDIO11_M ((HOST_FRC_SDIO11_V)<<(HOST_FRC_SDIO11_S))
+#define HOST_FRC_SDIO11_V 0x1F
+#define HOST_FRC_SDIO11_S 0
+
+#define HOST_SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1F4)
+/* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: */
+#define HOST_SDIO_QUICK_IN 0x0000001F
+#define HOST_SDIO_QUICK_IN_M ((HOST_SDIO_QUICK_IN_V)<<(HOST_SDIO_QUICK_IN_S))
+#define HOST_SDIO_QUICK_IN_V 0x1F
+#define HOST_SDIO_QUICK_IN_S 10
+/* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: */
+#define HOST_SDIO_NEG_SAMP 0x0000001F
+#define HOST_SDIO_NEG_SAMP_M ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S))
+#define HOST_SDIO_NEG_SAMP_V 0x1F
+#define HOST_SDIO_NEG_SAMP_S 5
+/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: */
+#define HOST_SDIO20_MODE 0x0000001F
+#define HOST_SDIO20_MODE_M ((HOST_SDIO20_MODE_V)<<(HOST_SDIO20_MODE_S))
+#define HOST_SDIO20_MODE_V 0x1F
+#define HOST_SDIO20_MODE_S 0
+
+
+
+
+#endif /*_SOC_HOST_REG_H_ */
+
+
--- /dev/null
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HOST_STRUCT_H_
+#define _SOC_HOST_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+ uint32_t reserved_0;
+ uint32_t reserved_4;
+ uint32_t reserved_8;
+ uint32_t reserved_c;
+ union {
+ struct {
+ uint32_t reserved0: 24;
+ uint32_t func2_int: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } func2_0;
+ union {
+ struct {
+ uint32_t func2_int_en: 1;
+ uint32_t reserved1: 31;
+ };
+ uint32_t val;
+ } func2_1;
+ uint32_t reserved_18;
+ uint32_t reserved_1c;
+ union {
+ struct {
+ uint32_t func1_mdstat: 1;
+ uint32_t reserved1: 31;
+ };
+ uint32_t val;
+ } func2_2;
+ uint32_t reserved_24;
+ uint32_t reserved_28;
+ uint32_t reserved_2c;
+ uint32_t reserved_30;
+ uint32_t gpio_status0; /**/
+ union {
+ struct {
+ uint32_t sdio_int1: 8;
+ uint32_t reserved8: 24;
+ };
+ uint32_t val;
+ } gpio_status1;
+ uint32_t gpio_in0; /**/
+ union {
+ struct {
+ uint32_t sdio_in1: 8;
+ uint32_t reserved8: 24;
+ };
+ uint32_t val;
+ } gpio_in1;
+ union {
+ struct {
+ uint32_t token0: 12;
+ uint32_t rx_pf_valid: 1;
+ uint32_t reserved13: 3;
+ uint32_t reg_token1: 12;
+ uint32_t rx_pf_eof: 4;
+ };
+ uint32_t val;
+ } slc0_token_rdata;
+ uint32_t slc0_pf; /**/
+ uint32_t slc1_pf; /**/
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t gpio_sdio: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_int_raw;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t wifi_rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t bt_rx_new_packet: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_int_raw;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t gpio_sdio: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_int_st;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t wifi_rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t bt_rx_new_packet: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_int_st;
+ union {
+ struct {
+ uint32_t reg_slc0_len: 20;
+ uint32_t reg_slc0_len_check:12;
+ };
+ uint32_t val;
+ } pkt_len;
+ union {
+ struct {
+ uint32_t state0: 8;
+ uint32_t state1: 8;
+ uint32_t state2: 8;
+ uint32_t state3: 8;
+ };
+ uint32_t val;
+ } state_w0;
+ union {
+ struct {
+ uint32_t state4: 8;
+ uint32_t state5: 8;
+ uint32_t state6: 8;
+ uint32_t state7: 8;
+ };
+ uint32_t val;
+ } state_w1;
+ union {
+ struct {
+ uint32_t conf0: 8;
+ uint32_t conf1: 8;
+ uint32_t conf2: 8;
+ uint32_t conf3: 8;
+ };
+ uint32_t val;
+ } conf_w0;
+ union {
+ struct {
+ uint32_t conf4: 8;
+ uint32_t conf5: 8;
+ uint32_t conf6: 8;
+ uint32_t conf7: 8;
+ };
+ uint32_t val;
+ } conf_w1;
+ union {
+ struct {
+ uint32_t conf8: 8;
+ uint32_t conf9: 8;
+ uint32_t conf10: 8;
+ uint32_t conf11: 8;
+ };
+ uint32_t val;
+ } conf_w2;
+ union {
+ struct {
+ uint32_t conf12: 8;
+ uint32_t conf13: 8;
+ uint32_t conf14: 8;
+ uint32_t conf15: 8;
+ };
+ uint32_t val;
+ } conf_w3;
+ union {
+ struct {
+ uint32_t conf16: 8; /*SLC timeout value*/
+ uint32_t conf17: 8; /*SLC timeout enable*/
+ uint32_t conf18: 8;
+ uint32_t conf19: 8; /*Interrupt to target CPU*/
+ };
+ uint32_t val;
+ } conf_w4;
+ union {
+ struct {
+ uint32_t conf20: 8;
+ uint32_t conf21: 8;
+ uint32_t conf22: 8;
+ uint32_t conf23: 8;
+ };
+ uint32_t val;
+ } conf_w5;
+ uint32_t win_cmd; /**/
+ union {
+ struct {
+ uint32_t conf24: 8;
+ uint32_t conf25: 8;
+ uint32_t conf26: 8;
+ uint32_t conf27: 8;
+ };
+ uint32_t val;
+ } conf_w6;
+ union {
+ struct {
+ uint32_t conf28: 8;
+ uint32_t conf29: 8;
+ uint32_t conf30: 8;
+ uint32_t conf31: 8;
+ };
+ uint32_t val;
+ } conf_w7;
+ union {
+ struct {
+ uint32_t reg_slc0_len0:20;
+ uint32_t reserved20: 12;
+ };
+ uint32_t val;
+ } pkt_len0;
+ union {
+ struct {
+ uint32_t reg_slc0_len1:20;
+ uint32_t reserved20: 12;
+ };
+ uint32_t val;
+ } pkt_len1;
+ union {
+ struct {
+ uint32_t reg_slc0_len2:20;
+ uint32_t reserved20: 12;
+ };
+ uint32_t val;
+ } pkt_len2;
+ union {
+ struct {
+ uint32_t conf32: 8;
+ uint32_t conf33: 8;
+ uint32_t conf34: 8;
+ uint32_t conf35: 8;
+ };
+ uint32_t val;
+ } conf_w8;
+ union {
+ struct {
+ uint32_t conf36: 8;
+ uint32_t conf37: 8;
+ uint32_t conf38: 8;
+ uint32_t conf39: 8;
+ };
+ uint32_t val;
+ } conf_w9;
+ union {
+ struct {
+ uint32_t conf40: 8;
+ uint32_t conf41: 8;
+ uint32_t conf42: 8;
+ uint32_t conf43: 8;
+ };
+ uint32_t val;
+ } conf_w10;
+ union {
+ struct {
+ uint32_t conf44: 8;
+ uint32_t conf45: 8;
+ uint32_t conf46: 8;
+ uint32_t conf47: 8;
+ };
+ uint32_t val;
+ } conf_w11;
+ union {
+ struct {
+ uint32_t conf48: 8;
+ uint32_t conf49: 8;
+ uint32_t conf50: 8;
+ uint32_t conf51: 8;
+ };
+ uint32_t val;
+ } conf_w12;
+ union {
+ struct {
+ uint32_t conf52: 8;
+ uint32_t conf53: 8;
+ uint32_t conf54: 8;
+ uint32_t conf55: 8;
+ };
+ uint32_t val;
+ } conf_w13;
+ union {
+ struct {
+ uint32_t conf56: 8;
+ uint32_t conf57: 8;
+ uint32_t conf58: 8;
+ uint32_t conf59: 8;
+ };
+ uint32_t val;
+ } conf_w14;
+ union {
+ struct {
+ uint32_t conf60: 8;
+ uint32_t conf61: 8;
+ uint32_t conf62: 8;
+ uint32_t conf63: 8;
+ };
+ uint32_t val;
+ } conf_w15;
+ uint32_t check_sum0; /**/
+ uint32_t check_sum1; /**/
+ union {
+ struct {
+ uint32_t token0: 12;
+ uint32_t rx_pf_valid: 1;
+ uint32_t reserved13: 3;
+ uint32_t reg_token1: 12;
+ uint32_t rx_pf_eof: 4;
+ };
+ uint32_t val;
+ } slc1_token_rdata;
+ union {
+ struct {
+ uint32_t token0_wd: 12;
+ uint32_t reserved12: 4;
+ uint32_t token1_wd: 12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } slc0_token_wdata;
+ union {
+ struct {
+ uint32_t token0_wd: 12;
+ uint32_t reserved12: 4;
+ uint32_t token1_wd: 12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } slc1_token_wdata;
+ union {
+ struct {
+ uint32_t slc0_token0_dec: 1;
+ uint32_t slc0_token1_dec: 1;
+ uint32_t slc0_token0_wr: 1;
+ uint32_t slc0_token1_wr: 1;
+ uint32_t slc1_token0_dec: 1;
+ uint32_t slc1_token1_dec: 1;
+ uint32_t slc1_token0_wr: 1;
+ uint32_t slc1_token1_wr: 1;
+ uint32_t slc0_len_wr: 1;
+ uint32_t reserved9: 23;
+ };
+ uint32_t val;
+ } token_con;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t gpio_sdio: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_int_clr;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t wifi_rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t bt_rx_new_packet: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_int_clr;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t gpio_sdio: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_func1_int_ena;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t wifi_rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t bt_rx_new_packet: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_func1_int_ena;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t gpio_sdio: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_func2_int_ena;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t wifi_rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t bt_rx_new_packet: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_func2_int_ena;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t gpio_sdio: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_int_ena;
+ union {
+ struct {
+ uint32_t tohost_bit0: 1;
+ uint32_t tohost_bit1: 1;
+ uint32_t tohost_bit2: 1;
+ uint32_t tohost_bit3: 1;
+ uint32_t tohost_bit4: 1;
+ uint32_t tohost_bit5: 1;
+ uint32_t tohost_bit6: 1;
+ uint32_t tohost_bit7: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t token0_0to1: 1;
+ uint32_t token1_0to1: 1;
+ uint32_t rx_sof: 1;
+ uint32_t rx_eof: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t rx_pf_valid: 1;
+ uint32_t ext_bit0: 1;
+ uint32_t ext_bit1: 1;
+ uint32_t ext_bit2: 1;
+ uint32_t ext_bit3: 1;
+ uint32_t wifi_rx_new_packet: 1;
+ uint32_t rd_retry: 1;
+ uint32_t bt_rx_new_packet: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_int_ena;
+ union {
+ struct {
+ uint32_t infor: 20;
+ uint32_t reserved20: 12;
+ };
+ uint32_t val;
+ } slc0_rx_infor;
+ union {
+ struct {
+ uint32_t infor: 20;
+ uint32_t reserved20: 12;
+ };
+ uint32_t val;
+ } slc1_rx_infor;
+ uint32_t slc0_len_wd; /**/
+ uint32_t apbwin_wdata; /**/
+ union {
+ struct {
+ uint32_t addr: 28;
+ uint32_t wr: 1;
+ uint32_t start: 1;
+ uint32_t reserved30: 2;
+ };
+ uint32_t val;
+ } apbwin_conf;
+ uint32_t apbwin_rdata; /**/
+ union {
+ struct {
+ uint32_t bit7_clraddr: 9;
+ uint32_t bit6_clraddr: 9;
+ uint32_t reserved18: 14;
+ };
+ uint32_t val;
+ } slc0_rdclr;
+ union {
+ struct {
+ uint32_t bit7_clraddr: 9;
+ uint32_t bit6_clraddr: 9;
+ uint32_t reserved18: 14;
+ };
+ uint32_t val;
+ } slc1_rdclr;
+ union {
+ struct {
+ uint32_t tohost_bit01: 1;
+ uint32_t tohost_bit11: 1;
+ uint32_t tohost_bit21: 1;
+ uint32_t tohost_bit31: 1;
+ uint32_t tohost_bit41: 1;
+ uint32_t tohost_bit51: 1;
+ uint32_t tohost_bit61: 1;
+ uint32_t tohost_bit71: 1;
+ uint32_t token0_1to01: 1;
+ uint32_t token1_1to01: 1;
+ uint32_t token0_0to11: 1;
+ uint32_t token1_0to11: 1;
+ uint32_t rx_sof1: 1;
+ uint32_t rx_eof1: 1;
+ uint32_t rx_start1: 1;
+ uint32_t tx_start1: 1;
+ uint32_t rx_udf1: 1;
+ uint32_t tx_ovf1: 1;
+ uint32_t rx_pf_valid1: 1;
+ uint32_t ext_bit01: 1;
+ uint32_t ext_bit11: 1;
+ uint32_t ext_bit21: 1;
+ uint32_t ext_bit31: 1;
+ uint32_t rx_new_packet1: 1;
+ uint32_t rd_retry1: 1;
+ uint32_t gpio_sdio1: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc0_int_ena1;
+ union {
+ struct {
+ uint32_t tohost_bit01: 1;
+ uint32_t tohost_bit11: 1;
+ uint32_t tohost_bit21: 1;
+ uint32_t tohost_bit31: 1;
+ uint32_t tohost_bit41: 1;
+ uint32_t tohost_bit51: 1;
+ uint32_t tohost_bit61: 1;
+ uint32_t tohost_bit71: 1;
+ uint32_t token0_1to01: 1;
+ uint32_t token1_1to01: 1;
+ uint32_t token0_0to11: 1;
+ uint32_t token1_0to11: 1;
+ uint32_t rx_sof1: 1;
+ uint32_t rx_eof1: 1;
+ uint32_t rx_start1: 1;
+ uint32_t tx_start1: 1;
+ uint32_t rx_udf1: 1;
+ uint32_t tx_ovf1: 1;
+ uint32_t rx_pf_valid1: 1;
+ uint32_t ext_bit01: 1;
+ uint32_t ext_bit11: 1;
+ uint32_t ext_bit21: 1;
+ uint32_t ext_bit31: 1;
+ uint32_t wifi_rx_new_packet1: 1;
+ uint32_t rd_retry1: 1;
+ uint32_t bt_rx_new_packet1: 1;
+ uint32_t reserved26: 6;
+ };
+ uint32_t val;
+ } slc1_int_ena1;
+ uint32_t reserved_11c;
+ uint32_t reserved_120;
+ uint32_t reserved_124;
+ uint32_t reserved_128;
+ uint32_t reserved_12c;
+ uint32_t reserved_130;
+ uint32_t reserved_134;
+ uint32_t reserved_138;
+ uint32_t reserved_13c;
+ uint32_t reserved_140;
+ uint32_t reserved_144;
+ uint32_t reserved_148;
+ uint32_t reserved_14c;
+ uint32_t reserved_150;
+ uint32_t reserved_154;
+ uint32_t reserved_158;
+ uint32_t reserved_15c;
+ uint32_t reserved_160;
+ uint32_t reserved_164;
+ uint32_t reserved_168;
+ uint32_t reserved_16c;
+ uint32_t reserved_170;
+ uint32_t reserved_174;
+ uint32_t date; /**/
+ uint32_t id; /**/
+ uint32_t reserved_180;
+ uint32_t reserved_184;
+ uint32_t reserved_188;
+ uint32_t reserved_18c;
+ uint32_t reserved_190;
+ uint32_t reserved_194;
+ uint32_t reserved_198;
+ uint32_t reserved_19c;
+ uint32_t reserved_1a0;
+ uint32_t reserved_1a4;
+ uint32_t reserved_1a8;
+ uint32_t reserved_1ac;
+ uint32_t reserved_1b0;
+ uint32_t reserved_1b4;
+ uint32_t reserved_1b8;
+ uint32_t reserved_1bc;
+ uint32_t reserved_1c0;
+ uint32_t reserved_1c4;
+ uint32_t reserved_1c8;
+ uint32_t reserved_1cc;
+ uint32_t reserved_1d0;
+ uint32_t reserved_1d4;
+ uint32_t reserved_1d8;
+ uint32_t reserved_1dc;
+ uint32_t reserved_1e0;
+ uint32_t reserved_1e4;
+ uint32_t reserved_1e8;
+ uint32_t reserved_1ec;
+ union {
+ struct {
+ uint32_t frc_sdio11: 5;
+ uint32_t frc_sdio20: 5;
+ uint32_t frc_neg_samp: 5;
+ uint32_t frc_pos_samp: 5;
+ uint32_t frc_quick_in: 5;
+ uint32_t sdio20_int_delay: 1;
+ uint32_t sdio_pad_pullup: 1;
+ uint32_t hspeed_con_en: 1;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } conf;
+ union {
+ struct {
+ uint32_t sdio20_mode: 5;
+ uint32_t sdio_neg_samp: 5;
+ uint32_t sdio_quick_in: 5;
+ uint32_t reserved15: 17;
+ };
+ uint32_t val;
+ } inf_st;
+} host_dev_t;
+extern host_dev_t HOST;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_HOST_STRUCT_H_ */
--- /dev/null
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SLC_REG_H_
+#define _SOC_SLC_REG_H_
+
+
+#include "soc.h"
+#define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0)
+/* SLC_SLC1_TOKEN_SEL : R/W ;bitpos:[31] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC1_TOKEN_SEL (BIT(31))
+#define SLC_SLC1_TOKEN_SEL_M (BIT(31))
+#define SLC_SLC1_TOKEN_SEL_V 0x1
+#define SLC_SLC1_TOKEN_SEL_S 31
+/* SLC_SLC1_TOKEN_AUTO_CLR : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC1_TOKEN_AUTO_CLR (BIT(30))
+#define SLC_SLC1_TOKEN_AUTO_CLR_M (BIT(30))
+#define SLC_SLC1_TOKEN_AUTO_CLR_V 0x1
+#define SLC_SLC1_TOKEN_AUTO_CLR_S 30
+/* SLC_SLC1_TXDATA_BURST_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TXDATA_BURST_EN (BIT(29))
+#define SLC_SLC1_TXDATA_BURST_EN_M (BIT(29))
+#define SLC_SLC1_TXDATA_BURST_EN_V 0x1
+#define SLC_SLC1_TXDATA_BURST_EN_S 29
+/* SLC_SLC1_TXDSCR_BURST_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TXDSCR_BURST_EN (BIT(28))
+#define SLC_SLC1_TXDSCR_BURST_EN_M (BIT(28))
+#define SLC_SLC1_TXDSCR_BURST_EN_V 0x1
+#define SLC_SLC1_TXDSCR_BURST_EN_S 28
+/* SLC_SLC1_TXLINK_AUTO_RET : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_AUTO_RET (BIT(27))
+#define SLC_SLC1_TXLINK_AUTO_RET_M (BIT(27))
+#define SLC_SLC1_TXLINK_AUTO_RET_V 0x1
+#define SLC_SLC1_TXLINK_AUTO_RET_S 27
+/* SLC_SLC1_RXLINK_AUTO_RET : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_AUTO_RET (BIT(26))
+#define SLC_SLC1_RXLINK_AUTO_RET_M (BIT(26))
+#define SLC_SLC1_RXLINK_AUTO_RET_V 0x1
+#define SLC_SLC1_RXLINK_AUTO_RET_S 26
+/* SLC_SLC1_RXDATA_BURST_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RXDATA_BURST_EN (BIT(25))
+#define SLC_SLC1_RXDATA_BURST_EN_M (BIT(25))
+#define SLC_SLC1_RXDATA_BURST_EN_V 0x1
+#define SLC_SLC1_RXDATA_BURST_EN_S 25
+/* SLC_SLC1_RXDSCR_BURST_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RXDSCR_BURST_EN (BIT(24))
+#define SLC_SLC1_RXDSCR_BURST_EN_M (BIT(24))
+#define SLC_SLC1_RXDSCR_BURST_EN_V 0x1
+#define SLC_SLC1_RXDSCR_BURST_EN_S 24
+/* SLC_SLC1_RX_NO_RESTART_CLR : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_NO_RESTART_CLR (BIT(23))
+#define SLC_SLC1_RX_NO_RESTART_CLR_M (BIT(23))
+#define SLC_SLC1_RX_NO_RESTART_CLR_V 0x1
+#define SLC_SLC1_RX_NO_RESTART_CLR_S 23
+/* SLC_SLC1_RX_AUTO_WRBACK : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_AUTO_WRBACK (BIT(22))
+#define SLC_SLC1_RX_AUTO_WRBACK_M (BIT(22))
+#define SLC_SLC1_RX_AUTO_WRBACK_V 0x1
+#define SLC_SLC1_RX_AUTO_WRBACK_S 22
+/* SLC_SLC1_RX_LOOP_TEST : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RX_LOOP_TEST (BIT(21))
+#define SLC_SLC1_RX_LOOP_TEST_M (BIT(21))
+#define SLC_SLC1_RX_LOOP_TEST_V 0x1
+#define SLC_SLC1_RX_LOOP_TEST_S 21
+/* SLC_SLC1_TX_LOOP_TEST : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TX_LOOP_TEST (BIT(20))
+#define SLC_SLC1_TX_LOOP_TEST_M (BIT(20))
+#define SLC_SLC1_TX_LOOP_TEST_V 0x1
+#define SLC_SLC1_TX_LOOP_TEST_S 20
+/* SLC_SLC1_WR_RETRY_MASK_EN : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_MASK_EN (BIT(19))
+#define SLC_SLC1_WR_RETRY_MASK_EN_M (BIT(19))
+#define SLC_SLC1_WR_RETRY_MASK_EN_V 0x1
+#define SLC_SLC1_WR_RETRY_MASK_EN_S 19
+/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_MASK_EN (BIT(18))
+#define SLC_SLC0_WR_RETRY_MASK_EN_M (BIT(18))
+#define SLC_SLC0_WR_RETRY_MASK_EN_V 0x1
+#define SLC_SLC0_WR_RETRY_MASK_EN_S 18
+/* SLC_SLC1_RX_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_RST (BIT(17))
+#define SLC_SLC1_RX_RST_M (BIT(17))
+#define SLC_SLC1_RX_RST_V 0x1
+#define SLC_SLC1_RX_RST_S 17
+/* SLC_SLC1_TX_RST : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC1_TX_RST (BIT(16))
+#define SLC_SLC1_TX_RST_M (BIT(16))
+#define SLC_SLC1_TX_RST_V 0x1
+#define SLC_SLC1_TX_RST_S 16
+/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TOKEN_SEL (BIT(15))
+#define SLC_SLC0_TOKEN_SEL_M (BIT(15))
+#define SLC_SLC0_TOKEN_SEL_V 0x1
+#define SLC_SLC0_TOKEN_SEL_S 15
+/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TOKEN_AUTO_CLR (BIT(14))
+#define SLC_SLC0_TOKEN_AUTO_CLR_M (BIT(14))
+#define SLC_SLC0_TOKEN_AUTO_CLR_V 0x1
+#define SLC_SLC0_TOKEN_AUTO_CLR_S 14
+/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TXDATA_BURST_EN (BIT(13))
+#define SLC_SLC0_TXDATA_BURST_EN_M (BIT(13))
+#define SLC_SLC0_TXDATA_BURST_EN_V 0x1
+#define SLC_SLC0_TXDATA_BURST_EN_S 13
+/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TXDSCR_BURST_EN (BIT(12))
+#define SLC_SLC0_TXDSCR_BURST_EN_M (BIT(12))
+#define SLC_SLC0_TXDSCR_BURST_EN_V 0x1
+#define SLC_SLC0_TXDSCR_BURST_EN_S 12
+/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_AUTO_RET (BIT(11))
+#define SLC_SLC0_TXLINK_AUTO_RET_M (BIT(11))
+#define SLC_SLC0_TXLINK_AUTO_RET_V 0x1
+#define SLC_SLC0_TXLINK_AUTO_RET_S 11
+/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_AUTO_RET (BIT(10))
+#define SLC_SLC0_RXLINK_AUTO_RET_M (BIT(10))
+#define SLC_SLC0_RXLINK_AUTO_RET_V 0x1
+#define SLC_SLC0_RXLINK_AUTO_RET_S 10
+/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RXDATA_BURST_EN (BIT(9))
+#define SLC_SLC0_RXDATA_BURST_EN_M (BIT(9))
+#define SLC_SLC0_RXDATA_BURST_EN_V 0x1
+#define SLC_SLC0_RXDATA_BURST_EN_S 9
+/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RXDSCR_BURST_EN (BIT(8))
+#define SLC_SLC0_RXDSCR_BURST_EN_M (BIT(8))
+#define SLC_SLC0_RXDSCR_BURST_EN_V 0x1
+#define SLC_SLC0_RXDSCR_BURST_EN_S 8
+/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_NO_RESTART_CLR (BIT(7))
+#define SLC_SLC0_RX_NO_RESTART_CLR_M (BIT(7))
+#define SLC_SLC0_RX_NO_RESTART_CLR_V 0x1
+#define SLC_SLC0_RX_NO_RESTART_CLR_S 7
+/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_AUTO_WRBACK (BIT(6))
+#define SLC_SLC0_RX_AUTO_WRBACK_M (BIT(6))
+#define SLC_SLC0_RX_AUTO_WRBACK_V 0x1
+#define SLC_SLC0_RX_AUTO_WRBACK_S 6
+/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_LOOP_TEST (BIT(5))
+#define SLC_SLC0_RX_LOOP_TEST_M (BIT(5))
+#define SLC_SLC0_RX_LOOP_TEST_V 0x1
+#define SLC_SLC0_RX_LOOP_TEST_S 5
+/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TX_LOOP_TEST (BIT(4))
+#define SLC_SLC0_TX_LOOP_TEST_M (BIT(4))
+#define SLC_SLC0_TX_LOOP_TEST_V 0x1
+#define SLC_SLC0_TX_LOOP_TEST_S 4
+/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_AHBM_RST (BIT(3))
+#define SLC_AHBM_RST_M (BIT(3))
+#define SLC_AHBM_RST_V 0x1
+#define SLC_AHBM_RST_S 3
+/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_AHBM_FIFO_RST (BIT(2))
+#define SLC_AHBM_FIFO_RST_M (BIT(2))
+#define SLC_AHBM_FIFO_RST_V 0x1
+#define SLC_AHBM_FIFO_RST_S 2
+/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_RST (BIT(1))
+#define SLC_SLC0_RX_RST_M (BIT(1))
+#define SLC_SLC0_RX_RST_V 0x1
+#define SLC_SLC0_RX_RST_S 1
+/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_RST (BIT(0))
+#define SLC_SLC0_TX_RST_M (BIT(0))
+#define SLC_SLC0_TX_RST_V 0x1
+#define SLC_SLC0_TX_RST_S 0
+
+#define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4)
+/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V 0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S 26
+/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_RAW (BIT(25))
+#define SLC_CMD_DTC_INT_RAW_M (BIT(25))
+#define SLC_CMD_DTC_INT_RAW_V 0x1
+#define SLC_CMD_DTC_INT_RAW_S 25
+/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V 0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S 24
+/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V 0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S 23
+/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V 0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S 22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21
+/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V 0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S 20
+/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V 0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S 19
+/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_RAW (BIT(18))
+#define SLC_SLC0_TOHOST_INT_RAW_M (BIT(18))
+#define SLC_SLC0_TOHOST_INT_RAW_V 0x1
+#define SLC_SLC0_TOHOST_INT_RAW_S 18
+/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_RAW (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_RAW_M (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_RAW_V 0x1
+#define SLC_SLC0_RX_EOF_INT_RAW_S 17
+/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_RAW (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_RAW_M (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_RAW_V 0x1
+#define SLC_SLC0_RX_DONE_INT_RAW_S 16
+/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V 0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S 15
+/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_RAW (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_RAW_M (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_RAW_V 0x1
+#define SLC_SLC0_TX_DONE_INT_RAW_S 14
+/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S 13
+/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S 12
+/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_RAW (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_RAW_M (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_RAW_V 0x1
+#define SLC_SLC0_TX_OVF_INT_RAW_S 11
+/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_RAW (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_RAW_M (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_RAW_V 0x1
+#define SLC_SLC0_RX_UDF_INT_RAW_S 10
+/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_RAW (BIT(9))
+#define SLC_SLC0_TX_START_INT_RAW_M (BIT(9))
+#define SLC_SLC0_TX_START_INT_RAW_V 0x1
+#define SLC_SLC0_TX_START_INT_RAW_S 9
+/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_RAW (BIT(8))
+#define SLC_SLC0_RX_START_INT_RAW_M (BIT(8))
+#define SLC_SLC0_RX_START_INT_RAW_V 0x1
+#define SLC_SLC0_RX_START_INT_RAW_S 8
+/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_RAW (BIT(7))
+#define SLC_FRHOST_BIT7_INT_RAW_M (BIT(7))
+#define SLC_FRHOST_BIT7_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT7_INT_RAW_S 7
+/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_RAW (BIT(6))
+#define SLC_FRHOST_BIT6_INT_RAW_M (BIT(6))
+#define SLC_FRHOST_BIT6_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT6_INT_RAW_S 6
+/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_RAW (BIT(5))
+#define SLC_FRHOST_BIT5_INT_RAW_M (BIT(5))
+#define SLC_FRHOST_BIT5_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT5_INT_RAW_S 5
+/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_RAW (BIT(4))
+#define SLC_FRHOST_BIT4_INT_RAW_M (BIT(4))
+#define SLC_FRHOST_BIT4_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT4_INT_RAW_S 4
+/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_RAW (BIT(3))
+#define SLC_FRHOST_BIT3_INT_RAW_M (BIT(3))
+#define SLC_FRHOST_BIT3_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT3_INT_RAW_S 3
+/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_RAW (BIT(2))
+#define SLC_FRHOST_BIT2_INT_RAW_M (BIT(2))
+#define SLC_FRHOST_BIT2_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT2_INT_RAW_S 2
+/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_RAW (BIT(1))
+#define SLC_FRHOST_BIT1_INT_RAW_M (BIT(1))
+#define SLC_FRHOST_BIT1_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT1_INT_RAW_S 1
+/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_RAW (BIT(0))
+#define SLC_FRHOST_BIT0_INT_RAW_M (BIT(0))
+#define SLC_FRHOST_BIT0_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT0_INT_RAW_S 0
+
+#define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8)
+/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V 0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S 26
+/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ST (BIT(25))
+#define SLC_CMD_DTC_INT_ST_M (BIT(25))
+#define SLC_CMD_DTC_INT_ST_V 0x1
+#define SLC_CMD_DTC_INT_ST_S 25
+/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ST (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_M (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_V 0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_S 24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V 0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S 23
+/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ST (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_M (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_V 0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_S 22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S 21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V 0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S 20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V 0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S 19
+/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ST (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST_M (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST_V 0x1
+#define SLC_SLC0_TOHOST_INT_ST_S 18
+/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ST (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST_M (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST_V 0x1
+#define SLC_SLC0_RX_EOF_INT_ST_S 17
+/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ST (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST_M (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST_V 0x1
+#define SLC_SLC0_RX_DONE_INT_ST_S 16
+/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ST (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_M (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_V 0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_S 15
+/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ST (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST_M (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST_V 0x1
+#define SLC_SLC0_TX_DONE_INT_ST_S 14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V 0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S 13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V 0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S 12
+/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ST (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST_M (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST_V 0x1
+#define SLC_SLC0_TX_OVF_INT_ST_S 11
+/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ST (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST_M (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST_V 0x1
+#define SLC_SLC0_RX_UDF_INT_ST_S 10
+/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ST (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST_M (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST_V 0x1
+#define SLC_SLC0_TX_START_INT_ST_S 9
+/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ST (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST_M (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST_V 0x1
+#define SLC_SLC0_RX_START_INT_ST_S 8
+/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ST (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST_M (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST_V 0x1
+#define SLC_FRHOST_BIT7_INT_ST_S 7
+/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ST (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST_M (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST_V 0x1
+#define SLC_FRHOST_BIT6_INT_ST_S 6
+/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ST (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST_M (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST_V 0x1
+#define SLC_FRHOST_BIT5_INT_ST_S 5
+/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ST (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST_M (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST_V 0x1
+#define SLC_FRHOST_BIT4_INT_ST_S 4
+/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ST (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST_M (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST_V 0x1
+#define SLC_FRHOST_BIT3_INT_ST_S 3
+/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ST (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST_M (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST_V 0x1
+#define SLC_FRHOST_BIT2_INT_ST_S 2
+/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ST (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST_M (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST_V 0x1
+#define SLC_FRHOST_BIT1_INT_ST_S 1
+/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ST (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST_M (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST_V 0x1
+#define SLC_FRHOST_BIT0_INT_ST_S 0
+
+#define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC)
+/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V 0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S 26
+/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ENA (BIT(25))
+#define SLC_CMD_DTC_INT_ENA_M (BIT(25))
+#define SLC_CMD_DTC_INT_ENA_V 0x1
+#define SLC_CMD_DTC_INT_ENA_S 25
+/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V 0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S 24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V 0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S 23
+/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V 0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S 22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V 0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S 20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V 0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S 19
+/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ENA (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA_M (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA_V 0x1
+#define SLC_SLC0_TOHOST_INT_ENA_S 18
+/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ENA (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA_M (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA_V 0x1
+#define SLC_SLC0_RX_EOF_INT_ENA_S 17
+/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ENA (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA_M (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA_V 0x1
+#define SLC_SLC0_RX_DONE_INT_ENA_S 16
+/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V 0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S 15
+/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ENA (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA_M (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA_V 0x1
+#define SLC_SLC0_TX_DONE_INT_ENA_S 14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S 13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S 12
+/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ENA (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA_M (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA_V 0x1
+#define SLC_SLC0_TX_OVF_INT_ENA_S 11
+/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ENA (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA_M (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA_V 0x1
+#define SLC_SLC0_RX_UDF_INT_ENA_S 10
+/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ENA (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA_M (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA_V 0x1
+#define SLC_SLC0_TX_START_INT_ENA_S 9
+/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ENA (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA_M (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA_V 0x1
+#define SLC_SLC0_RX_START_INT_ENA_S 8
+/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ENA (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA_M (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT7_INT_ENA_S 7
+/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ENA (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA_M (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT6_INT_ENA_S 6
+/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ENA (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA_M (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT5_INT_ENA_S 5
+/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ENA (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA_M (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT4_INT_ENA_S 4
+/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ENA (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA_M (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT3_INT_ENA_S 3
+/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ENA (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA_M (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT2_INT_ENA_S 2
+/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ENA (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA_M (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT1_INT_ENA_S 1
+/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ENA (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA_M (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT0_INT_ENA_S 0
+
+#define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10)
+/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V 0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S 26
+/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_CLR (BIT(25))
+#define SLC_CMD_DTC_INT_CLR_M (BIT(25))
+#define SLC_CMD_DTC_INT_CLR_V 0x1
+#define SLC_CMD_DTC_INT_CLR_S 25
+/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V 0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S 24
+/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V 0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S 23
+/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V 0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S 22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21
+/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V 0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S 20
+/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V 0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S 19
+/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_CLR (BIT(18))
+#define SLC_SLC0_TOHOST_INT_CLR_M (BIT(18))
+#define SLC_SLC0_TOHOST_INT_CLR_V 0x1
+#define SLC_SLC0_TOHOST_INT_CLR_S 18
+/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_CLR (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_CLR_M (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_CLR_V 0x1
+#define SLC_SLC0_RX_EOF_INT_CLR_S 17
+/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_CLR (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_CLR_M (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_CLR_V 0x1
+#define SLC_SLC0_RX_DONE_INT_CLR_S 16
+/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V 0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S 15
+/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_CLR (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_CLR_M (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_CLR_V 0x1
+#define SLC_SLC0_TX_DONE_INT_CLR_S 14
+/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S 13
+/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S 12
+/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_CLR (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_CLR_M (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_CLR_V 0x1
+#define SLC_SLC0_TX_OVF_INT_CLR_S 11
+/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_CLR (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_CLR_M (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_CLR_V 0x1
+#define SLC_SLC0_RX_UDF_INT_CLR_S 10
+/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_CLR (BIT(9))
+#define SLC_SLC0_TX_START_INT_CLR_M (BIT(9))
+#define SLC_SLC0_TX_START_INT_CLR_V 0x1
+#define SLC_SLC0_TX_START_INT_CLR_S 9
+/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_CLR (BIT(8))
+#define SLC_SLC0_RX_START_INT_CLR_M (BIT(8))
+#define SLC_SLC0_RX_START_INT_CLR_V 0x1
+#define SLC_SLC0_RX_START_INT_CLR_S 8
+/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_CLR (BIT(7))
+#define SLC_FRHOST_BIT7_INT_CLR_M (BIT(7))
+#define SLC_FRHOST_BIT7_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT7_INT_CLR_S 7
+/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_CLR (BIT(6))
+#define SLC_FRHOST_BIT6_INT_CLR_M (BIT(6))
+#define SLC_FRHOST_BIT6_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT6_INT_CLR_S 6
+/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_CLR (BIT(5))
+#define SLC_FRHOST_BIT5_INT_CLR_M (BIT(5))
+#define SLC_FRHOST_BIT5_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT5_INT_CLR_S 5
+/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_CLR (BIT(4))
+#define SLC_FRHOST_BIT4_INT_CLR_M (BIT(4))
+#define SLC_FRHOST_BIT4_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT4_INT_CLR_S 4
+/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_CLR (BIT(3))
+#define SLC_FRHOST_BIT3_INT_CLR_M (BIT(3))
+#define SLC_FRHOST_BIT3_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT3_INT_CLR_S 3
+/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_CLR (BIT(2))
+#define SLC_FRHOST_BIT2_INT_CLR_M (BIT(2))
+#define SLC_FRHOST_BIT2_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT2_INT_CLR_S 2
+/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_CLR (BIT(1))
+#define SLC_FRHOST_BIT1_INT_CLR_M (BIT(1))
+#define SLC_FRHOST_BIT1_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT1_INT_CLR_S 1
+/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_CLR (BIT(0))
+#define SLC_FRHOST_BIT0_INT_CLR_M (BIT(0))
+#define SLC_FRHOST_BIT0_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT0_INT_CLR_S 0
+
+#define SLC_1INT_RAW_REG (DR_REG_SLC_BASE + 0x14)
+/* SLC_SLC1_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_INT_RAW (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_RAW_M (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_RAW_V 0x1
+#define SLC_SLC1_TX_ERR_EOF_INT_RAW_S 24
+/* SLC_SLC1_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_M (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_V 0x1
+#define SLC_SLC1_WR_RETRY_DONE_INT_RAW_S 23
+/* SLC_SLC1_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_HOST_RD_ACK_INT_RAW (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_RAW_M (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_RAW_V 0x1
+#define SLC_SLC1_HOST_RD_ACK_INT_RAW_S 22
+/* SLC_SLC1_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_M (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x1
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21
+/* SLC_SLC1_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_M (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_V 0x1
+#define SLC_SLC1_RX_DSCR_ERR_INT_RAW_S 20
+/* SLC_SLC1_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_M (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_V 0x1
+#define SLC_SLC1_TX_DSCR_ERR_INT_RAW_S 19
+/* SLC_SLC1_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INT_RAW (BIT(18))
+#define SLC_SLC1_TOHOST_INT_RAW_M (BIT(18))
+#define SLC_SLC1_TOHOST_INT_RAW_V 0x1
+#define SLC_SLC1_TOHOST_INT_RAW_S 18
+/* SLC_SLC1_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_INT_RAW (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_RAW_M (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_RAW_V 0x1
+#define SLC_SLC1_RX_EOF_INT_RAW_S 17
+/* SLC_SLC1_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DONE_INT_RAW (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_RAW_M (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_RAW_V 0x1
+#define SLC_SLC1_RX_DONE_INT_RAW_S 16
+/* SLC_SLC1_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_INT_RAW (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_RAW_M (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_RAW_V 0x1
+#define SLC_SLC1_TX_SUC_EOF_INT_RAW_S 15
+/* SLC_SLC1_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DONE_INT_RAW (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_RAW_M (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_RAW_V 0x1
+#define SLC_SLC1_TX_DONE_INT_RAW_S 14
+/* SLC_SLC1_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_M (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_V 0x1
+#define SLC_SLC1_TOKEN1_1TO0_INT_RAW_S 13
+/* SLC_SLC1_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_M (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_V 0x1
+#define SLC_SLC1_TOKEN0_1TO0_INT_RAW_S 12
+/* SLC_SLC1_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_OVF_INT_RAW (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_RAW_M (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_RAW_V 0x1
+#define SLC_SLC1_TX_OVF_INT_RAW_S 11
+/* SLC_SLC1_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_UDF_INT_RAW (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_RAW_M (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_RAW_V 0x1
+#define SLC_SLC1_RX_UDF_INT_RAW_S 10
+/* SLC_SLC1_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_START_INT_RAW (BIT(9))
+#define SLC_SLC1_TX_START_INT_RAW_M (BIT(9))
+#define SLC_SLC1_TX_START_INT_RAW_V 0x1
+#define SLC_SLC1_TX_START_INT_RAW_S 9
+/* SLC_SLC1_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_START_INT_RAW (BIT(8))
+#define SLC_SLC1_RX_START_INT_RAW_M (BIT(8))
+#define SLC_SLC1_RX_START_INT_RAW_V 0x1
+#define SLC_SLC1_RX_START_INT_RAW_S 8
+/* SLC_FRHOST_BIT15_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT15_INT_RAW (BIT(7))
+#define SLC_FRHOST_BIT15_INT_RAW_M (BIT(7))
+#define SLC_FRHOST_BIT15_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT15_INT_RAW_S 7
+/* SLC_FRHOST_BIT14_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT14_INT_RAW (BIT(6))
+#define SLC_FRHOST_BIT14_INT_RAW_M (BIT(6))
+#define SLC_FRHOST_BIT14_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT14_INT_RAW_S 6
+/* SLC_FRHOST_BIT13_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT13_INT_RAW (BIT(5))
+#define SLC_FRHOST_BIT13_INT_RAW_M (BIT(5))
+#define SLC_FRHOST_BIT13_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT13_INT_RAW_S 5
+/* SLC_FRHOST_BIT12_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT12_INT_RAW (BIT(4))
+#define SLC_FRHOST_BIT12_INT_RAW_M (BIT(4))
+#define SLC_FRHOST_BIT12_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT12_INT_RAW_S 4
+/* SLC_FRHOST_BIT11_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT11_INT_RAW (BIT(3))
+#define SLC_FRHOST_BIT11_INT_RAW_M (BIT(3))
+#define SLC_FRHOST_BIT11_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT11_INT_RAW_S 3
+/* SLC_FRHOST_BIT10_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT10_INT_RAW (BIT(2))
+#define SLC_FRHOST_BIT10_INT_RAW_M (BIT(2))
+#define SLC_FRHOST_BIT10_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT10_INT_RAW_S 2
+/* SLC_FRHOST_BIT9_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT9_INT_RAW (BIT(1))
+#define SLC_FRHOST_BIT9_INT_RAW_M (BIT(1))
+#define SLC_FRHOST_BIT9_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT9_INT_RAW_S 1
+/* SLC_FRHOST_BIT8_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT8_INT_RAW (BIT(0))
+#define SLC_FRHOST_BIT8_INT_RAW_M (BIT(0))
+#define SLC_FRHOST_BIT8_INT_RAW_V 0x1
+#define SLC_FRHOST_BIT8_INT_RAW_S 0
+
+#define SLC_1INT_ST_REG (DR_REG_SLC_BASE + 0x18)
+/* SLC_SLC1_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_INT_ST (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ST_M (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ST_V 0x1
+#define SLC_SLC1_TX_ERR_EOF_INT_ST_S 24
+/* SLC_SLC1_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST_M (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST_V 0x1
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST_S 23
+/* SLC_SLC1_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_HOST_RD_ACK_INT_ST (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ST_M (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ST_V 0x1
+#define SLC_SLC1_HOST_RD_ACK_INT_ST_S 22
+/* SLC_SLC1_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_M (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x1
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST_S 21
+/* SLC_SLC1_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST_M (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST_V 0x1
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST_S 20
+/* SLC_SLC1_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST_M (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST_V 0x1
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST_S 19
+/* SLC_SLC1_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INT_ST (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ST_M (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ST_V 0x1
+#define SLC_SLC1_TOHOST_INT_ST_S 18
+/* SLC_SLC1_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_INT_ST (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ST_M (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ST_V 0x1
+#define SLC_SLC1_RX_EOF_INT_ST_S 17
+/* SLC_SLC1_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DONE_INT_ST (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ST_M (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ST_V 0x1
+#define SLC_SLC1_RX_DONE_INT_ST_S 16
+/* SLC_SLC1_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_INT_ST (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ST_M (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ST_V 0x1
+#define SLC_SLC1_TX_SUC_EOF_INT_ST_S 15
+/* SLC_SLC1_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DONE_INT_ST (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ST_M (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ST_V 0x1
+#define SLC_SLC1_TX_DONE_INT_ST_S 14
+/* SLC_SLC1_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST_M (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST_V 0x1
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST_S 13
+/* SLC_SLC1_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST_M (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST_V 0x1
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST_S 12
+/* SLC_SLC1_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_OVF_INT_ST (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ST_M (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ST_V 0x1
+#define SLC_SLC1_TX_OVF_INT_ST_S 11
+/* SLC_SLC1_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_UDF_INT_ST (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ST_M (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ST_V 0x1
+#define SLC_SLC1_RX_UDF_INT_ST_S 10
+/* SLC_SLC1_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_START_INT_ST (BIT(9))
+#define SLC_SLC1_TX_START_INT_ST_M (BIT(9))
+#define SLC_SLC1_TX_START_INT_ST_V 0x1
+#define SLC_SLC1_TX_START_INT_ST_S 9
+/* SLC_SLC1_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_START_INT_ST (BIT(8))
+#define SLC_SLC1_RX_START_INT_ST_M (BIT(8))
+#define SLC_SLC1_RX_START_INT_ST_V 0x1
+#define SLC_SLC1_RX_START_INT_ST_S 8
+/* SLC_FRHOST_BIT15_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT15_INT_ST (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ST_M (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ST_V 0x1
+#define SLC_FRHOST_BIT15_INT_ST_S 7
+/* SLC_FRHOST_BIT14_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT14_INT_ST (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ST_M (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ST_V 0x1
+#define SLC_FRHOST_BIT14_INT_ST_S 6
+/* SLC_FRHOST_BIT13_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT13_INT_ST (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ST_M (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ST_V 0x1
+#define SLC_FRHOST_BIT13_INT_ST_S 5
+/* SLC_FRHOST_BIT12_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT12_INT_ST (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ST_M (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ST_V 0x1
+#define SLC_FRHOST_BIT12_INT_ST_S 4
+/* SLC_FRHOST_BIT11_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT11_INT_ST (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ST_M (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ST_V 0x1
+#define SLC_FRHOST_BIT11_INT_ST_S 3
+/* SLC_FRHOST_BIT10_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT10_INT_ST (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ST_M (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ST_V 0x1
+#define SLC_FRHOST_BIT10_INT_ST_S 2
+/* SLC_FRHOST_BIT9_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT9_INT_ST (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ST_M (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ST_V 0x1
+#define SLC_FRHOST_BIT9_INT_ST_S 1
+/* SLC_FRHOST_BIT8_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT8_INT_ST (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ST_M (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ST_V 0x1
+#define SLC_FRHOST_BIT8_INT_ST_S 0
+
+#define SLC_1INT_ENA_REG (DR_REG_SLC_BASE + 0x1C)
+/* SLC_SLC1_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA_M (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA_V 0x1
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA_S 24
+/* SLC_SLC1_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_M (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_V 0x1
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA_S 23
+/* SLC_SLC1_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA_M (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA_V 0x1
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA_S 22
+/* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_M (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x1
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21
+/* SLC_SLC1_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_M (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_V 0x1
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA_S 20
+/* SLC_SLC1_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_M (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_V 0x1
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA_S 19
+/* SLC_SLC1_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INT_ENA (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ENA_M (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ENA_V 0x1
+#define SLC_SLC1_TOHOST_INT_ENA_S 18
+/* SLC_SLC1_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_INT_ENA (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ENA_M (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ENA_V 0x1
+#define SLC_SLC1_RX_EOF_INT_ENA_S 17
+/* SLC_SLC1_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DONE_INT_ENA (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ENA_M (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ENA_V 0x1
+#define SLC_SLC1_RX_DONE_INT_ENA_S 16
+/* SLC_SLC1_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA_M (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA_V 0x1
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA_S 15
+/* SLC_SLC1_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DONE_INT_ENA (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ENA_M (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ENA_V 0x1
+#define SLC_SLC1_TX_DONE_INT_ENA_S 14
+/* SLC_SLC1_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_M (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_V 0x1
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA_S 13
+/* SLC_SLC1_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_M (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_V 0x1
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA_S 12
+/* SLC_SLC1_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_OVF_INT_ENA (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ENA_M (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ENA_V 0x1
+#define SLC_SLC1_TX_OVF_INT_ENA_S 11
+/* SLC_SLC1_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_UDF_INT_ENA (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ENA_M (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ENA_V 0x1
+#define SLC_SLC1_RX_UDF_INT_ENA_S 10
+/* SLC_SLC1_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_START_INT_ENA (BIT(9))
+#define SLC_SLC1_TX_START_INT_ENA_M (BIT(9))
+#define SLC_SLC1_TX_START_INT_ENA_V 0x1
+#define SLC_SLC1_TX_START_INT_ENA_S 9
+/* SLC_SLC1_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_START_INT_ENA (BIT(8))
+#define SLC_SLC1_RX_START_INT_ENA_M (BIT(8))
+#define SLC_SLC1_RX_START_INT_ENA_V 0x1
+#define SLC_SLC1_RX_START_INT_ENA_S 8
+/* SLC_FRHOST_BIT15_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT15_INT_ENA (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ENA_M (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT15_INT_ENA_S 7
+/* SLC_FRHOST_BIT14_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT14_INT_ENA (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ENA_M (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT14_INT_ENA_S 6
+/* SLC_FRHOST_BIT13_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT13_INT_ENA (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ENA_M (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT13_INT_ENA_S 5
+/* SLC_FRHOST_BIT12_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT12_INT_ENA (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ENA_M (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT12_INT_ENA_S 4
+/* SLC_FRHOST_BIT11_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT11_INT_ENA (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ENA_M (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT11_INT_ENA_S 3
+/* SLC_FRHOST_BIT10_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT10_INT_ENA (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ENA_M (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT10_INT_ENA_S 2
+/* SLC_FRHOST_BIT9_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT9_INT_ENA (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ENA_M (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT9_INT_ENA_S 1
+/* SLC_FRHOST_BIT8_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT8_INT_ENA (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ENA_M (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ENA_V 0x1
+#define SLC_FRHOST_BIT8_INT_ENA_S 0
+
+#define SLC_1INT_CLR_REG (DR_REG_SLC_BASE + 0x20)
+/* SLC_SLC1_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_INT_CLR (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_CLR_M (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_CLR_V 0x1
+#define SLC_SLC1_TX_ERR_EOF_INT_CLR_S 24
+/* SLC_SLC1_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_M (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_V 0x1
+#define SLC_SLC1_WR_RETRY_DONE_INT_CLR_S 23
+/* SLC_SLC1_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_HOST_RD_ACK_INT_CLR (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_CLR_M (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_CLR_V 0x1
+#define SLC_SLC1_HOST_RD_ACK_INT_CLR_S 22
+/* SLC_SLC1_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_M (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x1
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21
+/* SLC_SLC1_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_M (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_V 0x1
+#define SLC_SLC1_RX_DSCR_ERR_INT_CLR_S 20
+/* SLC_SLC1_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_M (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_V 0x1
+#define SLC_SLC1_TX_DSCR_ERR_INT_CLR_S 19
+/* SLC_SLC1_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INT_CLR (BIT(18))
+#define SLC_SLC1_TOHOST_INT_CLR_M (BIT(18))
+#define SLC_SLC1_TOHOST_INT_CLR_V 0x1
+#define SLC_SLC1_TOHOST_INT_CLR_S 18
+/* SLC_SLC1_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_INT_CLR (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_CLR_M (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_CLR_V 0x1
+#define SLC_SLC1_RX_EOF_INT_CLR_S 17
+/* SLC_SLC1_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DONE_INT_CLR (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_CLR_M (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_CLR_V 0x1
+#define SLC_SLC1_RX_DONE_INT_CLR_S 16
+/* SLC_SLC1_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_INT_CLR (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_CLR_M (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_CLR_V 0x1
+#define SLC_SLC1_TX_SUC_EOF_INT_CLR_S 15
+/* SLC_SLC1_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DONE_INT_CLR (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_CLR_M (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_CLR_V 0x1
+#define SLC_SLC1_TX_DONE_INT_CLR_S 14
+/* SLC_SLC1_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_M (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_V 0x1
+#define SLC_SLC1_TOKEN1_1TO0_INT_CLR_S 13
+/* SLC_SLC1_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_M (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_V 0x1
+#define SLC_SLC1_TOKEN0_1TO0_INT_CLR_S 12
+/* SLC_SLC1_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_OVF_INT_CLR (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_CLR_M (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_CLR_V 0x1
+#define SLC_SLC1_TX_OVF_INT_CLR_S 11
+/* SLC_SLC1_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_UDF_INT_CLR (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_CLR_M (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_CLR_V 0x1
+#define SLC_SLC1_RX_UDF_INT_CLR_S 10
+/* SLC_SLC1_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_START_INT_CLR (BIT(9))
+#define SLC_SLC1_TX_START_INT_CLR_M (BIT(9))
+#define SLC_SLC1_TX_START_INT_CLR_V 0x1
+#define SLC_SLC1_TX_START_INT_CLR_S 9
+/* SLC_SLC1_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_START_INT_CLR (BIT(8))
+#define SLC_SLC1_RX_START_INT_CLR_M (BIT(8))
+#define SLC_SLC1_RX_START_INT_CLR_V 0x1
+#define SLC_SLC1_RX_START_INT_CLR_S 8
+/* SLC_FRHOST_BIT15_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT15_INT_CLR (BIT(7))
+#define SLC_FRHOST_BIT15_INT_CLR_M (BIT(7))
+#define SLC_FRHOST_BIT15_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT15_INT_CLR_S 7
+/* SLC_FRHOST_BIT14_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT14_INT_CLR (BIT(6))
+#define SLC_FRHOST_BIT14_INT_CLR_M (BIT(6))
+#define SLC_FRHOST_BIT14_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT14_INT_CLR_S 6
+/* SLC_FRHOST_BIT13_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT13_INT_CLR (BIT(5))
+#define SLC_FRHOST_BIT13_INT_CLR_M (BIT(5))
+#define SLC_FRHOST_BIT13_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT13_INT_CLR_S 5
+/* SLC_FRHOST_BIT12_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT12_INT_CLR (BIT(4))
+#define SLC_FRHOST_BIT12_INT_CLR_M (BIT(4))
+#define SLC_FRHOST_BIT12_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT12_INT_CLR_S 4
+/* SLC_FRHOST_BIT11_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT11_INT_CLR (BIT(3))
+#define SLC_FRHOST_BIT11_INT_CLR_M (BIT(3))
+#define SLC_FRHOST_BIT11_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT11_INT_CLR_S 3
+/* SLC_FRHOST_BIT10_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT10_INT_CLR (BIT(2))
+#define SLC_FRHOST_BIT10_INT_CLR_M (BIT(2))
+#define SLC_FRHOST_BIT10_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT10_INT_CLR_S 2
+/* SLC_FRHOST_BIT9_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT9_INT_CLR (BIT(1))
+#define SLC_FRHOST_BIT9_INT_CLR_M (BIT(1))
+#define SLC_FRHOST_BIT9_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT9_INT_CLR_S 1
+/* SLC_FRHOST_BIT8_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT8_INT_CLR (BIT(0))
+#define SLC_FRHOST_BIT8_INT_CLR_M (BIT(0))
+#define SLC_FRHOST_BIT8_INT_CLR_V 0x1
+#define SLC_FRHOST_BIT8_INT_CLR_S 0
+
+#define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24)
+/* SLC_SLC1_RX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RX_EMPTY (BIT(17))
+#define SLC_SLC1_RX_EMPTY_M (BIT(17))
+#define SLC_SLC1_RX_EMPTY_V 0x1
+#define SLC_SLC1_RX_EMPTY_S 17
+/* SLC_SLC1_RX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_FULL (BIT(16))
+#define SLC_SLC1_RX_FULL_M (BIT(16))
+#define SLC_SLC1_RX_FULL_V 0x1
+#define SLC_SLC1_RX_FULL_S 16
+/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_EMPTY (BIT(1))
+#define SLC_SLC0_RX_EMPTY_M (BIT(1))
+#define SLC_SLC0_RX_EMPTY_V 0x1
+#define SLC_SLC0_RX_EMPTY_S 1
+/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_FULL (BIT(0))
+#define SLC_SLC0_RX_FULL_M (BIT(0))
+#define SLC_SLC0_RX_FULL_V 0x1
+#define SLC_SLC0_RX_FULL_S 0
+
+#define SLC_0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28)
+/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_RXFIFO_PUSH (BIT(16))
+#define SLC_SLC0_RXFIFO_PUSH_M (BIT(16))
+#define SLC_SLC0_RXFIFO_PUSH_V 0x1
+#define SLC_SLC0_RXFIFO_PUSH_S 16
+/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define SLC_SLC0_RXFIFO_WDATA 0x000001FF
+#define SLC_SLC0_RXFIFO_WDATA_M ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S))
+#define SLC_SLC0_RXFIFO_WDATA_V 0x1FF
+#define SLC_SLC0_RXFIFO_WDATA_S 0
+
+#define SLC_1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2C)
+/* SLC_SLC1_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC1_RXFIFO_PUSH (BIT(16))
+#define SLC_SLC1_RXFIFO_PUSH_M (BIT(16))
+#define SLC_SLC1_RXFIFO_PUSH_V 0x1
+#define SLC_SLC1_RXFIFO_PUSH_S 16
+/* SLC_SLC1_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define SLC_SLC1_RXFIFO_WDATA 0x000001FF
+#define SLC_SLC1_RXFIFO_WDATA_M ((SLC_SLC1_RXFIFO_WDATA_V)<<(SLC_SLC1_RXFIFO_WDATA_S))
+#define SLC_SLC1_RXFIFO_WDATA_V 0x1FF
+#define SLC_SLC1_RXFIFO_WDATA_S 0
+
+#define SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30)
+/* SLC_SLC1_TX_EMPTY : RO ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TX_EMPTY (BIT(17))
+#define SLC_SLC1_TX_EMPTY_M (BIT(17))
+#define SLC_SLC1_TX_EMPTY_V 0x1
+#define SLC_SLC1_TX_EMPTY_S 17
+/* SLC_SLC1_TX_FULL : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_FULL (BIT(16))
+#define SLC_SLC1_TX_FULL_M (BIT(16))
+#define SLC_SLC1_TX_FULL_V 0x1
+#define SLC_SLC1_TX_FULL_S 16
+/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TX_EMPTY (BIT(1))
+#define SLC_SLC0_TX_EMPTY_M (BIT(1))
+#define SLC_SLC0_TX_EMPTY_V 0x1
+#define SLC_SLC0_TX_EMPTY_S 1
+/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_FULL (BIT(0))
+#define SLC_SLC0_TX_FULL_M (BIT(0))
+#define SLC_SLC0_TX_FULL_V 0x1
+#define SLC_SLC0_TX_FULL_S 0
+
+#define SLC_0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34)
+/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TXFIFO_POP (BIT(16))
+#define SLC_SLC0_TXFIFO_POP_M (BIT(16))
+#define SLC_SLC0_TXFIFO_POP_V 0x1
+#define SLC_SLC0_TXFIFO_POP_S 16
+/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SLC_SLC0_TXFIFO_RDATA 0x000007FF
+#define SLC_SLC0_TXFIFO_RDATA_M ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S))
+#define SLC_SLC0_TXFIFO_RDATA_V 0x7FF
+#define SLC_SLC0_TXFIFO_RDATA_S 0
+
+#define SLC_1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38)
+/* SLC_SLC1_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC1_TXFIFO_POP (BIT(16))
+#define SLC_SLC1_TXFIFO_POP_M (BIT(16))
+#define SLC_SLC1_TXFIFO_POP_V 0x1
+#define SLC_SLC1_TXFIFO_POP_S 16
+/* SLC_SLC1_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SLC_SLC1_TXFIFO_RDATA 0x000007FF
+#define SLC_SLC1_TXFIFO_RDATA_M ((SLC_SLC1_TXFIFO_RDATA_V)<<(SLC_SLC1_TXFIFO_RDATA_S))
+#define SLC_SLC1_TXFIFO_RDATA_V 0x7FF
+#define SLC_SLC1_TXFIFO_RDATA_S 0
+
+#define SLC_0RX_LINK_REG (DR_REG_SLC_BASE + 0x3C)
+/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_PARK (BIT(31))
+#define SLC_SLC0_RXLINK_PARK_M (BIT(31))
+#define SLC_SLC0_RXLINK_PARK_V 0x1
+#define SLC_SLC0_RXLINK_PARK_S 31
+/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_RESTART (BIT(30))
+#define SLC_SLC0_RXLINK_RESTART_M (BIT(30))
+#define SLC_SLC0_RXLINK_RESTART_V 0x1
+#define SLC_SLC0_RXLINK_RESTART_S 30
+/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_START (BIT(29))
+#define SLC_SLC0_RXLINK_START_M (BIT(29))
+#define SLC_SLC0_RXLINK_START_V 0x1
+#define SLC_SLC0_RXLINK_START_S 29
+/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_STOP (BIT(28))
+#define SLC_SLC0_RXLINK_STOP_M (BIT(28))
+#define SLC_SLC0_RXLINK_STOP_V 0x1
+#define SLC_SLC0_RXLINK_STOP_S 28
+/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_ADDR 0x000FFFFF
+#define SLC_SLC0_RXLINK_ADDR_M ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S))
+#define SLC_SLC0_RXLINK_ADDR_V 0xFFFFF
+#define SLC_SLC0_RXLINK_ADDR_S 0
+
+#define SLC_0TX_LINK_REG (DR_REG_SLC_BASE + 0x40)
+/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_PARK (BIT(31))
+#define SLC_SLC0_TXLINK_PARK_M (BIT(31))
+#define SLC_SLC0_TXLINK_PARK_V 0x1
+#define SLC_SLC0_TXLINK_PARK_S 31
+/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_RESTART (BIT(30))
+#define SLC_SLC0_TXLINK_RESTART_M (BIT(30))
+#define SLC_SLC0_TXLINK_RESTART_V 0x1
+#define SLC_SLC0_TXLINK_RESTART_S 30
+/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_START (BIT(29))
+#define SLC_SLC0_TXLINK_START_M (BIT(29))
+#define SLC_SLC0_TXLINK_START_V 0x1
+#define SLC_SLC0_TXLINK_START_S 29
+/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_STOP (BIT(28))
+#define SLC_SLC0_TXLINK_STOP_M (BIT(28))
+#define SLC_SLC0_TXLINK_STOP_V 0x1
+#define SLC_SLC0_TXLINK_STOP_S 28
+/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_ADDR 0x000FFFFF
+#define SLC_SLC0_TXLINK_ADDR_M ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S))
+#define SLC_SLC0_TXLINK_ADDR_V 0xFFFFF
+#define SLC_SLC0_TXLINK_ADDR_S 0
+
+#define SLC_1RX_LINK_REG (DR_REG_SLC_BASE + 0x44)
+/* SLC_SLC1_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_PARK (BIT(31))
+#define SLC_SLC1_RXLINK_PARK_M (BIT(31))
+#define SLC_SLC1_RXLINK_PARK_V 0x1
+#define SLC_SLC1_RXLINK_PARK_S 31
+/* SLC_SLC1_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_RESTART (BIT(30))
+#define SLC_SLC1_RXLINK_RESTART_M (BIT(30))
+#define SLC_SLC1_RXLINK_RESTART_V 0x1
+#define SLC_SLC1_RXLINK_RESTART_S 30
+/* SLC_SLC1_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_START (BIT(29))
+#define SLC_SLC1_RXLINK_START_M (BIT(29))
+#define SLC_SLC1_RXLINK_START_V 0x1
+#define SLC_SLC1_RXLINK_START_S 29
+/* SLC_SLC1_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_STOP (BIT(28))
+#define SLC_SLC1_RXLINK_STOP_M (BIT(28))
+#define SLC_SLC1_RXLINK_STOP_V 0x1
+#define SLC_SLC1_RXLINK_STOP_S 28
+/* SLC_SLC1_BT_PACKET : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_BT_PACKET (BIT(20))
+#define SLC_SLC1_BT_PACKET_M (BIT(20))
+#define SLC_SLC1_BT_PACKET_V 0x1
+#define SLC_SLC1_BT_PACKET_S 20
+/* SLC_SLC1_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_ADDR 0x000FFFFF
+#define SLC_SLC1_RXLINK_ADDR_M ((SLC_SLC1_RXLINK_ADDR_V)<<(SLC_SLC1_RXLINK_ADDR_S))
+#define SLC_SLC1_RXLINK_ADDR_V 0xFFFFF
+#define SLC_SLC1_RXLINK_ADDR_S 0
+
+#define SLC_1TX_LINK_REG (DR_REG_SLC_BASE + 0x48)
+/* SLC_SLC1_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_PARK (BIT(31))
+#define SLC_SLC1_TXLINK_PARK_M (BIT(31))
+#define SLC_SLC1_TXLINK_PARK_V 0x1
+#define SLC_SLC1_TXLINK_PARK_S 31
+/* SLC_SLC1_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_RESTART (BIT(30))
+#define SLC_SLC1_TXLINK_RESTART_M (BIT(30))
+#define SLC_SLC1_TXLINK_RESTART_V 0x1
+#define SLC_SLC1_TXLINK_RESTART_S 30
+/* SLC_SLC1_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_START (BIT(29))
+#define SLC_SLC1_TXLINK_START_M (BIT(29))
+#define SLC_SLC1_TXLINK_START_V 0x1
+#define SLC_SLC1_TXLINK_START_S 29
+/* SLC_SLC1_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_STOP (BIT(28))
+#define SLC_SLC1_TXLINK_STOP_M (BIT(28))
+#define SLC_SLC1_TXLINK_STOP_V 0x1
+#define SLC_SLC1_TXLINK_STOP_S 28
+/* SLC_SLC1_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_ADDR 0x000FFFFF
+#define SLC_SLC1_TXLINK_ADDR_M ((SLC_SLC1_TXLINK_ADDR_V)<<(SLC_SLC1_TXLINK_ADDR_S))
+#define SLC_SLC1_TXLINK_ADDR_V 0xFFFFF
+#define SLC_SLC1_TXLINK_ADDR_S 0
+
+#define SLC_INTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x4C)
+/* SLC_SLC1_TOHOST_INTVEC : WO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INTVEC 0x000000FF
+#define SLC_SLC1_TOHOST_INTVEC_M ((SLC_SLC1_TOHOST_INTVEC_V)<<(SLC_SLC1_TOHOST_INTVEC_S))
+#define SLC_SLC1_TOHOST_INTVEC_V 0xFF
+#define SLC_SLC1_TOHOST_INTVEC_S 16
+/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INTVEC 0x000000FF
+#define SLC_SLC0_TOHOST_INTVEC_M ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S))
+#define SLC_SLC0_TOHOST_INTVEC_V 0xFF
+#define SLC_SLC0_TOHOST_INTVEC_S 0
+
+#define SLC_0TOKEN0_REG (DR_REG_SLC_BASE + 0x50)
+/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0 0x00000FFF
+#define SLC_SLC0_TOKEN0_M ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S))
+#define SLC_SLC0_TOKEN0_V 0xFFF
+#define SLC_SLC0_TOKEN0_S 16
+/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_INC_MORE (BIT(14))
+#define SLC_SLC0_TOKEN0_INC_MORE_M (BIT(14))
+#define SLC_SLC0_TOKEN0_INC_MORE_V 0x1
+#define SLC_SLC0_TOKEN0_INC_MORE_S 14
+/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_INC (BIT(13))
+#define SLC_SLC0_TOKEN0_INC_M (BIT(13))
+#define SLC_SLC0_TOKEN0_INC_V 0x1
+#define SLC_SLC0_TOKEN0_INC_S 13
+/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_WR (BIT(12))
+#define SLC_SLC0_TOKEN0_WR_M (BIT(12))
+#define SLC_SLC0_TOKEN0_WR_V 0x1
+#define SLC_SLC0_TOKEN0_WR_S 12
+/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_WDATA 0x00000FFF
+#define SLC_SLC0_TOKEN0_WDATA_M ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S))
+#define SLC_SLC0_TOKEN0_WDATA_V 0xFFF
+#define SLC_SLC0_TOKEN0_WDATA_S 0
+
+#define SLC_0TOKEN1_REG (DR_REG_SLC_BASE + 0x54)
+/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1 0x00000FFF
+#define SLC_SLC0_TOKEN1_M ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S))
+#define SLC_SLC0_TOKEN1_V 0xFFF
+#define SLC_SLC0_TOKEN1_S 16
+/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_INC_MORE (BIT(14))
+#define SLC_SLC0_TOKEN1_INC_MORE_M (BIT(14))
+#define SLC_SLC0_TOKEN1_INC_MORE_V 0x1
+#define SLC_SLC0_TOKEN1_INC_MORE_S 14
+/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_INC (BIT(13))
+#define SLC_SLC0_TOKEN1_INC_M (BIT(13))
+#define SLC_SLC0_TOKEN1_INC_V 0x1
+#define SLC_SLC0_TOKEN1_INC_S 13
+/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_WR (BIT(12))
+#define SLC_SLC0_TOKEN1_WR_M (BIT(12))
+#define SLC_SLC0_TOKEN1_WR_V 0x1
+#define SLC_SLC0_TOKEN1_WR_S 12
+/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_WDATA 0x00000FFF
+#define SLC_SLC0_TOKEN1_WDATA_M ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S))
+#define SLC_SLC0_TOKEN1_WDATA_V 0xFFF
+#define SLC_SLC0_TOKEN1_WDATA_S 0
+
+#define SLC_1TOKEN0_REG (DR_REG_SLC_BASE + 0x58)
+/* SLC_SLC1_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0 0x00000FFF
+#define SLC_SLC1_TOKEN0_M ((SLC_SLC1_TOKEN0_V)<<(SLC_SLC1_TOKEN0_S))
+#define SLC_SLC1_TOKEN0_V 0xFFF
+#define SLC_SLC1_TOKEN0_S 16
+/* SLC_SLC1_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_INC_MORE (BIT(14))
+#define SLC_SLC1_TOKEN0_INC_MORE_M (BIT(14))
+#define SLC_SLC1_TOKEN0_INC_MORE_V 0x1
+#define SLC_SLC1_TOKEN0_INC_MORE_S 14
+/* SLC_SLC1_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_INC (BIT(13))
+#define SLC_SLC1_TOKEN0_INC_M (BIT(13))
+#define SLC_SLC1_TOKEN0_INC_V 0x1
+#define SLC_SLC1_TOKEN0_INC_S 13
+/* SLC_SLC1_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_WR (BIT(12))
+#define SLC_SLC1_TOKEN0_WR_M (BIT(12))
+#define SLC_SLC1_TOKEN0_WR_V 0x1
+#define SLC_SLC1_TOKEN0_WR_S 12
+/* SLC_SLC1_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_WDATA 0x00000FFF
+#define SLC_SLC1_TOKEN0_WDATA_M ((SLC_SLC1_TOKEN0_WDATA_V)<<(SLC_SLC1_TOKEN0_WDATA_S))
+#define SLC_SLC1_TOKEN0_WDATA_V 0xFFF
+#define SLC_SLC1_TOKEN0_WDATA_S 0
+
+#define SLC_1TOKEN1_REG (DR_REG_SLC_BASE + 0x5C)
+/* SLC_SLC1_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1 0x00000FFF
+#define SLC_SLC1_TOKEN1_M ((SLC_SLC1_TOKEN1_V)<<(SLC_SLC1_TOKEN1_S))
+#define SLC_SLC1_TOKEN1_V 0xFFF
+#define SLC_SLC1_TOKEN1_S 16
+/* SLC_SLC1_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_INC_MORE (BIT(14))
+#define SLC_SLC1_TOKEN1_INC_MORE_M (BIT(14))
+#define SLC_SLC1_TOKEN1_INC_MORE_V 0x1
+#define SLC_SLC1_TOKEN1_INC_MORE_S 14
+/* SLC_SLC1_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_INC (BIT(13))
+#define SLC_SLC1_TOKEN1_INC_M (BIT(13))
+#define SLC_SLC1_TOKEN1_INC_V 0x1
+#define SLC_SLC1_TOKEN1_INC_S 13
+/* SLC_SLC1_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_WR (BIT(12))
+#define SLC_SLC1_TOKEN1_WR_M (BIT(12))
+#define SLC_SLC1_TOKEN1_WR_V 0x1
+#define SLC_SLC1_TOKEN1_WR_S 12
+/* SLC_SLC1_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_WDATA 0x00000FFF
+#define SLC_SLC1_TOKEN1_WDATA_M ((SLC_SLC1_TOKEN1_WDATA_V)<<(SLC_SLC1_TOKEN1_WDATA_S))
+#define SLC_SLC1_TOKEN1_WDATA_V 0xFFF
+#define SLC_SLC1_TOKEN1_WDATA_S 0
+
+#define SLC_CONF1_REG (DR_REG_SLC_BASE + 0x60)
+/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CLK_EN (BIT(22))
+#define SLC_CLK_EN_M (BIT(22))
+#define SLC_CLK_EN_V 0x1
+#define SLC_CLK_EN_S 22
+/* SLC_SLC1_RX_STITCH_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RX_STITCH_EN (BIT(21))
+#define SLC_SLC1_RX_STITCH_EN_M (BIT(21))
+#define SLC_SLC1_RX_STITCH_EN_V 0x1
+#define SLC_SLC1_RX_STITCH_EN_S 21
+/* SLC_SLC1_TX_STITCH_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TX_STITCH_EN (BIT(20))
+#define SLC_SLC1_TX_STITCH_EN_M (BIT(20))
+#define SLC_SLC1_TX_STITCH_EN_V 0x1
+#define SLC_SLC1_TX_STITCH_EN_S 20
+/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_HOST_INT_LEVEL_SEL (BIT(19))
+#define SLC_HOST_INT_LEVEL_SEL_M (BIT(19))
+#define SLC_HOST_INT_LEVEL_SEL_V 0x1
+#define SLC_HOST_INT_LEVEL_SEL_S 19
+/* SLC_SLC1_RX_CHECK_SUM_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_CHECK_SUM_EN (BIT(18))
+#define SLC_SLC1_RX_CHECK_SUM_EN_M (BIT(18))
+#define SLC_SLC1_RX_CHECK_SUM_EN_V 0x1
+#define SLC_SLC1_RX_CHECK_SUM_EN_S 18
+/* SLC_SLC1_TX_CHECK_SUM_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_CHECK_SUM_EN (BIT(17))
+#define SLC_SLC1_TX_CHECK_SUM_EN_M (BIT(17))
+#define SLC_SLC1_TX_CHECK_SUM_EN_V 0x1
+#define SLC_SLC1_TX_CHECK_SUM_EN_S 17
+/* SLC_SLC1_CHECK_OWNER : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_CHECK_OWNER (BIT(16))
+#define SLC_SLC1_CHECK_OWNER_M (BIT(16))
+#define SLC_SLC1_CHECK_OWNER_V 0x1
+#define SLC_SLC1_CHECK_OWNER_S 16
+/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_STITCH_EN (BIT(6))
+#define SLC_SLC0_RX_STITCH_EN_M (BIT(6))
+#define SLC_SLC0_RX_STITCH_EN_V 0x1
+#define SLC_SLC0_RX_STITCH_EN_S 6
+/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TX_STITCH_EN (BIT(5))
+#define SLC_SLC0_TX_STITCH_EN_M (BIT(5))
+#define SLC_SLC0_TX_STITCH_EN_V 0x1
+#define SLC_SLC0_TX_STITCH_EN_S 5
+/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_LEN_AUTO_CLR (BIT(4))
+#define SLC_SLC0_LEN_AUTO_CLR_M (BIT(4))
+#define SLC_SLC0_LEN_AUTO_CLR_V 0x1
+#define SLC_SLC0_LEN_AUTO_CLR_S 4
+/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SLC_CMD_HOLD_EN (BIT(3))
+#define SLC_CMD_HOLD_EN_M (BIT(3))
+#define SLC_CMD_HOLD_EN_V 0x1
+#define SLC_CMD_HOLD_EN_S 3
+/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_CHECK_SUM_EN (BIT(2))
+#define SLC_SLC0_RX_CHECK_SUM_EN_M (BIT(2))
+#define SLC_SLC0_RX_CHECK_SUM_EN_V 0x1
+#define SLC_SLC0_RX_CHECK_SUM_EN_S 2
+/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_CHECK_SUM_EN (BIT(1))
+#define SLC_SLC0_TX_CHECK_SUM_EN_M (BIT(1))
+#define SLC_SLC0_TX_CHECK_SUM_EN_V 0x1
+#define SLC_SLC0_TX_CHECK_SUM_EN_S 1
+/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_CHECK_OWNER (BIT(0))
+#define SLC_SLC0_CHECK_OWNER_M (BIT(0))
+#define SLC_SLC0_CHECK_OWNER_V 0x1
+#define SLC_SLC0_CHECK_OWNER_S 0
+
+#define SLC_0_STATE0_REG (DR_REG_SLC_BASE + 0x64)
+/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_STATE0 0xFFFFFFFF
+#define SLC_SLC0_STATE0_M ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S))
+#define SLC_SLC0_STATE0_V 0xFFFFFFFF
+#define SLC_SLC0_STATE0_S 0
+
+#define SLC_0_STATE1_REG (DR_REG_SLC_BASE + 0x68)
+/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_STATE1 0xFFFFFFFF
+#define SLC_SLC0_STATE1_M ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S))
+#define SLC_SLC0_STATE1_V 0xFFFFFFFF
+#define SLC_SLC0_STATE1_S 0
+
+#define SLC_1_STATE0_REG (DR_REG_SLC_BASE + 0x6C)
+/* SLC_SLC1_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC1_STATE0 0xFFFFFFFF
+#define SLC_SLC1_STATE0_M ((SLC_SLC1_STATE0_V)<<(SLC_SLC1_STATE0_S))
+#define SLC_SLC1_STATE0_V 0xFFFFFFFF
+#define SLC_SLC1_STATE0_S 0
+
+#define SLC_1_STATE1_REG (DR_REG_SLC_BASE + 0x70)
+/* SLC_SLC1_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC1_STATE1 0xFFFFFFFF
+#define SLC_SLC1_STATE1_M ((SLC_SLC1_STATE1_V)<<(SLC_SLC1_STATE1_S))
+#define SLC_SLC1_STATE1_V 0xFFFFFFFF
+#define SLC_SLC1_STATE1_S 0
+
+#define SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x74)
+/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */
+/*description: */
+#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF
+#define SLC_TX_PUSH_IDLE_NUM_M ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S))
+#define SLC_TX_PUSH_IDLE_NUM_V 0xFFFF
+#define SLC_TX_PUSH_IDLE_NUM_S 16
+/* SLC_SLC1_TX_DUMMY_MODE : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC1_TX_DUMMY_MODE (BIT(14))
+#define SLC_SLC1_TX_DUMMY_MODE_M (BIT(14))
+#define SLC_SLC1_TX_DUMMY_MODE_V 0x1
+#define SLC_SLC1_TX_DUMMY_MODE_S 14
+/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: */
+#define SLC_HDA_MAP_128K (BIT(13))
+#define SLC_HDA_MAP_128K_M (BIT(13))
+#define SLC_HDA_MAP_128K_V 0x1
+#define SLC_HDA_MAP_128K_S 13
+/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TX_DUMMY_MODE (BIT(12))
+#define SLC_SLC0_TX_DUMMY_MODE_M (BIT(12))
+#define SLC_SLC0_TX_DUMMY_MODE_V 0x1
+#define SLC_SLC0_TX_DUMMY_MODE_S 12
+/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
+/*description: */
+#define SLC_FIFO_MAP_ENA 0x0000000F
+#define SLC_FIFO_MAP_ENA_M ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S))
+#define SLC_FIFO_MAP_ENA_V 0xF
+#define SLC_FIFO_MAP_ENA_S 8
+/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: */
+#define SLC_TXEOF_ENA 0x0000003F
+#define SLC_TXEOF_ENA_M ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S))
+#define SLC_TXEOF_ENA_V 0x3F
+#define SLC_TXEOF_ENA_S 0
+
+#define SLC_0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x78)
+/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_DES_ADDR_M ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S))
+#define SLC_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_DES_ADDR_S 0
+
+#define SLC_0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x7C)
+/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S 0
+
+#define SLC_0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x80)
+/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S 0
+
+#define SLC_1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x84)
+/* SLC_SLC1_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC1_TO_EOF_DES_ADDR_M ((SLC_SLC1_TO_EOF_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_DES_ADDR_S))
+#define SLC_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC1_TO_EOF_DES_ADDR_S 0
+
+#define SLC_1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88)
+/* SLC_SLC1_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC1_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_SUC_EOF_DES_ADDR_S))
+#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC1_TX_SUC_EOF_DES_ADDR_S 0
+
+#define SLC_1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8C)
+/* SLC_SLC1_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC1_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC1_TO_EOF_BFR_DES_ADDR_S))
+#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC1_TO_EOF_BFR_DES_ADDR_S 0
+
+#define SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0x90)
+/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SLC_AHB_TESTADDR 0x00000003
+#define SLC_AHB_TESTADDR_M ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S))
+#define SLC_AHB_TESTADDR_V 0x3
+#define SLC_AHB_TESTADDR_S 4
+/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define SLC_AHB_TESTMODE 0x00000007
+#define SLC_AHB_TESTMODE_M ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S))
+#define SLC_AHB_TESTMODE_V 0x7
+#define SLC_AHB_TESTMODE_S 0
+
+#define SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0x94)
+/* SLC_FUNC2_ACC_STATE : RO ;bitpos:[28:24] ;default: 5'b0 ; */
+/*description: */
+#define SLC_FUNC2_ACC_STATE 0x0000001F
+#define SLC_FUNC2_ACC_STATE_M ((SLC_FUNC2_ACC_STATE_V)<<(SLC_FUNC2_ACC_STATE_S))
+#define SLC_FUNC2_ACC_STATE_V 0x1F
+#define SLC_FUNC2_ACC_STATE_S 24
+/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */
+/*description: */
+#define SLC_FUNC1_ACC_STATE 0x0000001F
+#define SLC_FUNC1_ACC_STATE_M ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S))
+#define SLC_FUNC1_ACC_STATE_V 0x1F
+#define SLC_FUNC1_ACC_STATE_S 16
+/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */
+/*description: */
+#define SLC_BUS_ST 0x00000007
+#define SLC_BUS_ST_M ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S))
+#define SLC_BUS_ST_V 0x7
+#define SLC_BUS_ST_S 12
+/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SDIO_WAKEUP (BIT(8))
+#define SLC_SDIO_WAKEUP_M (BIT(8))
+#define SLC_SDIO_WAKEUP_V 0x1
+#define SLC_SDIO_WAKEUP_S 8
+/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: */
+#define SLC_FUNC_ST 0x0000000F
+#define SLC_FUNC_ST_M ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S))
+#define SLC_FUNC_ST_V 0xF
+#define SLC_FUNC_ST_S 4
+/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define SLC_CMD_ST 0x00000007
+#define SLC_CMD_ST_M ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S))
+#define SLC_CMD_ST_V 0x7
+#define SLC_CMD_ST_S 0
+
+#define SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0x98)
+/* SLC_SLC1_RD_RETRY_THRESHOLD : R/W ;bitpos:[31:21] ;default: 11'h80 ; */
+/*description: */
+#define SLC_SLC1_RD_RETRY_THRESHOLD 0x000007FF
+#define SLC_SLC1_RD_RETRY_THRESHOLD_M ((SLC_SLC1_RD_RETRY_THRESHOLD_V)<<(SLC_SLC1_RD_RETRY_THRESHOLD_S))
+#define SLC_SLC1_RD_RETRY_THRESHOLD_V 0x7FF
+#define SLC_SLC1_RD_RETRY_THRESHOLD_S 21
+/* SLC_SLC1_RX_FILL_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RX_FILL_EN (BIT(20))
+#define SLC_SLC1_RX_FILL_EN_M (BIT(20))
+#define SLC_SLC1_RX_FILL_EN_V 0x1
+#define SLC_SLC1_RX_FILL_EN_S 20
+/* SLC_SLC1_RX_EOF_MODE : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_MODE (BIT(19))
+#define SLC_SLC1_RX_EOF_MODE_M (BIT(19))
+#define SLC_SLC1_RX_EOF_MODE_V 0x1
+#define SLC_SLC1_RX_EOF_MODE_S 19
+/* SLC_SLC1_RX_FILL_MODE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_FILL_MODE (BIT(18))
+#define SLC_SLC1_RX_FILL_MODE_M (BIT(18))
+#define SLC_SLC1_RX_FILL_MODE_V 0x1
+#define SLC_SLC1_RX_FILL_MODE_S 18
+/* SLC_SLC1_INFOR_NO_REPLACE : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_INFOR_NO_REPLACE (BIT(17))
+#define SLC_SLC1_INFOR_NO_REPLACE_M (BIT(17))
+#define SLC_SLC1_INFOR_NO_REPLACE_V 0x1
+#define SLC_SLC1_INFOR_NO_REPLACE_S 17
+/* SLC_SLC1_TOKEN_NO_REPLACE : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC1_TOKEN_NO_REPLACE (BIT(16))
+#define SLC_SLC1_TOKEN_NO_REPLACE_M (BIT(16))
+#define SLC_SLC1_TOKEN_NO_REPLACE_V 0x1
+#define SLC_SLC1_TOKEN_NO_REPLACE_S 16
+/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */
+/*description: */
+#define SLC_SLC0_RD_RETRY_THRESHOLD 0x000007FF
+#define SLC_SLC0_RD_RETRY_THRESHOLD_M ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S))
+#define SLC_SLC0_RD_RETRY_THRESHOLD_V 0x7FF
+#define SLC_SLC0_RD_RETRY_THRESHOLD_S 5
+/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_FILL_EN (BIT(4))
+#define SLC_SLC0_RX_FILL_EN_M (BIT(4))
+#define SLC_SLC0_RX_FILL_EN_V 0x1
+#define SLC_SLC0_RX_FILL_EN_S 4
+/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_MODE (BIT(3))
+#define SLC_SLC0_RX_EOF_MODE_M (BIT(3))
+#define SLC_SLC0_RX_EOF_MODE_V 0x1
+#define SLC_SLC0_RX_EOF_MODE_S 3
+/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_FILL_MODE (BIT(2))
+#define SLC_SLC0_RX_FILL_MODE_M (BIT(2))
+#define SLC_SLC0_RX_FILL_MODE_V 0x1
+#define SLC_SLC0_RX_FILL_MODE_S 2
+/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_INFOR_NO_REPLACE (BIT(1))
+#define SLC_SLC0_INFOR_NO_REPLACE_M (BIT(1))
+#define SLC_SLC0_INFOR_NO_REPLACE_V 0x1
+#define SLC_SLC0_INFOR_NO_REPLACE_S 1
+/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN_NO_REPLACE (BIT(0))
+#define SLC_SLC0_TOKEN_NO_REPLACE_M (BIT(0))
+#define SLC_SLC0_TOKEN_NO_REPLACE_V 0x1
+#define SLC_SLC0_TOKEN_NO_REPLACE_S 0
+
+#define SLC_0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0x9C)
+/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_DSCR 0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_M ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S))
+#define SLC_SLC0_TXLINK_DSCR_V 0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_S 0
+
+#define SLC_0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xA0)
+/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF0_M ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S))
+#define SLC_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF0_S 0
+
+#define SLC_0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xA4)
+/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF1_M ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S))
+#define SLC_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF1_S 0
+
+#define SLC_0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xA8)
+/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_DSCR 0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_M ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S))
+#define SLC_SLC0_RXLINK_DSCR_V 0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_S 0
+
+#define SLC_0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xAC)
+/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF0_M ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S))
+#define SLC_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF0_S 0
+
+#define SLC_0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xB0)
+/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF1_M ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S))
+#define SLC_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF1_S 0
+
+#define SLC_1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xB4)
+/* SLC_SLC1_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_DSCR 0xFFFFFFFF
+#define SLC_SLC1_TXLINK_DSCR_M ((SLC_SLC1_TXLINK_DSCR_V)<<(SLC_SLC1_TXLINK_DSCR_S))
+#define SLC_SLC1_TXLINK_DSCR_V 0xFFFFFFFF
+#define SLC_SLC1_TXLINK_DSCR_S 0
+
+#define SLC_1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xB8)
+/* SLC_SLC1_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFF
+#define SLC_SLC1_TXLINK_DSCR_BF0_M ((SLC_SLC1_TXLINK_DSCR_BF0_V)<<(SLC_SLC1_TXLINK_DSCR_BF0_S))
+#define SLC_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFF
+#define SLC_SLC1_TXLINK_DSCR_BF0_S 0
+
+#define SLC_1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xBC)
+/* SLC_SLC1_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFF
+#define SLC_SLC1_TXLINK_DSCR_BF1_M ((SLC_SLC1_TXLINK_DSCR_BF1_V)<<(SLC_SLC1_TXLINK_DSCR_BF1_S))
+#define SLC_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFF
+#define SLC_SLC1_TXLINK_DSCR_BF1_S 0
+
+#define SLC_1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xC0)
+/* SLC_SLC1_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_DSCR 0xFFFFFFFF
+#define SLC_SLC1_RXLINK_DSCR_M ((SLC_SLC1_RXLINK_DSCR_V)<<(SLC_SLC1_RXLINK_DSCR_S))
+#define SLC_SLC1_RXLINK_DSCR_V 0xFFFFFFFF
+#define SLC_SLC1_RXLINK_DSCR_S 0
+
+#define SLC_1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xC4)
+/* SLC_SLC1_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFF
+#define SLC_SLC1_RXLINK_DSCR_BF0_M ((SLC_SLC1_RXLINK_DSCR_BF0_V)<<(SLC_SLC1_RXLINK_DSCR_BF0_S))
+#define SLC_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFF
+#define SLC_SLC1_RXLINK_DSCR_BF0_S 0
+
+#define SLC_1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xC8)
+/* SLC_SLC1_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFF
+#define SLC_SLC1_RXLINK_DSCR_BF1_M ((SLC_SLC1_RXLINK_DSCR_BF1_V)<<(SLC_SLC1_RXLINK_DSCR_BF1_S))
+#define SLC_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFF
+#define SLC_SLC1_RXLINK_DSCR_BF1_S 0
+
+#define SLC_0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xCC)
+/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S 0
+
+#define SLC_1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xD0)
+/* SLC_SLC1_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC1_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC1_TX_ERR_EOF_DES_ADDR_S))
+#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC1_TX_ERR_EOF_DES_ADDR_S 0
+
+#define SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xD4)
+/* SLC_SLC1_TOKEN : RO ;bitpos:[27:16] ;default: 12'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN 0x00000FFF
+#define SLC_SLC1_TOKEN_M ((SLC_SLC1_TOKEN_V)<<(SLC_SLC1_TOKEN_S))
+#define SLC_SLC1_TOKEN_V 0xFFF
+#define SLC_SLC1_TOKEN_S 16
+/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN 0x00000FFF
+#define SLC_SLC0_TOKEN_M ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S))
+#define SLC_SLC0_TOKEN_V 0xFFF
+#define SLC_SLC0_TOKEN_S 0
+
+#define SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xD8)
+/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */
+/*description: */
+#define SLC_WR_RETRY_THRESHOLD 0x000007FF
+#define SLC_WR_RETRY_THRESHOLD_M ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S))
+#define SLC_WR_RETRY_THRESHOLD_V 0x7FF
+#define SLC_WR_RETRY_THRESHOLD_S 0
+
+#define SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xDC)
+/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_CMD_CONTENT0 0xFFFFFFFF
+#define SLC_CMD_CONTENT0_M ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S))
+#define SLC_CMD_CONTENT0_V 0xFFFFFFFF
+#define SLC_CMD_CONTENT0_S 0
+
+#define SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xE0)
+/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_CMD_CONTENT1 0xFFFFFFFF
+#define SLC_CMD_CONTENT1_M ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S))
+#define SLC_CMD_CONTENT1_V 0xFFFFFFFF
+#define SLC_CMD_CONTENT1_S 0
+
+#define SLC_0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xE4)
+/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_NEW_PKT_IND (BIT(28))
+#define SLC_SLC0_TX_NEW_PKT_IND_M (BIT(28))
+#define SLC_SLC0_TX_NEW_PKT_IND_V 0x1
+#define SLC_SLC0_TX_NEW_PKT_IND_S 28
+/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_NEW_PKT_IND (BIT(27))
+#define SLC_SLC0_RX_NEW_PKT_IND_M (BIT(27))
+#define SLC_SLC0_RX_NEW_PKT_IND_V 0x1
+#define SLC_SLC0_RX_NEW_PKT_IND_S 27
+/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_GET_USED_DSCR (BIT(26))
+#define SLC_SLC0_TX_GET_USED_DSCR_M (BIT(26))
+#define SLC_SLC0_TX_GET_USED_DSCR_V 0x1
+#define SLC_SLC0_TX_GET_USED_DSCR_S 26
+/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_GET_USED_DSCR (BIT(25))
+#define SLC_SLC0_RX_GET_USED_DSCR_M (BIT(25))
+#define SLC_SLC0_RX_GET_USED_DSCR_V 0x1
+#define SLC_SLC0_RX_GET_USED_DSCR_S 25
+/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_PACKET_LOAD_EN (BIT(24))
+#define SLC_SLC0_TX_PACKET_LOAD_EN_M (BIT(24))
+#define SLC_SLC0_TX_PACKET_LOAD_EN_V 0x1
+#define SLC_SLC0_TX_PACKET_LOAD_EN_S 24
+/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_PACKET_LOAD_EN (BIT(23))
+#define SLC_SLC0_RX_PACKET_LOAD_EN_M (BIT(23))
+#define SLC_SLC0_RX_PACKET_LOAD_EN_V 0x1
+#define SLC_SLC0_RX_PACKET_LOAD_EN_S 23
+/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_LEN_INC_MORE (BIT(22))
+#define SLC_SLC0_LEN_INC_MORE_M (BIT(22))
+#define SLC_SLC0_LEN_INC_MORE_V 0x1
+#define SLC_SLC0_LEN_INC_MORE_S 22
+/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_LEN_INC (BIT(21))
+#define SLC_SLC0_LEN_INC_M (BIT(21))
+#define SLC_SLC0_LEN_INC_V 0x1
+#define SLC_SLC0_LEN_INC_S 21
+/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_LEN_WR (BIT(20))
+#define SLC_SLC0_LEN_WR_M (BIT(20))
+#define SLC_SLC0_LEN_WR_V 0x1
+#define SLC_SLC0_LEN_WR_S 20
+/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_LEN_WDATA 0x000FFFFF
+#define SLC_SLC0_LEN_WDATA_M ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S))
+#define SLC_SLC0_LEN_WDATA_V 0xFFFFF
+#define SLC_SLC0_LEN_WDATA_S 0
+
+#define SLC_0_LENGTH_REG (DR_REG_SLC_BASE + 0xE8)
+/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_LEN 0x000FFFFF
+#define SLC_SLC0_LEN_M ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S))
+#define SLC_SLC0_LEN_V 0xFFFFF
+#define SLC_SLC0_LEN_S 0
+
+#define SLC_0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xEC)
+/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S 0
+
+#define SLC_0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF0)
+/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S 0
+
+#define SLC_0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xF4)
+/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S 0
+
+#define SLC_0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF8)
+/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S 0
+
+#define SLC_0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0xFC)
+/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S 0
+
+#define SLC_0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x100)
+/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S 0
+
+#define SLC_0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x104)
+/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S 0
+
+#define SLC_0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x108)
+/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S 0
+
+#define SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x114)
+/* SLC_SLC1_SEQ_POSITION : R/W ;bitpos:[15:8] ;default: 8'h5 ; */
+/*description: */
+#define SLC_SLC1_SEQ_POSITION 0x000000FF
+#define SLC_SLC1_SEQ_POSITION_M ((SLC_SLC1_SEQ_POSITION_V)<<(SLC_SLC1_SEQ_POSITION_S))
+#define SLC_SLC1_SEQ_POSITION_V 0xFF
+#define SLC_SLC1_SEQ_POSITION_S 8
+/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */
+/*description: */
+#define SLC_SLC0_SEQ_POSITION 0x000000FF
+#define SLC_SLC0_SEQ_POSITION_M ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S))
+#define SLC_SLC0_SEQ_POSITION_V 0xFF
+#define SLC_SLC0_SEQ_POSITION_S 0
+
+#define SLC_0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x118)
+/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_REC_LIM 0x000003FF
+#define SLC_SLC0_RX_DSCR_REC_LIM_M ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S))
+#define SLC_SLC0_RX_DSCR_REC_LIM_V 0x3FF
+#define SLC_SLC0_RX_DSCR_REC_LIM_S 0
+
+#define SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x11C)
+/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT3_CRC_ERR_CNT 0x000000FF
+#define SLC_DAT3_CRC_ERR_CNT_M ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S))
+#define SLC_DAT3_CRC_ERR_CNT_V 0xFF
+#define SLC_DAT3_CRC_ERR_CNT_S 24
+/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT2_CRC_ERR_CNT 0x000000FF
+#define SLC_DAT2_CRC_ERR_CNT_M ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S))
+#define SLC_DAT2_CRC_ERR_CNT_V 0xFF
+#define SLC_DAT2_CRC_ERR_CNT_S 16
+/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT1_CRC_ERR_CNT 0x000000FF
+#define SLC_DAT1_CRC_ERR_CNT_M ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S))
+#define SLC_DAT1_CRC_ERR_CNT_V 0xFF
+#define SLC_DAT1_CRC_ERR_CNT_S 8
+/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT0_CRC_ERR_CNT 0x000000FF
+#define SLC_DAT0_CRC_ERR_CNT_M ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S))
+#define SLC_DAT0_CRC_ERR_CNT_V 0xFF
+#define SLC_DAT0_CRC_ERR_CNT_S 0
+
+#define SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x120)
+/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SLC_ERR_CNT_CLR (BIT(31))
+#define SLC_ERR_CNT_CLR_M (BIT(31))
+#define SLC_ERR_CNT_CLR_V 0x1
+#define SLC_ERR_CNT_CLR_S 31
+/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SLC_CMD_CRC_ERR_CNT 0x000000FF
+#define SLC_CMD_CRC_ERR_CNT_M ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S))
+#define SLC_CMD_CRC_ERR_CNT_V 0xFF
+#define SLC_CMD_CRC_ERR_CNT_S 0
+
+#define SLC_0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x124)
+/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_EOF_START_DES_ADDR 0xFFFFFFFF
+#define SLC_SLC0_EOF_START_DES_ADDR_M ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S))
+#define SLC_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_EOF_START_DES_ADDR_S 0
+
+#define SLC_0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x128)
+/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S 0
+
+#define SLC_0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x12C)
+/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_M ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S))
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_S 0
+
+#define SLC_0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x130)
+/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFF
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFF
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S 0
+
+#define SLC_0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x134)
+/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_GET_EOF_OCC (BIT(16))
+#define SLC_SLC0_RX_GET_EOF_OCC_M (BIT(16))
+#define SLC_SLC0_RX_GET_EOF_OCC_V 0x1
+#define SLC_SLC0_RX_GET_EOF_OCC_S 16
+/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_CNT_LAT 0x000003FF
+#define SLC_SLC0_RX_DSCR_CNT_LAT_M ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S))
+#define SLC_SLC0_RX_DSCR_CNT_LAT_V 0x3FF
+#define SLC_SLC0_RX_DSCR_CNT_LAT_S 0
+
+#define SLC_0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x138)
+/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */
+/*description: */
+#define SLC_SLC0_LEN_LIM 0x000FFFFF
+#define SLC_SLC0_LEN_LIM_M ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S))
+#define SLC_SLC0_LEN_LIM_V 0xFFFFF
+#define SLC_SLC0_LEN_LIM_S 0
+
+#define SLC_0INT_ST1_REG (DR_REG_SLC_BASE + 0x13C)
+/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V 0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S 26
+/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ST1 (BIT(25))
+#define SLC_CMD_DTC_INT_ST1_M (BIT(25))
+#define SLC_CMD_DTC_INT_ST1_V 0x1
+#define SLC_CMD_DTC_INT_ST1_S 25
+/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V 0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S 24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V 0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S 23
+/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V 0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S 22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V 0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S 20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V 0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S 19
+/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ST1 (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST1_M (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST1_V 0x1
+#define SLC_SLC0_TOHOST_INT_ST1_S 18
+/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ST1 (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST1_M (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST1_V 0x1
+#define SLC_SLC0_RX_EOF_INT_ST1_S 17
+/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ST1 (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST1_M (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST1_V 0x1
+#define SLC_SLC0_RX_DONE_INT_ST1_S 16
+/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V 0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S 15
+/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ST1 (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST1_M (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST1_V 0x1
+#define SLC_SLC0_TX_DONE_INT_ST1_S 14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V 0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S 13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V 0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S 12
+/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ST1 (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST1_M (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST1_V 0x1
+#define SLC_SLC0_TX_OVF_INT_ST1_S 11
+/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ST1 (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST1_M (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST1_V 0x1
+#define SLC_SLC0_RX_UDF_INT_ST1_S 10
+/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ST1 (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST1_M (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST1_V 0x1
+#define SLC_SLC0_TX_START_INT_ST1_S 9
+/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ST1 (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST1_M (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST1_V 0x1
+#define SLC_SLC0_RX_START_INT_ST1_S 8
+/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ST1 (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST1_M (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT7_INT_ST1_S 7
+/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ST1 (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST1_M (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT6_INT_ST1_S 6
+/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ST1 (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST1_M (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT5_INT_ST1_S 5
+/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ST1 (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST1_M (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT4_INT_ST1_S 4
+/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ST1 (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST1_M (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT3_INT_ST1_S 3
+/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ST1 (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST1_M (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT2_INT_ST1_S 2
+/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ST1 (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST1_M (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT1_INT_ST1_S 1
+/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ST1 (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST1_M (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT0_INT_ST1_S 0
+
+#define SLC_0INT_ENA1_REG (DR_REG_SLC_BASE + 0x140)
+/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S 26
+/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ENA1 (BIT(25))
+#define SLC_CMD_DTC_INT_ENA1_M (BIT(25))
+#define SLC_CMD_DTC_INT_ENA1_V 0x1
+#define SLC_CMD_DTC_INT_ENA1_S 25
+/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S 24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S 23
+/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V 0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S 22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S 20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S 19
+/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ENA1 (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA1_M (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA1_V 0x1
+#define SLC_SLC0_TOHOST_INT_ENA1_S 18
+/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ENA1 (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA1_M (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA1_V 0x1
+#define SLC_SLC0_RX_EOF_INT_ENA1_S 17
+/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ENA1 (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA1_M (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA1_V 0x1
+#define SLC_SLC0_RX_DONE_INT_ENA1_S 16
+/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S 15
+/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ENA1 (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA1_M (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_DONE_INT_ENA1_S 14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S 13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S 12
+/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ENA1 (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA1_M (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_OVF_INT_ENA1_S 11
+/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ENA1 (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA1_M (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA1_V 0x1
+#define SLC_SLC0_RX_UDF_INT_ENA1_S 10
+/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ENA1 (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA1_M (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA1_V 0x1
+#define SLC_SLC0_TX_START_INT_ENA1_S 9
+/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ENA1 (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA1_M (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA1_V 0x1
+#define SLC_SLC0_RX_START_INT_ENA1_S 8
+/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ENA1 (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA1_M (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT7_INT_ENA1_S 7
+/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ENA1 (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA1_M (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT6_INT_ENA1_S 6
+/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ENA1 (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA1_M (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT5_INT_ENA1_S 5
+/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ENA1 (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA1_M (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT4_INT_ENA1_S 4
+/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ENA1 (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA1_M (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT3_INT_ENA1_S 3
+/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ENA1 (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA1_M (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT2_INT_ENA1_S 2
+/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ENA1 (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA1_M (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT1_INT_ENA1_S 1
+/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ENA1 (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA1_M (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT0_INT_ENA1_S 0
+
+#define SLC_1INT_ST1_REG (DR_REG_SLC_BASE + 0x144)
+/* SLC_SLC1_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ST1_M (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ST1_V 0x1
+#define SLC_SLC1_TX_ERR_EOF_INT_ST1_S 24
+/* SLC_SLC1_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_M (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_V 0x1
+#define SLC_SLC1_WR_RETRY_DONE_INT_ST1_S 23
+/* SLC_SLC1_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ST1_M (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ST1_V 0x1
+#define SLC_SLC1_HOST_RD_ACK_INT_ST1_S 22
+/* SLC_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_M (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x1
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21
+/* SLC_SLC1_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_M (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_V 0x1
+#define SLC_SLC1_RX_DSCR_ERR_INT_ST1_S 20
+/* SLC_SLC1_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_M (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_V 0x1
+#define SLC_SLC1_TX_DSCR_ERR_INT_ST1_S 19
+/* SLC_SLC1_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INT_ST1 (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ST1_M (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ST1_V 0x1
+#define SLC_SLC1_TOHOST_INT_ST1_S 18
+/* SLC_SLC1_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_INT_ST1 (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ST1_M (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ST1_V 0x1
+#define SLC_SLC1_RX_EOF_INT_ST1_S 17
+/* SLC_SLC1_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DONE_INT_ST1 (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ST1_M (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ST1_V 0x1
+#define SLC_SLC1_RX_DONE_INT_ST1_S 16
+/* SLC_SLC1_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ST1_M (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ST1_V 0x1
+#define SLC_SLC1_TX_SUC_EOF_INT_ST1_S 15
+/* SLC_SLC1_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DONE_INT_ST1 (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ST1_M (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ST1_V 0x1
+#define SLC_SLC1_TX_DONE_INT_ST1_S 14
+/* SLC_SLC1_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_M (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_V 0x1
+#define SLC_SLC1_TOKEN1_1TO0_INT_ST1_S 13
+/* SLC_SLC1_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_M (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_V 0x1
+#define SLC_SLC1_TOKEN0_1TO0_INT_ST1_S 12
+/* SLC_SLC1_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_OVF_INT_ST1 (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ST1_M (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ST1_V 0x1
+#define SLC_SLC1_TX_OVF_INT_ST1_S 11
+/* SLC_SLC1_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_UDF_INT_ST1 (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ST1_M (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ST1_V 0x1
+#define SLC_SLC1_RX_UDF_INT_ST1_S 10
+/* SLC_SLC1_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_START_INT_ST1 (BIT(9))
+#define SLC_SLC1_TX_START_INT_ST1_M (BIT(9))
+#define SLC_SLC1_TX_START_INT_ST1_V 0x1
+#define SLC_SLC1_TX_START_INT_ST1_S 9
+/* SLC_SLC1_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_START_INT_ST1 (BIT(8))
+#define SLC_SLC1_RX_START_INT_ST1_M (BIT(8))
+#define SLC_SLC1_RX_START_INT_ST1_V 0x1
+#define SLC_SLC1_RX_START_INT_ST1_S 8
+/* SLC_FRHOST_BIT15_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT15_INT_ST1 (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ST1_M (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT15_INT_ST1_S 7
+/* SLC_FRHOST_BIT14_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT14_INT_ST1 (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ST1_M (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT14_INT_ST1_S 6
+/* SLC_FRHOST_BIT13_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT13_INT_ST1 (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ST1_M (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT13_INT_ST1_S 5
+/* SLC_FRHOST_BIT12_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT12_INT_ST1 (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ST1_M (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT12_INT_ST1_S 4
+/* SLC_FRHOST_BIT11_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT11_INT_ST1 (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ST1_M (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT11_INT_ST1_S 3
+/* SLC_FRHOST_BIT10_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT10_INT_ST1 (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ST1_M (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT10_INT_ST1_S 2
+/* SLC_FRHOST_BIT9_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT9_INT_ST1 (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ST1_M (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT9_INT_ST1_S 1
+/* SLC_FRHOST_BIT8_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT8_INT_ST1 (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ST1_M (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ST1_V 0x1
+#define SLC_FRHOST_BIT8_INT_ST1_S 0
+
+#define SLC_1INT_ENA1_REG (DR_REG_SLC_BASE + 0x148)
+/* SLC_SLC1_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_M (BIT(24))
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_ERR_EOF_INT_ENA1_S 24
+/* SLC_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_M (BIT(23))
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x1
+#define SLC_SLC1_WR_RETRY_DONE_INT_ENA1_S 23
+/* SLC_SLC1_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_M (BIT(22))
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_V 0x1
+#define SLC_SLC1_HOST_RD_ACK_INT_ENA1_S 22
+/* SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21))
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21
+/* SLC_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_M (BIT(20))
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x1
+#define SLC_SLC1_RX_DSCR_ERR_INT_ENA1_S 20
+/* SLC_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_M (BIT(19))
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_DSCR_ERR_INT_ENA1_S 19
+/* SLC_SLC1_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOHOST_INT_ENA1 (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ENA1_M (BIT(18))
+#define SLC_SLC1_TOHOST_INT_ENA1_V 0x1
+#define SLC_SLC1_TOHOST_INT_ENA1_S 18
+/* SLC_SLC1_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_EOF_INT_ENA1 (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ENA1_M (BIT(17))
+#define SLC_SLC1_RX_EOF_INT_ENA1_V 0x1
+#define SLC_SLC1_RX_EOF_INT_ENA1_S 17
+/* SLC_SLC1_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_DONE_INT_ENA1 (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ENA1_M (BIT(16))
+#define SLC_SLC1_RX_DONE_INT_ENA1_V 0x1
+#define SLC_SLC1_RX_DONE_INT_ENA1_S 16
+/* SLC_SLC1_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_M (BIT(15))
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_SUC_EOF_INT_ENA1_S 15
+/* SLC_SLC1_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_DONE_INT_ENA1 (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ENA1_M (BIT(14))
+#define SLC_SLC1_TX_DONE_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_DONE_INT_ENA1_S 14
+/* SLC_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_M (BIT(13))
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x1
+#define SLC_SLC1_TOKEN1_1TO0_INT_ENA1_S 13
+/* SLC_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_M (BIT(12))
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x1
+#define SLC_SLC1_TOKEN0_1TO0_INT_ENA1_S 12
+/* SLC_SLC1_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_OVF_INT_ENA1 (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ENA1_M (BIT(11))
+#define SLC_SLC1_TX_OVF_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_OVF_INT_ENA1_S 11
+/* SLC_SLC1_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_UDF_INT_ENA1 (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ENA1_M (BIT(10))
+#define SLC_SLC1_RX_UDF_INT_ENA1_V 0x1
+#define SLC_SLC1_RX_UDF_INT_ENA1_S 10
+/* SLC_SLC1_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_TX_START_INT_ENA1 (BIT(9))
+#define SLC_SLC1_TX_START_INT_ENA1_M (BIT(9))
+#define SLC_SLC1_TX_START_INT_ENA1_V 0x1
+#define SLC_SLC1_TX_START_INT_ENA1_S 9
+/* SLC_SLC1_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC1_RX_START_INT_ENA1 (BIT(8))
+#define SLC_SLC1_RX_START_INT_ENA1_M (BIT(8))
+#define SLC_SLC1_RX_START_INT_ENA1_V 0x1
+#define SLC_SLC1_RX_START_INT_ENA1_S 8
+/* SLC_FRHOST_BIT15_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT15_INT_ENA1 (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ENA1_M (BIT(7))
+#define SLC_FRHOST_BIT15_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT15_INT_ENA1_S 7
+/* SLC_FRHOST_BIT14_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT14_INT_ENA1 (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ENA1_M (BIT(6))
+#define SLC_FRHOST_BIT14_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT14_INT_ENA1_S 6
+/* SLC_FRHOST_BIT13_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT13_INT_ENA1 (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ENA1_M (BIT(5))
+#define SLC_FRHOST_BIT13_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT13_INT_ENA1_S 5
+/* SLC_FRHOST_BIT12_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT12_INT_ENA1 (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ENA1_M (BIT(4))
+#define SLC_FRHOST_BIT12_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT12_INT_ENA1_S 4
+/* SLC_FRHOST_BIT11_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT11_INT_ENA1 (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ENA1_M (BIT(3))
+#define SLC_FRHOST_BIT11_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT11_INT_ENA1_S 3
+/* SLC_FRHOST_BIT10_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT10_INT_ENA1 (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ENA1_M (BIT(2))
+#define SLC_FRHOST_BIT10_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT10_INT_ENA1_S 2
+/* SLC_FRHOST_BIT9_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT9_INT_ENA1 (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ENA1_M (BIT(1))
+#define SLC_FRHOST_BIT9_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT9_INT_ENA1_S 1
+/* SLC_FRHOST_BIT8_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT8_INT_ENA1 (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ENA1_M (BIT(0))
+#define SLC_FRHOST_BIT8_INT_ENA1_V 0x1
+#define SLC_FRHOST_BIT8_INT_ENA1_S 0
+
+#define SLC_DATE_REG (DR_REG_SLC_BASE + 0x1F8)
+/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16022500 ; */
+/*description: */
+#define SLC_DATE 0xFFFFFFFF
+#define SLC_DATE_M ((SLC_DATE_V)<<(SLC_DATE_S))
+#define SLC_DATE_V 0xFFFFFFFF
+#define SLC_DATE_S 0
+
+#define SLC_ID_REG (DR_REG_SLC_BASE + 0x1FC)
+/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */
+/*description: */
+#define SLC_ID 0xFFFFFFFF
+#define SLC_ID_M ((SLC_ID_V)<<(SLC_ID_S))
+#define SLC_ID_V 0xFFFFFFFF
+#define SLC_ID_S 0
+
+
+
+
+#endif /*_SOC_SLC_REG_H_ */
+
+
--- /dev/null
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SLC_STRUCT_H_
+#define _SOC_SLC_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+ union {
+ struct {
+ uint32_t slc0_tx_rst: 1;
+ uint32_t slc0_rx_rst: 1;
+ uint32_t ahbm_fifo_rst: 1;
+ uint32_t ahbm_rst: 1;
+ uint32_t slc0_tx_loop_test: 1;
+ uint32_t slc0_rx_loop_test: 1;
+ uint32_t slc0_rx_auto_wrback: 1;
+ uint32_t slc0_rx_no_restart_clr: 1;
+ uint32_t slc0_rxdscr_burst_en: 1;
+ uint32_t slc0_rxdata_burst_en: 1;
+ uint32_t slc0_rxlink_auto_ret: 1;
+ uint32_t slc0_txlink_auto_ret: 1;
+ uint32_t slc0_txdscr_burst_en: 1;
+ uint32_t slc0_txdata_burst_en: 1;
+ uint32_t slc0_token_auto_clr: 1;
+ uint32_t slc0_token_sel: 1;
+ uint32_t slc1_tx_rst: 1;
+ uint32_t slc1_rx_rst: 1;
+ uint32_t slc0_wr_retry_mask_en: 1;
+ uint32_t slc1_wr_retry_mask_en: 1;
+ uint32_t slc1_tx_loop_test: 1;
+ uint32_t slc1_rx_loop_test: 1;
+ uint32_t slc1_rx_auto_wrback: 1;
+ uint32_t slc1_rx_no_restart_clr: 1;
+ uint32_t slc1_rxdscr_burst_en: 1;
+ uint32_t slc1_rxdata_burst_en: 1;
+ uint32_t slc1_rxlink_auto_ret: 1;
+ uint32_t slc1_txlink_auto_ret: 1;
+ uint32_t slc1_txdscr_burst_en: 1;
+ uint32_t slc1_txdata_burst_en: 1;
+ uint32_t slc1_token_auto_clr: 1;
+ uint32_t slc1_token_sel: 1;
+ };
+ uint32_t val;
+ } conf0;
+ union {
+ struct {
+ uint32_t frhost_bit0: 1;
+ uint32_t frhost_bit1: 1;
+ uint32_t frhost_bit2: 1;
+ uint32_t frhost_bit3: 1;
+ uint32_t frhost_bit4: 1;
+ uint32_t frhost_bit5: 1;
+ uint32_t frhost_bit6: 1;
+ uint32_t frhost_bit7: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t cmd_dtc: 1;
+ uint32_t rx_quick_eof: 1;
+ uint32_t reserved27: 5;
+ };
+ uint32_t val;
+ } slc0_int_raw;
+ union {
+ struct {
+ uint32_t frhost_bit0: 1;
+ uint32_t frhost_bit1: 1;
+ uint32_t frhost_bit2: 1;
+ uint32_t frhost_bit3: 1;
+ uint32_t frhost_bit4: 1;
+ uint32_t frhost_bit5: 1;
+ uint32_t frhost_bit6: 1;
+ uint32_t frhost_bit7: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t cmd_dtc: 1;
+ uint32_t rx_quick_eof: 1;
+ uint32_t reserved27: 5;
+ };
+ uint32_t val;
+ } slc0_int_st;
+ union {
+ struct {
+ uint32_t frhost_bit0: 1;
+ uint32_t frhost_bit1: 1;
+ uint32_t frhost_bit2: 1;
+ uint32_t frhost_bit3: 1;
+ uint32_t frhost_bit4: 1;
+ uint32_t frhost_bit5: 1;
+ uint32_t frhost_bit6: 1;
+ uint32_t frhost_bit7: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t cmd_dtc: 1;
+ uint32_t rx_quick_eof: 1;
+ uint32_t reserved27: 5;
+ };
+ uint32_t val;
+ } slc0_int_ena;
+ union {
+ struct {
+ uint32_t frhost_bit0: 1;
+ uint32_t frhost_bit1: 1;
+ uint32_t frhost_bit2: 1;
+ uint32_t frhost_bit3: 1;
+ uint32_t frhost_bit4: 1;
+ uint32_t frhost_bit5: 1;
+ uint32_t frhost_bit6: 1;
+ uint32_t frhost_bit7: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t cmd_dtc: 1;
+ uint32_t rx_quick_eof: 1;
+ uint32_t reserved27: 5;
+ };
+ uint32_t val;
+ } slc0_int_clr;
+ union {
+ struct {
+ uint32_t frhost_bit8: 1;
+ uint32_t frhost_bit9: 1;
+ uint32_t frhost_bit10: 1;
+ uint32_t frhost_bit11: 1;
+ uint32_t frhost_bit12: 1;
+ uint32_t frhost_bit13: 1;
+ uint32_t frhost_bit14: 1;
+ uint32_t frhost_bit15: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } slc1_int_raw;
+ union {
+ struct {
+ uint32_t frhost_bit8: 1;
+ uint32_t frhost_bit9: 1;
+ uint32_t frhost_bit10: 1;
+ uint32_t frhost_bit11: 1;
+ uint32_t frhost_bit12: 1;
+ uint32_t frhost_bit13: 1;
+ uint32_t frhost_bit14: 1;
+ uint32_t frhost_bit15: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } slc1_int_st;
+ union {
+ struct {
+ uint32_t frhost_bit8: 1;
+ uint32_t frhost_bit9: 1;
+ uint32_t frhost_bit10: 1;
+ uint32_t frhost_bit11: 1;
+ uint32_t frhost_bit12: 1;
+ uint32_t frhost_bit13: 1;
+ uint32_t frhost_bit14: 1;
+ uint32_t frhost_bit15: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } slc1_int_ena;
+ union {
+ struct {
+ uint32_t frhost_bit8: 1;
+ uint32_t frhost_bit9: 1;
+ uint32_t frhost_bit10: 1;
+ uint32_t frhost_bit11: 1;
+ uint32_t frhost_bit12: 1;
+ uint32_t frhost_bit13: 1;
+ uint32_t frhost_bit14: 1;
+ uint32_t frhost_bit15: 1;
+ uint32_t rx_start: 1;
+ uint32_t tx_start: 1;
+ uint32_t rx_udf: 1;
+ uint32_t tx_ovf: 1;
+ uint32_t token0_1to0: 1;
+ uint32_t token1_1to0: 1;
+ uint32_t tx_done: 1;
+ uint32_t tx_suc_eof: 1;
+ uint32_t rx_done: 1;
+ uint32_t rx_eof: 1;
+ uint32_t tohost: 1;
+ uint32_t tx_dscr_err: 1;
+ uint32_t rx_dscr_err: 1;
+ uint32_t tx_dscr_empty: 1;
+ uint32_t host_rd_ack: 1;
+ uint32_t wr_retry_done: 1;
+ uint32_t tx_err_eof: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } slc1_int_clr;
+ union {
+ struct {
+ uint32_t slc0_rx_full: 1;
+ uint32_t slc0_rx_empty: 1;
+ uint32_t reserved2: 14;
+ uint32_t slc1_rx_full: 1;
+ uint32_t slc1_rx_empty: 1;
+ uint32_t reserved18:14;
+ };
+ uint32_t val;
+ } rx_status;
+ union {
+ struct {
+ uint32_t rxfifo_wdata: 9;
+ uint32_t reserved9: 7;
+ uint32_t rxfifo_push: 1;
+ uint32_t reserved17: 15;
+ };
+ uint32_t val;
+ } slc0_rxfifo_push;
+ union {
+ struct {
+ uint32_t rxfifo_wdata: 9;
+ uint32_t reserved9: 7;
+ uint32_t rxfifo_push: 1;
+ uint32_t reserved17: 15;
+ };
+ uint32_t val;
+ } slc1_rxfifo_push;
+ union {
+ struct {
+ uint32_t slc0_tx_full: 1;
+ uint32_t slc0_tx_empty: 1;
+ uint32_t reserved2: 14;
+ uint32_t slc1_tx_full: 1;
+ uint32_t slc1_tx_empty: 1;
+ uint32_t reserved18:14;
+ };
+ uint32_t val;
+ } tx_status;
+ union {
+ struct {
+ uint32_t txfifo_rdata: 11;
+ uint32_t reserved11: 5;
+ uint32_t txfifo_pop: 1;
+ uint32_t reserved17: 15;
+ };
+ uint32_t val;
+ } slc0_txfifo_pop;
+ union {
+ struct {
+ uint32_t txfifo_rdata: 11;
+ uint32_t reserved11: 5;
+ uint32_t txfifo_pop: 1;
+ uint32_t reserved17: 15;
+ };
+ uint32_t val;
+ } slc1_txfifo_pop;
+ union {
+ struct {
+ uint32_t addr: 20;
+ uint32_t reserved20: 8;
+ uint32_t stop: 1;
+ uint32_t start: 1;
+ uint32_t restart: 1;
+ uint32_t park: 1;
+ };
+ uint32_t val;
+ } slc0_rx_link;
+ union {
+ struct {
+ uint32_t addr: 20;
+ uint32_t reserved20: 8;
+ uint32_t stop: 1;
+ uint32_t start: 1;
+ uint32_t restart: 1;
+ uint32_t park: 1;
+ };
+ uint32_t val;
+ } slc0_tx_link;
+ union {
+ struct {
+ uint32_t addr: 20;
+ uint32_t bt_packet: 1;
+ uint32_t reserved21: 7;
+ uint32_t stop: 1;
+ uint32_t start: 1;
+ uint32_t restart: 1;
+ uint32_t park: 1;
+ };
+ uint32_t val;
+ } slc1_rx_link;
+ union {
+ struct {
+ uint32_t addr: 20;
+ uint32_t reserved20: 8;
+ uint32_t stop: 1;
+ uint32_t start: 1;
+ uint32_t restart: 1;
+ uint32_t park: 1;
+ };
+ uint32_t val;
+ } slc1_tx_link;
+ union {
+ struct {
+ uint32_t slc0_intvec: 8;
+ uint32_t reserved8: 8;
+ uint32_t slc1_intvec: 8;
+ uint32_t reserved24: 8;
+ };
+ uint32_t val;
+ } intvec_tohost;
+ union {
+ struct {
+ uint32_t wdata: 12;
+ uint32_t wr: 1;
+ uint32_t inc: 1;
+ uint32_t inc_more: 1;
+ uint32_t reserved15: 1;
+ uint32_t token0: 12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } slc0_token0;
+ union {
+ struct {
+ uint32_t wdata: 12;
+ uint32_t wr: 1;
+ uint32_t inc: 1;
+ uint32_t inc_more: 1;
+ uint32_t reserved15: 1;
+ uint32_t token1: 12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } slc0_token1;
+ union {
+ struct {
+ uint32_t wdata: 12;
+ uint32_t wr: 1;
+ uint32_t inc: 1;
+ uint32_t inc_more: 1;
+ uint32_t reserved15: 1;
+ uint32_t token0: 12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } slc1_token0;
+ union {
+ struct {
+ uint32_t wdata: 12;
+ uint32_t wr: 1;
+ uint32_t inc: 1;
+ uint32_t inc_more: 1;
+ uint32_t reserved15: 1;
+ uint32_t token1: 12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } slc1_token1;
+ union {
+ struct {
+ uint32_t slc0_check_owner: 1;
+ uint32_t slc0_tx_check_sum_en: 1;
+ uint32_t slc0_rx_check_sum_en: 1;
+ uint32_t cmd_hold_en: 1;
+ uint32_t slc0_len_auto_clr: 1;
+ uint32_t slc0_tx_stitch_en: 1;
+ uint32_t slc0_rx_stitch_en: 1;
+ uint32_t reserved7: 9;
+ uint32_t slc1_check_owner: 1;
+ uint32_t slc1_tx_check_sum_en: 1;
+ uint32_t slc1_rx_check_sum_en: 1;
+ uint32_t host_int_level_sel: 1;
+ uint32_t slc1_tx_stitch_en: 1;
+ uint32_t slc1_rx_stitch_en: 1;
+ uint32_t clk_en: 1;
+ uint32_t reserved23: 9;
+ };
+ uint32_t val;
+ } conf1;
+ uint32_t slc0_state0; /**/
+ uint32_t slc0_state1; /**/
+ uint32_t slc1_state0; /**/
+ uint32_t slc1_state1; /**/
+ union {
+ struct {
+ uint32_t txeof_ena: 6;
+ uint32_t reserved6: 2;
+ uint32_t fifo_map_ena: 4;
+ uint32_t slc0_tx_dummy_mode: 1;
+ uint32_t hda_map_128k: 1;
+ uint32_t slc1_tx_dummy_mode: 1;
+ uint32_t reserved15: 1;
+ uint32_t tx_push_idle_num:16;
+ };
+ uint32_t val;
+ } bridge_conf;
+ uint32_t slc0_to_eof_des_addr; /**/
+ uint32_t slc0_tx_eof_des_addr; /**/
+ uint32_t slc0_to_eof_bfr_des_addr; /**/
+ uint32_t slc1_to_eof_des_addr; /**/
+ uint32_t slc1_tx_eof_des_addr; /**/
+ uint32_t slc1_to_eof_bfr_des_addr; /**/
+ union {
+ struct {
+ uint32_t mode: 3;
+ uint32_t reserved3: 1;
+ uint32_t addr: 2;
+ uint32_t reserved6: 26;
+ };
+ uint32_t val;
+ } ahb_test;
+ union {
+ struct {
+ uint32_t cmd_st: 3;
+ uint32_t reserved3: 1;
+ uint32_t func_st: 4;
+ uint32_t sdio_wakeup: 1;
+ uint32_t reserved9: 3;
+ uint32_t bus_st: 3;
+ uint32_t reserved15: 1;
+ uint32_t func1_acc_state: 5;
+ uint32_t reserved21: 3;
+ uint32_t func2_acc_state: 5;
+ uint32_t reserved29: 3;
+ };
+ uint32_t val;
+ } sdio_st;
+ union {
+ struct {
+ uint32_t slc0_token_no_replace: 1;
+ uint32_t slc0_infor_no_replace: 1;
+ uint32_t slc0_rx_fill_mode: 1;
+ uint32_t slc0_rx_eof_mode: 1;
+ uint32_t slc0_rx_fill_en: 1;
+ uint32_t slc0_rd_retry_threshold:11;
+ uint32_t slc1_token_no_replace: 1;
+ uint32_t slc1_infor_no_replace: 1;
+ uint32_t slc1_rx_fill_mode: 1;
+ uint32_t slc1_rx_eof_mode: 1;
+ uint32_t slc1_rx_fill_en: 1;
+ uint32_t slc1_rd_retry_threshold:11;
+ };
+ uint32_t val;
+ } rx_dscr_conf;
+ uint32_t slc0_txlink_dscr; /**/
+ uint32_t slc0_txlink_dscr_bf0; /**/
+ uint32_t slc0_txlink_dscr_bf1; /**/
+ uint32_t slc0_rxlink_dscr; /**/
+ uint32_t slc0_rxlink_dscr_bf0; /**/
+ uint32_t slc0_rxlink_dscr_bf1; /**/
+ uint32_t slc1_txlink_dscr; /**/
+ uint32_t slc1_txlink_dscr_bf0; /**/
+ uint32_t slc1_txlink_dscr_bf1; /**/
+ uint32_t slc1_rxlink_dscr; /**/
+ uint32_t slc1_rxlink_dscr_bf0; /**/
+ uint32_t slc1_rxlink_dscr_bf1; /**/
+ uint32_t slc0_tx_erreof_des_addr; /**/
+ uint32_t slc1_tx_erreof_des_addr; /**/
+ union {
+ struct {
+ uint32_t slc0_token:12;
+ uint32_t reserved12: 4;
+ uint32_t slc1_token:12;
+ uint32_t reserved28: 4;
+ };
+ uint32_t val;
+ } token_lat;
+ union {
+ struct {
+ uint32_t wr_retry_threshold:11;
+ uint32_t reserved11: 21;
+ };
+ uint32_t val;
+ } tx_dscr_conf;
+ uint32_t cmd_infor0; /**/
+ uint32_t cmd_infor1; /**/
+ union {
+ struct {
+ uint32_t len_wdata: 20;
+ uint32_t len_wr: 1;
+ uint32_t len_inc: 1;
+ uint32_t len_inc_more: 1;
+ uint32_t rx_packet_load_en: 1;
+ uint32_t tx_packet_load_en: 1;
+ uint32_t rx_get_used_dscr: 1;
+ uint32_t tx_get_used_dscr: 1;
+ uint32_t rx_new_pkt_ind: 1;
+ uint32_t tx_new_pkt_ind: 1;
+ uint32_t reserved29: 3;
+ };
+ uint32_t val;
+ } slc0_len_conf;
+ union {
+ struct {
+ uint32_t len: 20;
+ uint32_t reserved20:12;
+ };
+ uint32_t val;
+ } slc0_length;
+ uint32_t slc0_txpkt_h_dscr; /**/
+ uint32_t slc0_txpkt_e_dscr; /**/
+ uint32_t slc0_rxpkt_h_dscr; /**/
+ uint32_t slc0_rxpkt_e_dscr; /**/
+ uint32_t slc0_txpktu_h_dscr; /**/
+ uint32_t slc0_txpktu_e_dscr; /**/
+ uint32_t slc0_rxpktu_h_dscr; /**/
+ uint32_t slc0_rxpktu_e_dscr; /**/
+ uint32_t reserved_10c;
+ uint32_t reserved_110;
+ union {
+ struct {
+ uint32_t slc0_position: 8;
+ uint32_t slc1_position: 8;
+ uint32_t reserved16: 16;
+ };
+ uint32_t val;
+ } seq_position;
+ union {
+ struct {
+ uint32_t rx_dscr_rec_lim: 10;
+ uint32_t reserved10: 22;
+ };
+ uint32_t val;
+ } slc0_dscr_rec_conf;
+ union {
+ struct {
+ uint32_t dat0_crc_err_cnt: 8;
+ uint32_t dat1_crc_err_cnt: 8;
+ uint32_t dat2_crc_err_cnt: 8;
+ uint32_t dat3_crc_err_cnt: 8;
+ };
+ uint32_t val;
+ } sdio_crc_st0;
+ union {
+ struct {
+ uint32_t cmd_crc_err_cnt: 8;
+ uint32_t reserved8: 23;
+ uint32_t err_cnt_clr: 1;
+ };
+ uint32_t val;
+ } sdio_crc_st1;
+ uint32_t slc0_eof_start_des; /**/
+ uint32_t slc0_push_dscr_addr; /**/
+ uint32_t slc0_done_dscr_addr; /**/
+ uint32_t slc0_sub_start_des; /**/
+ union {
+ struct {
+ uint32_t rx_dscr_cnt_lat: 10;
+ uint32_t reserved10: 6;
+ uint32_t rx_get_eof_occ: 1;
+ uint32_t reserved17: 15;
+ };
+ uint32_t val;
+ } slc0_dscr_cnt;
+ union {
+ struct {
+ uint32_t len_lim: 20;
+ uint32_t reserved20:12;
+ };
+ uint32_t val;
+ } slc0_len_lim_conf;
+ union {
+ struct {
+ uint32_t frhost_bit01: 1;
+ uint32_t frhost_bit11: 1;
+ uint32_t frhost_bit21: 1;
+ uint32_t frhost_bit31: 1;
+ uint32_t frhost_bit41: 1;
+ uint32_t frhost_bit51: 1;
+ uint32_t frhost_bit61: 1;
+ uint32_t frhost_bit71: 1;
+ uint32_t rx_start1: 1;
+ uint32_t tx_start1: 1;
+ uint32_t rx_udf1: 1;
+ uint32_t tx_ovf1: 1;
+ uint32_t token0_1to01: 1;
+ uint32_t token1_1to01: 1;
+ uint32_t tx_done1: 1;
+ uint32_t tx_suc_eof1: 1;
+ uint32_t rx_done1: 1;
+ uint32_t rx_eof1: 1;
+ uint32_t tohost1: 1;
+ uint32_t tx_dscr_err1: 1;
+ uint32_t rx_dscr_err1: 1;
+ uint32_t tx_dscr_empty1: 1;
+ uint32_t host_rd_ack1: 1;
+ uint32_t wr_retry_done1: 1;
+ uint32_t tx_err_eof1: 1;
+ uint32_t cmd_dtc1: 1;
+ uint32_t rx_quick_eof1: 1;
+ uint32_t reserved27: 5;
+ };
+ uint32_t val;
+ } slc0_int_st1;
+ union {
+ struct {
+ uint32_t frhost_bit01: 1;
+ uint32_t frhost_bit11: 1;
+ uint32_t frhost_bit21: 1;
+ uint32_t frhost_bit31: 1;
+ uint32_t frhost_bit41: 1;
+ uint32_t frhost_bit51: 1;
+ uint32_t frhost_bit61: 1;
+ uint32_t frhost_bit71: 1;
+ uint32_t rx_start1: 1;
+ uint32_t tx_start1: 1;
+ uint32_t rx_udf1: 1;
+ uint32_t tx_ovf1: 1;
+ uint32_t token0_1to01: 1;
+ uint32_t token1_1to01: 1;
+ uint32_t tx_done1: 1;
+ uint32_t tx_suc_eof1: 1;
+ uint32_t rx_done1: 1;
+ uint32_t rx_eof1: 1;
+ uint32_t tohost1: 1;
+ uint32_t tx_dscr_err1: 1;
+ uint32_t rx_dscr_err1: 1;
+ uint32_t tx_dscr_empty1: 1;
+ uint32_t host_rd_ack1: 1;
+ uint32_t wr_retry_done1: 1;
+ uint32_t tx_err_eof1: 1;
+ uint32_t cmd_dtc1: 1;
+ uint32_t rx_quick_eof1: 1;
+ uint32_t reserved27: 5;
+ };
+ uint32_t val;
+ } slc0_int_ena1;
+ union {
+ struct {
+ uint32_t frhost_bit81: 1;
+ uint32_t frhost_bit91: 1;
+ uint32_t frhost_bit101: 1;
+ uint32_t frhost_bit111: 1;
+ uint32_t frhost_bit121: 1;
+ uint32_t frhost_bit131: 1;
+ uint32_t frhost_bit141: 1;
+ uint32_t frhost_bit151: 1;
+ uint32_t rx_start1: 1;
+ uint32_t tx_start1: 1;
+ uint32_t rx_udf1: 1;
+ uint32_t tx_ovf1: 1;
+ uint32_t token0_1to01: 1;
+ uint32_t token1_1to01: 1;
+ uint32_t tx_done1: 1;
+ uint32_t tx_suc_eof1: 1;
+ uint32_t rx_done1: 1;
+ uint32_t rx_eof1: 1;
+ uint32_t tohost1: 1;
+ uint32_t tx_dscr_err1: 1;
+ uint32_t rx_dscr_err1: 1;
+ uint32_t tx_dscr_empty1: 1;
+ uint32_t host_rd_ack1: 1;
+ uint32_t wr_retry_done1: 1;
+ uint32_t tx_err_eof1: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } slc1_int_st1;
+ union {
+ struct {
+ uint32_t frhost_bit81: 1;
+ uint32_t frhost_bit91: 1;
+ uint32_t frhost_bit101: 1;
+ uint32_t frhost_bit111: 1;
+ uint32_t frhost_bit121: 1;
+ uint32_t frhost_bit131: 1;
+ uint32_t frhost_bit141: 1;
+ uint32_t frhost_bit151: 1;
+ uint32_t rx_start1: 1;
+ uint32_t tx_start1: 1;
+ uint32_t rx_udf1: 1;
+ uint32_t tx_ovf1: 1;
+ uint32_t token0_1to01: 1;
+ uint32_t token1_1to01: 1;
+ uint32_t tx_done1: 1;
+ uint32_t tx_suc_eof1: 1;
+ uint32_t rx_done1: 1;
+ uint32_t rx_eof1: 1;
+ uint32_t tohost1: 1;
+ uint32_t tx_dscr_err1: 1;
+ uint32_t rx_dscr_err1: 1;
+ uint32_t tx_dscr_empty1: 1;
+ uint32_t host_rd_ack1: 1;
+ uint32_t wr_retry_done1: 1;
+ uint32_t tx_err_eof1: 1;
+ uint32_t reserved25: 7;
+ };
+ uint32_t val;
+ } slc1_int_ena1;
+ uint32_t reserved_14c;
+ uint32_t reserved_150;
+ uint32_t reserved_154;
+ uint32_t reserved_158;
+ uint32_t reserved_15c;
+ uint32_t reserved_160;
+ uint32_t reserved_164;
+ uint32_t reserved_168;
+ uint32_t reserved_16c;
+ uint32_t reserved_170;
+ uint32_t reserved_174;
+ uint32_t reserved_178;
+ uint32_t reserved_17c;
+ uint32_t reserved_180;
+ uint32_t reserved_184;
+ uint32_t reserved_188;
+ uint32_t reserved_18c;
+ uint32_t reserved_190;
+ uint32_t reserved_194;
+ uint32_t reserved_198;
+ uint32_t reserved_19c;
+ uint32_t reserved_1a0;
+ uint32_t reserved_1a4;
+ uint32_t reserved_1a8;
+ uint32_t reserved_1ac;
+ uint32_t reserved_1b0;
+ uint32_t reserved_1b4;
+ uint32_t reserved_1b8;
+ uint32_t reserved_1bc;
+ uint32_t reserved_1c0;
+ uint32_t reserved_1c4;
+ uint32_t reserved_1c8;
+ uint32_t reserved_1cc;
+ uint32_t reserved_1d0;
+ uint32_t reserved_1d4;
+ uint32_t reserved_1d8;
+ uint32_t reserved_1dc;
+ uint32_t reserved_1e0;
+ uint32_t reserved_1e4;
+ uint32_t reserved_1e8;
+ uint32_t reserved_1ec;
+ uint32_t reserved_1f0;
+ uint32_t reserved_1f4;
+ uint32_t date; /**/
+ uint32_t id; /**/
+} slc_dev_t;
+extern slc_dev_t SLC;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_SLC_STRUCT_H_ */
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