[AArch64] Add test case to show missed opportunity to remove a shift before tbnz...

This pattern showed up in D60358 and it was suggested I had a test and fix that separately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358030 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/AArch64/tbz-tbnz.ll b/test/CodeGen/AArch64/tbz-tbnz.ll
index 8dc943b79624fb86253e7f08097c4f1b6f573921..fa792509d4e72e55de051fa11aa707c2b38962fb 100644 (file)
--- a/test/CodeGen/AArch64/tbz-tbnz.ll
+++ b/test/CodeGen/AArch64/tbz-tbnz.ll
@@ -359,3 +359,24 @@ then:
 end:
   ret void
 }
+
+define void @test20(i32 %in) {
+; CHECK-LABEL: @test20
+  %shl = shl i32 %in, 3
+  %zext = zext i32 %shl to i64
+  %and = and i64 %zext, 32
+  %cond = icmp eq i64 %and, 0
+  br i1 %cond, label %then, label %end
+
+; FIXME: Should be no lsl
+; CHECK: lsl w8, w0, #3
+; CHECK: tbnz w8, #5
+
+then:
+  call void @t()
+  br label %end
+
+end:
+  ret void
+}
+