return __builtin_ia32_minss((__v4sf)__a, (__v4sf)__b);
}
-/// \brief Compares two 128-bit vectors of [4 x float] and returns the
-/// lesser of each pair of values.
+/// \brief Compares two 128-bit vectors of [4 x float] and returns the lesser
+/// of each pair of values.
///
/// \headerfile <x86intrin.h>
///
}
/// \brief Compares two 32-bit float values in the low-order bits of both
-/// operands and returns the greater value in the low-order bits of
-/// a vector [4 x float].
+/// operands and returns the greater value in the low-order bits of a 128-bit
+/// vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNEQSS / CMPNEQSS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNEQSS / CMPNEQSS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNEQPS / CMPNEQPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNEQPS / CMPNEQPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLTSS / CMPNLTSS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLTSS / CMPNLTSS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLTPS / CMPNLTPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLTPS / CMPNLTPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLESS / CMPNLESS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLESS / CMPNLESS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLEPS / CMPNLEPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLEPS / CMPNLEPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLTSS / CMPNLTSS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLTSS / CMPNLTSS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLTPS / CMPNLTPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLTPS / CMPNLTPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLESS / CMPNLESS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLESS / CMPNLESS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPNLEPS / CMPNLEPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPNLEPS / CMPNLEPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPORDSS / CMPORDSS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPORDSS / CMPORDSS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPORDPS / CMPORDPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPORDPS / CMPORDPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPUNORDSS / CMPUNORDSS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPUNORDSS / CMPUNORDSS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float] containing one of the operands. The lower
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCMPUNORDPS / CMPUNORDPS </c> instructions.
+/// This intrinsic corresponds to the <c> VCMPUNORDPS / CMPUNORDPS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> instructions.
+/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c> instructions.
+/// This intrinsic corresponds to the <c> VCOMISS / COMISS </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
}
/// \brief Performs an unordered comparison of two 32-bit float values using
-/// the low-order bits of both operands to determine if the first operand
-/// is less than or equal to the second operand and returns the result of
-/// the comparison.
+/// the low-order bits of both operands to determine if the first operand is
+/// less than or equal to the second operand and returns the result of the
+/// comparison.
///
/// \headerfile <x86intrin.h>
///
}
/// \brief Performs an unordered comparison of two 32-bit float values using
-/// the low-order bits of both operands to determine if the first operand
-/// is greater than the second operand and returns the result of the
+/// the low-order bits of both operands to determine if the first operand is
+/// greater than the second operand and returns the result of the
/// comparison.
///
/// \headerfile <x86intrin.h>
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c> instructions.
+/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c> instructions.
+/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c> instructions.
+/// This intrinsic corresponds to the <c> VCVTSS2SI / CVTSS2SI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c> instructions.
+/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c> instructions.
+/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c> instructions.
+/// This intrinsic corresponds to the <c> VCVTTSS2SI / CVTTSS2SI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float]. The lower 32 bits of this operand are
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTTPS2PI / VTTPS2PI </c> instructions.
+/// This intrinsic corresponds to the <c> CVTTPS2PI / VTTPS2PI </c>
+/// instructions.
///
/// \param __a
/// A 128-bit vector of [4 x float].
///
/// \param __p
/// A pointer to a float value to be loaded and duplicated.
-/// \returns A 128-bit vector of [4 x float] containing the loaded
-/// and duplicated values.
+/// \returns A 128-bit vector of [4 x float] containing the loaded and
+/// duplicated values.
static __inline__ __m128 __DEFAULT_FN_ATTRS
_mm_load1_ps(const float *__p)
{
/// \param a
/// A pointer to a memory location containing a cache line of data.
/// \param sel
-/// A predefined integer constant specifying the type of prefetch operation:
-/// _MM_HINT_NTA: Move data using the non-temporal access (NTA) hint.
-/// The PREFETCHNTA instruction will be generated.
+/// A predefined integer constant specifying the type of prefetch
+/// operation: \n
+/// _MM_HINT_NTA: Move data using the non-temporal access (NTA) hint. The
+/// PREFETCHNTA instruction will be generated. \n
/// _MM_HINT_T0: Move data using the T0 hint. The PREFETCHT0 instruction will
-/// be generated.
+/// be generated. \n
/// _MM_HINT_T1: Move data using the T1 hint. The PREFETCHT1 instruction will
-/// be generated.
+/// be generated. \n
/// _MM_HINT_T2: Move data using the T2 hint. The PREFETCHT2 instruction will
-/// be generated.
+/// be generated.
#define _mm_prefetch(a, sel) (__builtin_prefetch((void *)(a), 0, (sel)))
#endif
/// \param a
/// A 64-bit vector of [4 x i16].
/// \param n
-/// An immediate integer operand that determines which bits are extracted:
-/// 0: Bits [15:0] are copied to the destination.
-/// 1: Bits [31:16] are copied to the destination.
-/// 2: Bits [47:32] are copied to the destination.
+/// An immediate integer operand that determines which bits are extracted: \n
+/// 0: Bits [15:0] are copied to the destination. \n
+/// 1: Bits [31:16] are copied to the destination. \n
+/// 2: Bits [47:32] are copied to the destination. \n
/// 3: Bits [63:48] are copied to the destination.
/// \returns A 16-bit integer containing the extracted 16 bits of packed data.
#define _mm_extract_pi16(a, n) __extension__ ({ \
/// destination at the offset specified by operand \a n.
/// \param n
/// An immediate integer operant that determines which the bits to be used
-/// in the destination.
-/// 0: Bits [15:0] are copied to the destination.
-/// 1: Bits [31:16] are copied to the destination.
-/// 2: Bits [47:32] are copied to the destination.
-/// 3: Bits [63:48] are copied to the destination.
+/// in the destination. \n
+/// 0: Bits [15:0] are copied to the destination. \n
+/// 1: Bits [31:16] are copied to the destination. \n
+/// 2: Bits [47:32] are copied to the destination. \n
+/// 3: Bits [63:48] are copied to the destination. \n
/// The remaining bits in the destination are copied from the corresponding
/// bits in operand \a a.
/// \returns A 64-bit integer vector containing the copied packed data from the
/// \param n
/// An immediate value containing an 8-bit value specifying which elements to
/// copy from \a a. The destinations within the 64-bit destination are
-/// assigned values as follows:
-/// Bits [1:0] are used to assign values to bits [15:0] in the destination.
-/// Bits [3:2] are used to assign values to bits [31:16] in the destination.
-/// Bits [5:4] are used to assign values to bits [47:32] in the destination.
-/// Bits [7:6] are used to assign values to bits [63:48] in the destination.
-/// Bit value assignments:
-/// 00: assigned from bits [15:0] of \a a.
-/// 01: assigned from bits [31:16] of \a a.
-/// 10: assigned from bits [47:32] of \a a.
+/// assigned values as follows: \n
+/// Bits [1:0] are used to assign values to bits [15:0] in the
+/// destination. \n
+/// Bits [3:2] are used to assign values to bits [31:16] in the
+/// destination. \n
+/// Bits [5:4] are used to assign values to bits [47:32] in the
+/// destination. \n
+/// Bits [7:6] are used to assign values to bits [63:48] in the
+/// destination. \n
+/// Bit value assignments: \n
+/// 00: assigned from bits [15:0] of \a a. \n
+/// 01: assigned from bits [31:16] of \a a. \n
+/// 10: assigned from bits [47:32] of \a a. \n
/// 11: assigned from bits [63:48] of \a a.
/// \returns A 64-bit integer vector containing the shuffled values.
#define _mm_shuffle_pi16(a, n) __extension__ ({ \
#endif
/// \brief Returns the contents of the MXCSR register as a 32-bit unsigned
-/// integer value. There are several groups of macros associated with this
+/// integer value.
+///
+/// There are several groups of macros associated with this
/// intrinsic, including:
-/// * For checking exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO,
+/// <ul>
+/// <li>
+/// For checking exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO,
/// _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW,
/// _MM_EXCEPT_INEXACT. There is a convenience wrapper
/// _MM_GET_EXCEPTION_STATE().
-/// * For checking exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW,
+/// </li>
+/// <li>
+/// For checking exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW,
/// _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_INEXACT.
/// There is a convenience wrapper _MM_GET_EXCEPTION_MASK().
-/// * For checking rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN,
+/// </li>
+/// <li>
+/// For checking rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN,
/// _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO. There is a convenience wrapper
/// _MM_GET_ROUNDING_MODE(x) where x is one of these macros.
-/// * For checking flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF.
+/// </li>
+/// <li>
+/// For checking flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF.
/// There is a convenience wrapper _MM_GET_FLUSH_ZERO_MODE().
-/// * For checking denormals-are-zero mode: _MM_DENORMALS_ZERO_ON,
+/// </li>
+/// <li>
+/// For checking denormals-are-zero mode: _MM_DENORMALS_ZERO_ON,
/// _MM_DENORMALS_ZERO_OFF. There is a convenience wrapper
/// _MM_GET_DENORMALS_ZERO_MODE().
+/// </li>
+/// </ul>
///
/// For example, the expression below checks if an overflow exception has
/// occurred:
/// register.
unsigned int _mm_getcsr(void);
-/// \brief Sets the MXCSR register with the 32-bit unsigned integer value. There
-/// are several groups of macros associated with this intrinsic, including:
-/// * For setting exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO,
+/// \brief Sets the MXCSR register with the 32-bit unsigned integer value.
+///
+/// There are several groups of macros associated with this intrinsic,
+/// including:
+/// <ul>
+/// <li>
+/// For setting exception states: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO,
/// _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW,
/// _MM_EXCEPT_INEXACT. There is a convenience wrapper
/// _MM_SET_EXCEPTION_STATE(x) where x is one of these macros.
-/// * For setting exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW,
+/// </li>
+/// <li>
+/// For setting exception masks: _MM_MASK_UNDERFLOW, _MM_MASK_OVERFLOW,
/// _MM_MASK_INVALID, _MM_MASK_DENORM, _MM_MASK_DIV_ZERO, _MM_MASK_INEXACT.
/// There is a convenience wrapper _MM_SET_EXCEPTION_MASK(x) where x is one
/// of these macros.
-/// * For setting rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN,
+/// </li>
+/// <li>
+/// For setting rounding modes: _MM_ROUND_NEAREST, _MM_ROUND_DOWN,
/// _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO. There is a convenience wrapper
/// _MM_SET_ROUNDING_MODE(x) where x is one of these macros.
-/// * For setting flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF.
+/// </li>
+/// <li>
+/// For setting flush-to-zero mode: _MM_FLUSH_ZERO_ON, _MM_FLUSH_ZERO_OFF.
/// There is a convenience wrapper _MM_SET_FLUSH_ZERO_MODE(x) where x is
/// one of these macros.
-/// * For setting denormals-are-zero mode: _MM_DENORMALS_ZERO_ON,
+/// </li>
+/// <li>
+/// For setting denormals-are-zero mode: _MM_DENORMALS_ZERO_ON,
/// _MM_DENORMALS_ZERO_OFF. There is a convenience wrapper
/// _MM_SET_DENORMALS_ZERO_MODE(x) where x is one of these macros.
+/// </li>
+/// </ul>
///
/// For example, the following expression causes subsequent floating-point
/// operations to round up:
/// A 128-bit vector of [4 x float].
/// \param mask
/// An immediate value containing an 8-bit value specifying which elements to
-/// copy from \ a and \a b.
-/// Bits [3:0] specify the values copied from operand \a a.
-/// Bits [7:4] specify the values copied from operand \a b. The destinations
-/// within the 128-bit destination are assigned values as follows:
-/// Bits [1:0] are used to assign values to bits [31:0] in the destination.
-/// Bits [3:2] are used to assign values to bits [63:32] in the destination.
-/// Bits [5:4] are used to assign values to bits [95:64] in the destination.
-/// Bits [7:6] are used to assign values to bits [127:96] in the destination.
-/// Bit value assignments:
-/// 00: Bits [31:0] copied from the specified operand.
-/// 01: Bits [63:32] copied from the specified operand.
-/// 10: Bits [95:64] copied from the specified operand.
+/// copy from \ a and \a b. \n
+/// Bits [3:0] specify the values copied from operand \a a. \n
+/// Bits [7:4] specify the values copied from operand \a b. \n
+/// The destinations within the 128-bit destination are assigned values as
+/// follows: \n
+/// Bits [1:0] are used to assign values to bits [31:0] in the
+/// destination. \n
+/// Bits [3:2] are used to assign values to bits [63:32] in the
+/// destination. \n
+/// Bits [5:4] are used to assign values to bits [95:64] in the
+/// destination. \n
+/// Bits [7:6] are used to assign values to bits [127:96] in the
+/// destination. \n
+/// Bit value assignments: \n
+/// 00: Bits [31:0] copied from the specified operand. \n
+/// 01: Bits [63:32] copied from the specified operand. \n
+/// 10: Bits [95:64] copied from the specified operand. \n
/// 11: Bits [127:96] copied from the specified operand.
/// \returns A 128-bit vector of [4 x float] containing the shuffled values.
#define _mm_shuffle_ps(a, b, mask) __extension__ ({ \
4 + (((mask) >> 6) & 0x3)); })
/// \brief Unpacks the high-order (index 2,3) values from two 128-bit vectors of
-/// [4 x float] and interleaves them into a 128-bit vector of [4 x
-/// float].
+/// [4 x float] and interleaves them into a 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
/// This intrinsic corresponds to the <c> VUNPCKHPS / UNPCKHPS </c> instruction.
///
/// \param __a
-/// A 128-bit vector of [4 x float].
-/// Bits [95:64] are written to bits [31:0] of the destination.
+/// A 128-bit vector of [4 x float]. \n
+/// Bits [95:64] are written to bits [31:0] of the destination. \n
/// Bits [127:96] are written to bits [95:64] of the destination.
/// \param __b
/// A 128-bit vector of [4 x float].
-/// Bits [95:64] are written to bits [63:32] of the destination.
+/// Bits [95:64] are written to bits [63:32] of the destination. \n
/// Bits [127:96] are written to bits [127:96] of the destination.
/// \returns A 128-bit vector of [4 x float] containing the interleaved values.
static __inline__ __m128 __DEFAULT_FN_ATTRS
}
/// \brief Unpacks the low-order (index 0,1) values from two 128-bit vectors of
-/// [4 x float] and interleaves them into a 128-bit vector of [4 x
-/// float].
+/// [4 x float] and interleaves them into a 128-bit vector of [4 x float].
///
/// \headerfile <x86intrin.h>
///
/// This intrinsic corresponds to the <c> VUNPCKLPS / UNPCKLPS </c> instruction.
///
/// \param __a
-/// A 128-bit vector of [4 x float].
-/// Bits [31:0] are written to bits [31:0] of the destination.
+/// A 128-bit vector of [4 x float]. \n
+/// Bits [31:0] are written to bits [31:0] of the destination. \n
/// Bits [63:32] are written to bits [95:64] of the destination.
/// \param __b
-/// A 128-bit vector of [4 x float].
-/// Bits [31:0] are written to bits [63:32] of the destination.
+/// A 128-bit vector of [4 x float]. \n
+/// Bits [31:0] are written to bits [63:32] of the destination. \n
/// Bits [63:32] are written to bits [127:96] of the destination.
/// \returns A 128-bit vector of [4 x float] containing the interleaved values.
static __inline__ __m128 __DEFAULT_FN_ATTRS
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// A 64-bit vector of [4 x i16]. The elements of the destination are copied
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// A 64-bit vector of 16-bit unsigned integer values. The elements of the
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// A 64-bit vector of [8 x i8]. The elements of the destination are copied
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// A 64-bit vector of unsigned 8-bit integer values. The elements of the
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPI2PS + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// A 64-bit vector of [2 x i32]. The lower elements of the destination are
/// packs the results into a 64-bit integer vector of [4 x i16]. If the
/// floating-point element is NaN or infinity, or if the floating-point
/// element is greater than 0x7FFFFFFF or less than -0x8000, it is converted
-/// to 0x8000. Otherwise if the floating-point element is greater
-/// than 0x7FFF, it is converted to 0x7FFF.
+/// to 0x8000. Otherwise if the floating-point element is greater than
+/// 0x7FFF, it is converted to 0x7FFF.
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPS2PI + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPS2PI + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// A 128-bit floating-point vector of [4 x float].
/// [8 x i8]. The upper 32 bits of the vector are set to 0. If the
/// floating-point element is NaN or infinity, or if the floating-point
/// element is greater than 0x7FFFFFFF or less than -0x80, it is converted
-/// to 0x80. Otherwise if the floating-point element is greater
-/// than 0x7F, it is converted to 0x7F.
+/// to 0x80. Otherwise if the floating-point element is greater than 0x7F,
+/// it is converted to 0x7F.
///
/// \headerfile <x86intrin.h>
///
-/// This intrinsic corresponds to the <c> CVTPS2PI + \c COMPOSITE </c> instruction.
+/// This intrinsic corresponds to the <c> CVTPS2PI + \c COMPOSITE </c>
+/// instruction.
///
/// \param __a
/// 128-bit floating-point vector of [4 x float].