rename clock enable and reset bits for SPI modules

    1.The names of clock enable and reset bits do not match with TRM, just rename them.

diff --git a/components/driver/periph_ctrl.c b/components/driver/periph_ctrl.c
index 67431a4276cdb55851a845a68da679e9f19798b1..59baf48311c25c04c8871f7a6c4fc7b683bf486e 100644 (file)
--- a/components/driver/periph_ctrl.c
+++ b/components/driver/periph_ctrl.c
@@ -91,11 +91,11 @@ static uint32_t get_clk_en_mask(periph_module_t periph)
         case PERIPH_PCNT_MODULE:
             return DPORT_PCNT_CLK_EN;
         case PERIPH_SPI_MODULE:
-            return DPORT_SPI_CLK_EN_1;
+            return DPORT_SPI01_CLK_EN;
         case PERIPH_HSPI_MODULE:
-            return DPORT_SPI_CLK_EN;
+            return DPORT_SPI2_CLK_EN;
         case PERIPH_VSPI_MODULE:
-            return DPORT_SPI_CLK_EN_2;
+            return DPORT_SPI3_CLK_EN;
         case PERIPH_SPI_DMA_MODULE:
             return DPORT_SPI_DMA_CLK_EN;
         case PERIPH_SDMMC_MODULE:
@@ -159,11 +159,11 @@ static uint32_t get_rst_en_mask(periph_module_t periph)
         case PERIPH_PCNT_MODULE:
             return DPORT_PCNT_RST;
         case PERIPH_SPI_MODULE:
-            return DPORT_SPI_RST_1;
+            return DPORT_SPI01_RST;
         case PERIPH_HSPI_MODULE:
-            return DPORT_SPI_RST;
+            return DPORT_SPI2_RST;
         case PERIPH_VSPI_MODULE:
-            return DPORT_SPI_RST_2;
+            return DPORT_SPI3_RST;
         case PERIPH_SPI_DMA_MODULE:
             return DPORT_SPI_DMA_RST;
         case PERIPH_SDMMC_MODULE:

diff --git a/components/esp32/clk.c b/components/esp32/clk.c
index ec8d73c9bbdab60f2670444df8b27815e70c85b8..64fe3af4a1a929826726696987effef851ce66ac 100644 (file)
--- a/components/esp32/clk.c
+++ b/components/esp32/clk.c
@@ -221,7 +221,7 @@ void esp_perip_clk_init(void)
 #if CONFIG_CONSOLE_UART_NUM != 2
                               DPORT_UART2_CLK_EN |
 #endif
-                              DPORT_SPI_CLK_EN |
+                              DPORT_SPI2_CLK_EN |
                               DPORT_I2C_EXT0_CLK_EN |
                               DPORT_UHCI0_CLK_EN |
                               DPORT_RMT_CLK_EN |
@@ -229,7 +229,7 @@ void esp_perip_clk_init(void)
                               DPORT_LEDC_CLK_EN |
                               DPORT_UHCI1_CLK_EN |
                               DPORT_TIMERGROUP1_CLK_EN |
-                              DPORT_SPI_CLK_EN_2 |
+                              DPORT_SPI3_CLK_EN |
                               DPORT_PWM0_CLK_EN |
                               DPORT_I2C_EXT1_CLK_EN |
                               DPORT_CAN_CLK_EN |
@@ -253,11 +253,11 @@ void esp_perip_clk_init(void)
 
 
 #if CONFIG_SPIRAM_SPEED_80M
-//80MHz SPIRAM uses SPI2 as well; it's initialized before this is called. Because it is used in
+//80MHz SPIRAM uses SPI3 as well; it's initialized before this is called. Because it is used in
 //a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
 //in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
 //not modify that state, regardless of what we calculated earlier.
-    common_perip_clk &= ~DPORT_SPI_CLK_EN_2;
+    common_perip_clk &= ~DPORT_SPI3_CLK_EN;
 #endif
 
     /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,

diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c
index 279de8d2f71e53bac842dd981db144f131c7fb6e..50a8571d84e91e2b4e89a1fb12404ac18827975b 100644 (file)
--- a/components/esp32/spiram_psram.c
+++ b/components/esp32/spiram_psram.c
@@ -543,7 +543,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
             while (1) {
                 spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_3));
                 if (spi_status != 0 && spi_status != 1) {
-                    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
+                    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
                     break;
                 }
             }

diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c
index 9b242c789f3a44dd39f4aec845568ffa419bc38b..8068f3bc4f61e4b134ff625b081bd9b5627f8a53 100644 (file)
--- a/components/esp32/system_api.c
+++ b/components/esp32/system_api.c
@@ -327,7 +327,7 @@ void IRAM_ATTR esp_restart_noos()
 
     // Reset timer/spi/uart
     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
-            DPORT_TIMERS_RST | DPORT_SPI_RST_1 | DPORT_UART_RST);
+            DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
     DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
 
     // Set CPU back to XTAL source, no PLL, same as hard reset

diff --git a/components/esp32/test/test_intr_alloc.c b/components/esp32/test/test_intr_alloc.c
index 2eef456a56c3d87a6c3086c7721fa2a95654fee9..00a325b1ea804decdef8a2cd744f7ec106cef66f 100644 (file)
--- a/components/esp32/test/test_intr_alloc.c
+++ b/components/esp32/test/test_intr_alloc.c
@@ -16,6 +16,7 @@
 #include "soc/dport_reg.h"
 #include "soc/io_mux_reg.h"
 #include "esp_intr_alloc.h"
+#include "driver/periph_ctrl.h"
 #include "driver/timer.h"
 
 
@@ -266,9 +267,8 @@ TEST_CASE("allocate 2 handlers for a same source and remove the later one","[esp
     intr_alloc_test_ctx_t ctx = {false, false, false, false };
     intr_handle_t handle1, handle2;
 
-    //enable spi
-    DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN );
-    DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
+    //enable HSPI(spi2)
+    periph_module_enable(PERIPH_HSPI_MODULE);
 
     esp_err_t r;
     r=esp_intr_alloc(ETS_SPI2_INTR_SOURCE, ESP_INTR_FLAG_SHARED, int_handler1, &ctx, &handle1);

diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h
index b7c9bdb905be7e07b124a7e8e6ea41c5df8d2a26..ecb1cf3a29076ff80b692f9cc535b8997a97b10b 100644 (file)
--- a/components/soc/esp32/include/soc/dport_reg.h
+++ b/components/soc/esp32/include/soc/dport_reg.h
@@ -958,7 +958,8 @@
 #define DPORT_CAN_CLK_EN   (BIT(19))
 #define DPORT_I2C_EXT1_CLK_EN   (BIT(18))
 #define DPORT_PWM0_CLK_EN   (BIT(17))
-#define DPORT_SPI_CLK_EN_2   (BIT(16))
+#define DPORT_SPI_CLK_EN_2   (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/
+#define DPORT_SPI3_CLK_EN   (BIT(16))
 #define DPORT_TIMERGROUP1_CLK_EN   (BIT(15))
 #define DPORT_EFUSE_CLK_EN   (BIT(14))
 #define DPORT_TIMERGROUP_CLK_EN   (BIT(13))
@@ -968,12 +969,14 @@
 #define DPORT_RMT_CLK_EN   (BIT(9))
 #define DPORT_UHCI0_CLK_EN   (BIT(8))
 #define DPORT_I2C_EXT0_CLK_EN   (BIT(7))
-#define DPORT_SPI_CLK_EN   (BIT(6))
+#define DPORT_SPI_CLK_EN   (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/
+#define DPORT_SPI2_CLK_EN   (BIT(6))
 #define DPORT_UART1_CLK_EN   (BIT(5))
 #define DPORT_I2S0_CLK_EN   (BIT(4))
 #define DPORT_WDG_CLK_EN   (BIT(3))
 #define DPORT_UART_CLK_EN   (BIT(2))
-#define DPORT_SPI_CLK_EN_1   (BIT(1))
+#define DPORT_SPI_CLK_EN_1   (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/
+#define DPORT_SPI01_CLK_EN   (BIT(1))
 #define DPORT_TIMERS_CLK_EN   (BIT(0))
 #define DPORT_PERIP_RST_EN_REG          (DR_REG_DPORT_BASE + 0x0C4)
 /* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -992,7 +995,8 @@
 #define DPORT_CAN_RST   (BIT(19))
 #define DPORT_I2C_EXT1_RST   (BIT(18))
 #define DPORT_PWM0_RST   (BIT(17))
-#define DPORT_SPI_RST_2   (BIT(16))
+#define DPORT_SPI_RST_2   (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/
+#define DPORT_SPI3_RST   (BIT(16))
 #define DPORT_TIMERGROUP1_RST   (BIT(15))
 #define DPORT_EFUSE_RST   (BIT(14))
 #define DPORT_TIMERGROUP_RST   (BIT(13))
@@ -1002,12 +1006,14 @@
 #define DPORT_RMT_RST   (BIT(9))
 #define DPORT_UHCI0_RST   (BIT(8))
 #define DPORT_I2C_EXT0_RST   (BIT(7))
-#define DPORT_SPI_RST   (BIT(6))
+#define DPORT_SPI_RST   (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/
+#define DPORT_SPI2_RST   (BIT(6))
 #define DPORT_UART1_RST   (BIT(5))
 #define DPORT_I2S0_RST   (BIT(4))
 #define DPORT_WDG_RST   (BIT(3))
 #define DPORT_UART_RST   (BIT(2))
-#define DPORT_SPI_RST_1   (BIT(1))
+#define DPORT_SPI_RST_1   (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/
+#define DPORT_SPI01_RST   (BIT(1))
 #define DPORT_TIMERS_RST   (BIT(0))
 #define DPORT_SLAVE_SPI_CONFIG_REG          (DR_REG_DPORT_BASE + 0x0C8)
 /* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */