[Hexagon] Do not insert instructions before PHI nodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297141 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonBitSimplify.cpp b/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 797874636844d899335ac66ecf5dc1f562d3fd07..a155762cd4a7d256565b70afc2f33568ffa9e5df 100644 (file)
--- a/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2375,7 +2375,9 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
     DebugLoc DL = MI->getDebugLoc();
     MachineBasicBlock &B = *MI->getParent();
     unsigned NewR = MRI.createVirtualRegister(FRC);
-    auto MIB = BuildMI(B, MI, DL, HII.get(ExtOpc), NewR)
+    auto At = MI->isPHI() ? B.getFirstNonPHI()
+                          : MachineBasicBlock::iterator(MI);
+    auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
                   .addReg(R, 0, SR);
     switch (ExtOpc) {
       case Hexagon::A2_sxtb:

diff --git a/test/CodeGen/Hexagon/bit-phi.ll b/test/CodeGen/Hexagon/bit-phi.ll
index 86b18d8bf2563bc11818cf6e3eb1da1c9ca28de4..7abfba079bb07456ec77c301a3eb190ad6dfaea9 100644 (file)
--- a/test/CodeGen/Hexagon/bit-phi.ll
+++ b/test/CodeGen/Hexagon/bit-phi.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -march=hexagon < %s
+; RUN: llc -march=hexagon -disable-hcp < %s
 ; REQUIRES: asserts
 
 target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"