Code size optimisation: don't expand a div to a mul and and a shift sequence.

As a result, the urem instruction will not be expanded to a sequence of umull,
lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod.

Differential Revision: http://reviews.llvm.org/D22131

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274843 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index dc2ff6eb918b588b45019b9dce6cad06770a0f02..456c5498e3cdba1562d9dd37f364fada70d22856 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14516,6 +14516,11 @@ SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
 /// number.
 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
+  // when optimising for size, we don't want to expand a div to a mul and
+  // and a shift.
+  if (ForCodeSize)
+    return SDValue();
+
   ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
   if (!C)
     return SDValue();

diff --git a/test/CodeGen/ARM/urem-opt-size.ll b/test/CodeGen/ARM/urem-opt-size.ll
new file mode 100644 (file)
index 0000000..4490a47
--- /dev/null
+++ b/test/CodeGen/ARM/urem-opt-size.ll
@@ -0,0 +1,25 @@
+; When optimising for size, we don't want to expand a div to a mul and
+; and a shift sequence. As a result, the urem instruction will not be
+; expanded to a sequence of umull, lsrs, muls and sub instructions, but
+; just a call to __aeabi_uidivmod.
+;
+; RUN: llc -mtriple=armv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv7m-arm-none-eabi"
+
+define i32 @foo() local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: foo:
+; CHECK: __aeabi_uidivmod
+; CHECK-NOT: umull
+  %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)()
+  %rem = urem i32 %call, 1000000
+  %cmp = icmp eq i32 %rem, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+declare i32 @GetValue(...) local_unnamed_addr
+
+attributes #0 = { minsize nounwind optsize }