#ifndef LLVM_ADT_STRINGREF_H
#define LLVM_ADT_STRINGREF_H
+#include "llvm/ADT/iterator_range.h"
#include "llvm/Support/Compiler.h"
#include <algorithm>
#include <cassert>
const unsigned char *bytes_end() const {
return reinterpret_cast<const unsigned char *>(end());
}
+ iterator_range<const unsigned char *> bytes() const {
+ return make_range(bytes_begin(), bytes_end());
+ }
/// @}
/// @name String Operations
/// Heuristics for estimating register pressure.
unsigned ParallelLiveRanges;
- signed HorizontalVerticalBalance;
+ int HorizontalVerticalBalance;
public:
ResourcePriorityQueue(SelectionDAGISel *IS);
/// Single cost function reflecting benefit of scheduling SU
/// in the current cycle.
- signed SUSchedulingCost (SUnit *SU);
+ int SUSchedulingCost (SUnit *SU);
/// InitNumRegDefsLeft - Determine the # of regs defined by this node.
///
void initNumRegDefsLeft(SUnit *SU);
void updateNumRegDefsLeft(SUnit *SU);
- signed regPressureDelta(SUnit *SU, bool RawPressure = false);
- signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
+ int regPressureDelta(SUnit *SU, bool RawPressure = false);
+ int rawRegPressureDelta (SUnit *SU, unsigned RCId);
bool empty() const override { return Queue.empty(); }
//===----------------------------------------------------------------------===//
#include "llvm/Analysis/ConstantFolding.h"
+#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
// directly if string length is small enough.
StringRef Str;
if (getConstantStringInfo(CE, Str) && !Str.empty()) {
- unsigned StrLen = Str.size();
+ size_t StrLen = Str.size();
unsigned NumBits = Ty->getPrimitiveSizeInBits();
// Replace load with immediate integer if the result is an integer or fp
// value.
APInt StrVal(NumBits, 0);
APInt SingleChar(NumBits, 0);
if (DL.isLittleEndian()) {
- for (signed i = StrLen-1; i >= 0; i--) {
- SingleChar = (uint64_t) Str[i] &
- std::numeric_limits<unsigned char>::max();
+ for (unsigned char C : reverse(Str.bytes())) {
+ SingleChar = static_cast<uint64_t>(C);
StrVal = (StrVal << 8) | SingleChar;
}
} else {
- for (unsigned i = 0; i < StrLen; i++) {
- SingleChar = (uint64_t) Str[i] &
- std::numeric_limits<unsigned char>::max();
+ for (unsigned char C : Str.bytes()) {
+ SingleChar = static_cast<uint64_t>(C);
StrVal = (StrVal << 8) | SingleChar;
}
// Append NULL at the end.
TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
// Determine the residual right-shift amount.
- signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
+ int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
// If the shift is not a no-op (in which case this should be just a sign
// extend already), the truncated to type is legal, sign_extend is legal
cl::ZeroOrMore, cl::init(false),
cl::desc("Disable use of DFA during scheduling"));
-static cl::opt<signed> RegPressureThreshold(
+static cl::opt<int> RegPressureThreshold(
"dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5),
cl::desc("Track reg pressure and switch priority to in-depth"));
}
}
-signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
- signed RegBalance = 0;
+int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
+ int RegBalance = 0;
if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
return RegBalance;
/// The RawPressure flag makes this function to ignore
/// existing reg file sizes, and report raw def/use
/// balance.
-signed ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {
- signed RegBalance = 0;
+int ResourcePriorityQueue::regPressureDelta(SUnit *SU, bool RawPressure) {
+ int RegBalance = 0;
if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode())
return RegBalance;
/// Returns single number reflecting benefit of scheduling SU
/// in the current cycle.
-signed ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
+int ResourcePriorityQueue::SUSchedulingCost(SUnit *SU) {
// Initial trivial priority.
- signed ResCount = 1;
+ int ResCount = 1;
// Do not waste time on a node that is already scheduled.
if (SU->isScheduled)
std::vector<SUnit *>::iterator Best = Queue.begin();
if (!DisableDFASched) {
- signed BestCost = SUSchedulingCost(*Best);
+ int BestCost = SUSchedulingCost(*Best);
for (std::vector<SUnit *>::iterator I = std::next(Queue.begin()),
E = Queue.end(); I != E; ++I) {
// isEquivalentMaskless() is the code for testing if the AND can be removed
// factored out of the DAG recognition as the DAG can take several forms.
-static
-bool isEquivalentMaskless(unsigned CC, unsigned width,
- ISD::LoadExtType ExtType, signed AddConstant,
- signed CompConstant) {
+static bool isEquivalentMaskless(unsigned CC, unsigned width,
+ ISD::LoadExtType ExtType, int AddConstant,
+ int CompConstant) {
// By being careful about our equations and only writing the in term
// symbolic values and well known constants (0, 1, -1, MaxUInt) we can
// make them generally applicable to all bit widths.
- signed MaxUInt = (1 << width);
+ int MaxUInt = (1 << width);
// For the purposes of these comparisons sign extending the type is
// equivalent to zero extending the add and displacing it by half the integer
// ARM halfword load/stores and signed byte loads need an additional
// operand.
if (useAM3) {
- signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
+ int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
MIB.addReg(0);
MIB.addImm(Imm);
} else {
// ARM halfword load/stores and signed byte loads need an additional
// operand.
if (useAM3) {
- signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
+ int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
MIB.addReg(0);
MIB.addImm(Imm);
} else {
MCOperand &MO = Inst.getOperand(1);
int64_t Value;
if (MO.getExpr()->evaluateAsAbsolute(Value)) {
- unsigned long long u64 = Value;
- signed int s8 = (u64 >> 32) & 0xFFFFFFFF;
- if (s8 < -128 || s8 > 127)
+ int s8 = Hi_32(Value);
+ if (!isInt<8>(s8))
OutOfRange(IDLoc, s8, -128);
MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
MCConstantExpr::create(s8, Context), Context))); // upper 32
auto Expr = HexagonMCExpr::create(
- MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),
- Context);
+ MCConstantExpr::create(Lo_32(Value), Context), Context);
HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
uint32_t Offset = Fixup.getOffset();
unsigned NumBytes = getFixupKindNumBytes(Kind);
assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
- char* InstAddr = Data + Offset;
+ char *InstAddr = Data + Offset;
Value = adjustFixupValue(Kind, FixupValue);
if(!Value)
return;
- signed sValue = (signed)Value;
+ int sValue = (int)Value;
switch((unsigned)Kind) {
default:
unsigned VR = MF.getRegInfo().createVirtualRegister(RC);
assert(isInt<16>(MFI->getMaxAlignment()) &&
"Function's alignment size requirement is not supported.");
- int MaxAlign = - (signed) MFI->getMaxAlignment();
+ int MaxAlign = -(int)MFI->getMaxAlignment();
BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
def HA16 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- signed int Val = N->getZExtValue();
+ int Val = N->getZExtValue();
return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
}]>;
def MB : SDNodeXForm<imm, [{
if (Op1 == &GEP)
return nullptr;
- signed DI = -1;
+ int DI = -1;
for (auto I = PN->op_begin()+1, E = PN->op_end(); I !=E; ++I) {
GetElementPtrInst *Op2 = dyn_cast<GetElementPtrInst>(*I);
projects / llvm / commitdiff