]> granicus.if.org Git - llvm/commitdiff
[X86] Fix VEX encoded VPMADDUBSW to not be marked commutable.
authorCraig Topper <craig.topper@gmail.com>
Sat, 3 Dec 2016 05:35:44 +0000 (05:35 +0000)
committerCraig Topper <craig.topper@gmail.com>
Sat, 3 Dec 2016 05:35:44 +0000 (05:35 +0000)
This was accidentallly broken in r285515 when we started lowering the intrinsic to an ISD node. Should fix PR31241.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288578 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/avx-intrinsics-x86.ll
test/CodeGen/X86/avx2-intrinsics-x86.ll

index 9a25cc0065a22cfbcea5b09267bb88fa40349a45..070bf49b8b01862b109ed970a65b92e234962bc8 100644 (file)
@@ -5496,13 +5496,13 @@ let isCommutable = 0 in {
   defm VPSHUFB    : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, v16i8,
                                   VR128, loadv2i64, i128mem,
                                   SSE_PSHUFB, 0>, VEX_4V;
+  defm VPMADDUBSW : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v8i16,
+                                  v16i8, VR128, loadv2i64, i128mem,
+                                  SSE_PMADD, 0>, VEX_4V;
 }
 defm VPMULHRSW    : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v8i16, v8i16,
                                   VR128, loadv2i64, i128mem,
                                   SSE_PMULHRSW, 0>, VEX_4V;
-defm VPMADDUBSW : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v8i16,
-                                v16i8, VR128, loadv2i64, i128mem,
-                                SSE_PMADD, 0>, VEX_4V;
 }
 
 let ImmT = NoImm, Predicates = [HasAVX] in {
@@ -5542,13 +5542,13 @@ let isCommutable = 0 in {
   defm VPSHUFBY   : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, v32i8,
                                   VR256, loadv4i64, i256mem,
                                   SSE_PSHUFB, 0>, VEX_4V, VEX_L;
+  defm VPMADDUBSWY : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v16i16,
+                                   v32i8, VR256, loadv4i64, i256mem,
+                                   SSE_PMADD, 0>, VEX_4V, VEX_L;
 }
 defm VPMULHRSWY   : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v16i16, v16i16,
                                   VR256, loadv4i64, i256mem,
                                   SSE_PMULHRSW, 0>, VEX_4V, VEX_L;
-defm VPMADDUBSWY : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v16i16,
-                                 v32i8, VR256, loadv4i64, i256mem,
-                                 SSE_PMADD, 0>, VEX_4V, VEX_L;
 }
 
 let ImmT = NoImm, Predicates = [HasAVX2] in {
index c0bc259bae29a4024690c874b933c56fba465962..ba0c67a8e5c2c1befc4b468bcb3b2a4cd14f478e 100644 (file)
@@ -2545,7 +2545,8 @@ define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128_load_op0(<16 x i8>* %ptr, <16 x
 ; AVX-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
 ; AVX:       ## BB#0:
 ; AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX-NEXT:    vpmaddubsw (%eax), %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x04,0x00]
+; AVX-NEXT:    vmovdqa (%eax), %xmm1 ## encoding: [0xc5,0xf9,0x6f,0x08]
+; AVX-NEXT:    vpmaddubsw %xmm0, %xmm1, %xmm0 ## encoding: [0xc4,0xe2,0x71,0x04,0xc0]
 ; AVX-NEXT:    retl ## encoding: [0xc3]
 ;
 ; AVX512VL-LABEL: test_x86_ssse3_pmadd_ub_sw_128_load_op0:
index c8c0e103155310d6e5e251404e30e816ba636b7b..30b32688ef16d54facff8c05b98de2134d2a4593 100644 (file)
@@ -761,7 +761,8 @@ define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(<32 x i8>* %ptr, <32 x i8>
 ; AVX2-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0:
 ; AVX2:       ## BB#0:
 ; AVX2-NEXT:    movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
-; AVX2-NEXT:    vpmaddubsw (%eax), %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x04,0x00]
+; AVX2-NEXT:    vmovdqa (%eax), %ymm1 ## encoding: [0xc5,0xfd,0x6f,0x08]
+; AVX2-NEXT:    vpmaddubsw %ymm0, %ymm1, %ymm0 ## encoding: [0xc4,0xe2,0x75,0x04,0xc0]
 ; AVX2-NEXT:    retl ## encoding: [0xc3]
 ;
 ; AVX512VL-LABEL: test_x86_avx2_pmadd_ub_sw_load_op0: