Change order of conditions in predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@349918
91177308-0d34-0410-b5e6-
96231b3b80d8
IsArithLogicShiftOp.ValidOpcodes,
MCReturnStatement<
CheckAny<
- [CheckAll<
+ [ExynosCheckShift,
+ CheckAll<
[CheckShiftLSL,
- CheckShiftBy8]>,
- ExynosCheckShift]>>>],
+ CheckShiftBy8]>]>>>],
MCReturnStatement<FalsePred>>>;
def ExynosShiftExPred : MCSchedPredicate<ExynosShiftExFn>;
-
// Identify arithmetic and logic immediate instructions.
def ExynosCheapFn : TIIPredicate<
"isExynosCheapAsMove",