]> granicus.if.org Git - esp-idf/commitdiff
add MACRO to get flash pad number from efuse value
authorJack <jack@espressif.com>
Mon, 12 Sep 2016 05:54:08 +0000 (13:54 +0800)
committerWu Jian Gang <wujiangang@espressif.com>
Mon, 12 Sep 2016 09:47:50 +0000 (17:47 +0800)
components/esp32/include/rom/efuse.h

index 62692c3098be46de589180902938947bdfa41e94..58cfdb20bc3e00b9d7a03b04326280feaed95e46 100644 (file)
@@ -55,7 +55,7 @@ void ets_efuse_program_op(void);
   *
   * @param  null
   *
-  * @return u32: 1 for 100KHZ.
+  * @return u32: 1 for 100KHZ, range is 0 to 255.
   */
 uint32_t ets_efuse_get_8M_clock(void);
 
@@ -69,6 +69,27 @@ uint32_t ets_efuse_get_8M_clock(void);
   */
 uint32_t ets_efuse_get_spiconfig(void);
 
+#define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
+#define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
+#define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
+#define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
+#define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
+
+
+#define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
+#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
+#define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
+
 /**
   * @brief  A crc8 algorithm used in efuse check.
   *