]> granicus.if.org Git - llvm/commitdiff
[mips][dsp] Fix use without def on DSPCtrl registers read by rddsp intrinsic.
authorDaniel Sanders <daniel.sanders@imgtec.com>
Tue, 14 Jun 2016 09:29:46 +0000 (09:29 +0000)
committerDaniel Sanders <daniel.sanders@imgtec.com>
Tue, 14 Jun 2016 09:29:46 +0000 (09:29 +0000)
Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D21063

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272647 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsSEISelDAGToDAG.cpp
test/CodeGen/Mips/dsp-r1.ll

index 8ea35f135420ff8f484af1ec1a44c67dda5435b0..72c15e22c482d59a18991301ae2679d7ccc562ef 100644 (file)
@@ -47,7 +47,8 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
                                                MachineFunction &MF) {
   MachineInstrBuilder MIB(MF, &MI);
   unsigned Mask = MI.getOperand(1).getImm();
-  unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
+  unsigned Flag =
+      IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
 
   if (Mask & 1)
     MIB.addReg(Mips::DSPPos, Flag);
index fbd9703996409655473482c61bcc2a1ba7bbbda4..edd6258270a0c1c19ff356364220fb9b1f94464b 100644 (file)
@@ -1,4 +1,5 @@
-; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \
+; RUN:     FileCheck %s
 
 define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind {
 entry: