AMDGPU/GlobalISel: Only make f16 constants legal on f16 targets

We could deal with it, but there's no real point.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@353845 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 3319a04ecedd0da1c61f01bf06f1edbb2fe23ec5..ecf8e1b732e97e6b5dcdf73ec3b10b64f7589172 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -149,8 +149,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
     // Don't worry about the size constraint.
     .legalIf(all(isPointer(0), isPointer(1)));
 
-  getActionDefinitionsBuilder(G_FCONSTANT)
-    .legalFor({S32, S64, S16});
+  if (ST.has16BitInsts()) {
+    getActionDefinitionsBuilder(G_FCONSTANT)
+      .legalFor({S32, S64, S16})
+      .clampScalar(0, S16, S64);
+  } else {
+    getActionDefinitionsBuilder(G_FCONSTANT)
+      .legalFor({S32, S64})
+      .clampScalar(0, S32, S64);
+  }
 
   getActionDefinitionsBuilder(G_IMPLICIT_DEF)
     .legalFor({S1, S32, S64, V2S32, V4S32, V2S16, V4S16, GlobalPtr,

diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
index 8d9485dc6d8deba612c60eafaab425a7a57d0056..0d46f5fe0026d48d7bec6a619a74bbe4059b7567 100644 (file)
--- a/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
+++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
@@ -1,15 +1,18 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI  %s
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
 
 ---
 name: test_fconstant_s32
 body: |
   bb.0:
 
-    ; CHECK-LABEL: name: test_fconstant_s32
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
-    ; CHECK: $vgpr0 = COPY [[C]](s32)
+    ; SI-LABEL: name: test_fconstant_s32
+    ; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; SI: $vgpr0 = COPY [[C]](s32)
+    ; VI-LABEL: name: test_fconstant_s32
+    ; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; VI: $vgpr0 = COPY [[C]](s32)
     %0:_(s32) = G_FCONSTANT float 1.0
     $vgpr0 = COPY %0
 ...
@@ -18,9 +21,12 @@ name: test_fconstant_s64
 body: |
   bb.0:
 
-    ; CHECK-LABEL: name: test_fconstant_s64
-    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
-    ; CHECK: $vgpr0_vgpr1 = COPY [[C]](s64)
+    ; SI-LABEL: name: test_fconstant_s64
+    ; SI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+    ; SI: $vgpr0_vgpr1 = COPY [[C]](s64)
+    ; VI-LABEL: name: test_fconstant_s64
+    ; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
+    ; VI: $vgpr0_vgpr1 = COPY [[C]](s64)
     %0:_(s64) = G_FCONSTANT double 1.0
     $vgpr0_vgpr1 = COPY %0
 ...
@@ -30,10 +36,15 @@ name: test_fconstant_s16
 body: |
   bb.0:
 
-    ; CHECK-LABEL: name: test_fconstant_s16
-    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; SI-LABEL: name: test_fconstant_s16
+    ; SI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+    ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C]](s32)
+    ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
+    ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
+    ; VI-LABEL: name: test_fconstant_s16
+    ; VI: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
+    ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s16)
+    ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
     %0:_(s16) = G_FCONSTANT half 1.0
     %1:_(s32) = G_ANYEXT %0
     $vgpr0 = COPY %1