[InstCombine] use m_APInt to allow icmp X, C folds for splat constant vectors

isSignBitCheck could be changed to take a pointer param to avoid the 'UnusedBit' ugliness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281231 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Transforms/InstCombine/InstCombineCompares.cpp b/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 3108142397f56ee8ef16640529ff71acb7247a8e..6c8eea1f1bc58d820bee266ca17f4d2dfb12e07c 100644 (file)
--- a/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -3153,9 +3153,10 @@ Instruction *InstCombiner::foldICmpUsingKnownBits(ICmpInst &I) {
   // If this is a normal comparison, it demands all bits. If it is a sign bit
   // comparison, it only demands the sign bit.
   bool IsSignBit = false;
-  if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
+  const APInt *CmpC;
+  if (match(Op1, m_APInt(CmpC))) {
     bool UnusedBit;
-    IsSignBit = isSignBitCheck(Pred, CI->getValue(), UnusedBit);
+    IsSignBit = isSignBitCheck(Pred, *CmpC, UnusedBit);
   }
 
   APInt Op0KnownZero(BitWidth, 0), Op0KnownOne(BitWidth, 0);

diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index 12ab3535d4a49b18ca0429b155c2e01f71f71096..dab212dc583d1b5ceb6f95f33033a63473540cd0 100644 (file)
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -628,11 +628,9 @@ define i1 @test35(i32 %X) {
   ret i1 %tmp2
 }
 
-; FIXME: Vectors should fold the same way.
 define <2 x i1> @test35vec(<2 x i32> %X) {
 ; CHECK-LABEL: @test35vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> %X, <i32 7, i32 7>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> %X, zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[TMP2]]
 ;
   %tmp1 = ashr <2 x i32> %X, <i32 7, i32 7>

diff --git a/test/Transforms/InstCombine/vec_sext.ll b/test/Transforms/InstCombine/vec_sext.ll
index be808e902ab22c8e000ba7236f2219aca5fea36c..10947c1781e0322757493d6c058b16c93017c651 100644 (file)
--- a/test/Transforms/InstCombine/vec_sext.ll
+++ b/test/Transforms/InstCombine/vec_sext.ll
@@ -3,8 +3,8 @@
 
 define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: @psignd_3(
-; CHECK-NEXT:    [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
+; CHECK-NEXT:    [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
 ; CHECK-NEXT:    [[T1:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
 ; CHECK-NEXT:    [[T2:%.*]] = and <4 x i32> %a, [[T1]]
 ; CHECK-NEXT:    [[T3:%.*]] = and <4 x i32> [[B_LOBIT]], [[SUB]]
@@ -25,8 +25,8 @@ define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) {
 
 define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
+; CHECK-NEXT:    [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
 ; CHECK-NEXT:    [[B_LOBIT_NOT:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
 ; CHECK-NEXT:    [[T2:%.*]] = and <4 x i32> [[B_LOBIT]], %a
 ; CHECK-NEXT:    [[T3:%.*]] = and <4 x i32> [[B_LOBIT_NOT]], [[SUB]]