Fix #211: Add INVEPT, INVVPID, and GETSEC instructions.

INVEPT and INVVPID is enabled via the "eptvpid" cpu feature.
GETSEC is enabled via the "smx" cpu feature.

svn path=/trunk/yasm/; revision=2339

diff --git a/modules/arch/x86/gen_x86_insn.py b/modules/arch/x86/gen_x86_insn.py
index 83f7111ed8122c45f0155126e1c9d5ade7217ff3..1074ad1563b41caefb4e78b10ba0abc030640bfa 100755 (executable)
--- a/modules/arch/x86/gen_x86_insn.py
+++ b/modules/arch/x86/gen_x86_insn.py
@@ -43,7 +43,7 @@ ordered_cpu_features = [
     "FPU", "Cyrix", "AMD", "MMX", "3DNow", "SMM", "SSE", "SSE2",
     "SSE3", "SVM", "PadLock", "SSSE3", "SSE41", "SSE42", "SSE4a", "SSE5",
     "AVX", "FMA", "AES", "CLMUL", "MOVBE", "XOP", "FMA4", "F16C",
-    "FSGSBASE", "RDRND"]
+    "FSGSBASE", "RDRND", "XSAVEOPT", "EPTVPID"]
 unordered_cpu_features = ["Priv", "Prot", "Undoc", "Obs"]
 
 # Predefined VEX prefix field values
@@ -5272,6 +5272,28 @@ add_insn("vmovsd", "movsd", modifiers=[VEXL0], avx=True)
 # P4 VMX Instructions
 #####################################################################
 
+add_group("eptvpid",
+    modifiers=["Op2Add"],
+    suffix="l",
+    not64=True,
+    cpu=["EPTVPID"],
+    opersize=32,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x80],
+    operands=[Operand(type="Reg", size=32, dest="Spare"),
+              Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_group("eptvpid",
+    modifiers=["Op2Add"],
+    suffix="q",
+    cpu=["EPTVPID"],
+    opersize=64,
+    prefix=0x66,
+    opcode=[0x0F, 0x38, 0x80],
+    operands=[Operand(type="Reg", size=64, dest="Spare"),
+              Operand(type="Mem", size=128, relaxed=True, dest="EA")])
+add_insn("invept", "eptvpid", modifiers=[0])
+add_insn("invvpid", "eptvpid", modifiers=[1])
+
 add_insn("vmcall", "threebyte", modifiers=[0x0F, 0x01, 0xC1], cpu=["P4"])
 add_insn("vmlaunch", "threebyte", modifiers=[0x0F, 0x01, 0xC2], cpu=["P4"])
 add_insn("vmresume", "threebyte", modifiers=[0x0F, 0x01, 0xC3], cpu=["P4"])
@@ -5332,6 +5354,11 @@ add_group("vmxthreebytemem",
 add_insn("vmclear", "vmxthreebytemem", modifiers=[0x66])
 add_insn("vmxon", "vmxthreebytemem", modifiers=[0xF3])
 
+#####################################################################
+# Intel SMX Instructions
+#####################################################################
+add_insn("getsec", "twobyte", modifiers=[0x0F, 0x37], cpu=["SMX"])
+
 add_insn("cvttpd2pi", "cvt_mm_xmm", modifiers=[0x66, 0x2C], cpu=["SSE2"])
 add_insn("cvttsd2si", "cvt_rx_xmm64", modifiers=[0xF2, 0x2C], cpu=["SSE2"])
 add_insn("cvttpd2dq", "xmm_xmm128", modifiers=[0x66, 0xE6], cpu=["SSE2"])

diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index b99a52f9d35c10387e979a847e2d7d9a44d00deb..f46fa07423867a804cb7b602192dd49aad630f0f 100644 (file)
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -56,6 +56,8 @@ EXTRA_DIST += modules/arch/x86/tests/effaddr.hex
 EXTRA_DIST += modules/arch/x86/tests/enter.asm
 EXTRA_DIST += modules/arch/x86/tests/enter.errwarn
 EXTRA_DIST += modules/arch/x86/tests/enter.hex
+EXTRA_DIST += modules/arch/x86/tests/eptvpid.asm
+EXTRA_DIST += modules/arch/x86/tests/eptvpid.hex
 EXTRA_DIST += modules/arch/x86/tests/f16c.asm
 EXTRA_DIST += modules/arch/x86/tests/f16c.hex
 EXTRA_DIST += modules/arch/x86/tests/far64.asm
@@ -183,6 +185,8 @@ EXTRA_DIST += modules/arch/x86/tests/simd64-1.asm
 EXTRA_DIST += modules/arch/x86/tests/simd64-1.hex
 EXTRA_DIST += modules/arch/x86/tests/simd64-2.asm
 EXTRA_DIST += modules/arch/x86/tests/simd64-2.hex
+EXTRA_DIST += modules/arch/x86/tests/smx.asm
+EXTRA_DIST += modules/arch/x86/tests/smx.hex
 EXTRA_DIST += modules/arch/x86/tests/sse-prefix.asm
 EXTRA_DIST += modules/arch/x86/tests/sse-prefix.hex
 EXTRA_DIST += modules/arch/x86/tests/sse3.asm

diff --git a/modules/arch/x86/tests/eptvpid.asm b/modules/arch/x86/tests/eptvpid.asm
new file mode 100644 (file)
index 0000000..8c4881f
--- /dev/null
+++ b/modules/arch/x86/tests/eptvpid.asm
@@ -0,0 +1,8 @@
+[bits 32]
+invept eax, [eax]
+invvpid eax, [eax]
+
+[bits 64]
+invept rax, [rax]
+invvpid rax, [rax]
+

diff --git a/modules/arch/x86/tests/eptvpid.hex b/modules/arch/x86/tests/eptvpid.hex
new file mode 100644 (file)
index 0000000..1e2c242
--- /dev/null
+++ b/modules/arch/x86/tests/eptvpid.hex
@@ -0,0 +1,22 @@
+66 
+0f 
+38 
+80 
+00 
+66 
+0f 
+38 
+81 
+00 
+66 
+48 
+0f 
+38 
+80 
+00 
+66 
+48 
+0f 
+38 
+81 
+00 

diff --git a/modules/arch/x86/tests/smx.asm b/modules/arch/x86/tests/smx.asm
new file mode 100644 (file)
index 0000000..e5ca5b5
--- /dev/null
+++ b/modules/arch/x86/tests/smx.asm
@@ -0,0 +1,3 @@
+[bits 32]
+getsec
+

diff --git a/modules/arch/x86/tests/smx.hex b/modules/arch/x86/tests/smx.hex
new file mode 100644 (file)
index 0000000..7e6dae1
--- /dev/null
+++ b/modules/arch/x86/tests/smx.hex
@@ -0,0 +1,2 @@
+0f 
+37 

diff --git a/modules/arch/x86/x86arch.h b/modules/arch/x86/x86arch.h
index a148ee377978e7aa72ad2d8cdc4166e67854fff8..773f163eecd2341a2d4a582fa385b71304c1f305 100644 (file)
--- a/modules/arch/x86/x86arch.h
+++ b/modules/arch/x86/x86arch.h
@@ -76,6 +76,8 @@
 #define CPU_FSGSBASE 42     /* Intel FSGSBASE instructions */
 #define CPU_RDRND   43      /* Intel RDRND instruction */
 #define CPU_XSAVEOPT 44     /* Intel XSAVEOPT instruction */
+#define CPU_EPTVPID 45      /* Intel INVEPT, INVVPID instructions */
+#define CPU_SMX     46      /* Intel SMX instruction (GETSEC) */
 
 enum x86_parser_type {
     X86_PARSER_NASM = 0,

diff --git a/modules/arch/x86/x86cpu.gperf b/modules/arch/x86/x86cpu.gperf
index 3baa954c01090bd0ce9a1cb8a7fe56c8f7e38c5b..488f2791841f7912d19a1f5183aa8cadeaa73df7 100644 (file)
--- a/modules/arch/x86/x86cpu.gperf
+++ b/modules/arch/x86/x86cpu.gperf
@@ -385,6 +385,10 @@ rdrnd,             x86_cpu_set,    CPU_RDRND
 nordrnd,       x86_cpu_clear,  CPU_RDRND
 xsaveopt,      x86_cpu_set,    CPU_XSAVEOPT
 noxsaveopt,    x86_cpu_clear,  CPU_XSAVEOPT
+eptvpid,       x86_cpu_set,    CPU_EPTVPID
+noeptvpid,     x86_cpu_clear,  CPU_EPTVPID
+smx,           x86_cpu_set,    CPU_SMX
+nosmx,         x86_cpu_clear,  CPU_SMX
 # Change NOP patterns
 basicnop,      x86_nop,        X86_NOP_BASIC
 intelnop,      x86_nop,        X86_NOP_INTEL