[ARM] Fix parsing of special register masks

This parsing code was incorrectly checking for invalid characters, so an
invalid instruction like:
  msr spsr_w, r0
would be emitted as:
  msr spsr_cxsf, r0

Differential revision: https://reviews.llvm.org/D30462

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296607 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index dae8618fa070d1e5afb28c4d183024d3dd308b8f..c7d0709a1a77ae7d7f65b4b9d578d262d786d3b3 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -4330,7 +4330,7 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
 
       // If some specific flag is already set, it means that some letter is
       // present more than once, this is not acceptable.
-      if (FlagsVal == ~0U || (FlagsVal & Flag))
+      if (Flag == ~0U || (FlagsVal & Flag))
         return MatchOperand_NoMatch;
       FlagsVal |= Flag;
     }

diff --git a/test/MC/ARM/invalid-special-reg.s b/test/MC/ARM/invalid-special-reg.s
new file mode 100644 (file)
index 0000000..7a192e7
--- /dev/null
+++ b/test/MC/ARM/invalid-special-reg.s
@@ -0,0 +1,11 @@
+@ RUN: not llvm-mc -triple armv7a--none-eabi < %s |& FileCheck %s
+@ RUN: not llvm-mc -triple thumbv7a--none-eabi < %s |& FileCheck %s
+
+  msr apsr_c, r0
+@ CHECK: invalid operand for instruction
+  msr cpsr_w
+@ CHECK: invalid operand for instruction
+  msr cpsr_cc
+@ CHECK: invalid operand for instruction
+  msr xpsr_c
+@ CHECK: invalid operand for instruction