}
define double @test_vfmsd_lane_f64_0(double %a, double %b, <1 x double> %v) {
-; CHCK-LABEL: test_vfmsd_lane_f64_0
-; CHCK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
-; CHCK-NEXT: ret
+; CHECK-LABEL: test_vfmsd_lane_f64_0
+; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NEXT: ret
entry:
%tmp0 = fsub <1 x double> <double -0.000000e+00>, %v
%tmp1 = extractelement <1 x double> %tmp0, i32 0
; CHECK-NEXT: %2 = call %void_one_out_arg_v2i32_1_use @void_one_out_arg_v2i32_1_use.body(<2 x i32>* undef)
; CHECK-NEXT: %3 = extractvalue %void_one_out_arg_v2i32_1_use %2, 0
; CHECK-NEXT: store <2 x i32> %3, <2 x i32>* %0, align 8
-; CHCEK-NEXT: ret void
+; CHECK-NEXT: ret void
define void @void_one_out_arg_v2i32_1_use(<2 x i32>* %val) #0 {
store <2 x i32> <i32 17, i32 9>, <2 x i32>* %val
ret void
; CHECK-NEXT: test_v4i32,\r
; CHECK: ld.param.v4.b32 {[[RE0:%r[0-9]+]], [[RE1:%r[0-9]+]], [[RE2:%r[0-9]+]], [[RE3:%r[0-9]+]]}, [retval0+0];\r
; CHECK: st.param.v4.b32 [func_retval0+0], {[[RE0]], [[RE1]], [[RE2]], [[RE3]]}\r
-; CHCK-NEXT: ret;\r
+; CHECK-NEXT: ret;\r
define <4 x i32> @test_v4i32(<4 x i32> %a) {\r
%r = tail call <4 x i32> @test_v4i32(<4 x i32> %a);\r
ret <4 x i32> %r;\r