driver: add rtc module and bugfix gpio32 gpio33

feature(rtc_module):add rtc module

1. add rtc io control API (pull,output and input)
2. add touch pad API (touch pad read and interrupt)
3. add adc1 API (the max width is 12 Bits and support attenuation)
4. add hall sensor API (support hall sensor read )
5. add dac API (the width is 8 Bits)

bugfix(gpio):gpio32 and gpio33 can not output and input

the gpio32 and gpio33 is initialize by librtc.a,and gpio_config not initialize the gpio as
digital gpio.they can not output and input,when users use gpio32 or gpio33.And there are some problems
about others driver ,when they use gpio32 or gpio33 as  matrix.

diff --git a/components/driver/gpio.c b/components/driver/gpio.c
index d5d4d9d40a03382b6e65f15cc860740923faea54..f8694597a816c69dbc4b49f61bcd203e002dae23 100644 (file)
--- a/components/driver/gpio.c
+++ b/components/driver/gpio.c
@@ -17,6 +17,7 @@
 #include "freertos/FreeRTOS.h"
 #include "freertos/xtensa_api.h"
 #include "driver/gpio.h"
+#include "driver/rtc_io.h"
 #include "soc/soc.h"
 #include "esp_log.h"
 
@@ -69,74 +70,45 @@ const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
     GPIO_PIN_REG_39
 };
 
-const gpio_pu_pd_desc_t gpio_pu_pd_desc[GPIO_PIN_COUNT]={
-    {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M},
-    {PERIPHS_IO_MUX_U0TXD_U, FUN_PU, FUN_PD},
-    {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M},
-    {PERIPHS_IO_MUX_U0RXD_U, FUN_PU, FUN_PD},
-    {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M},
-    {PERIPHS_IO_MUX_GPIO5_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_SD_CLK_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_SD_DATA0_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_SD_DATA1_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_SD_DATA2_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_SD_DATA3_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_SD_CMD_U, FUN_PU, FUN_PD},
-    {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M},
-    {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M},
-    {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M},
-    {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M},
-    {PERIPHS_IO_MUX_GPIO16_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO17_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO18_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO19_U, FUN_PU, FUN_PD},
-    {0,0,0},
-    {PERIPHS_IO_MUX_GPIO21_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO22_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO23_U, FUN_PU, FUN_PD},
-    {0,0,0},
-    {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M},
-    {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M},
-    {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M},
-    {0,0,0},
-    {0,0,0},
-    {0,0,0},
-    {0,0,0},
-    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M},
-    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M},
-    {PERIPHS_IO_MUX_GPIO34_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO35_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO36_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO37_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO38_U, FUN_PU, FUN_PD},
-    {PERIPHS_IO_MUX_GPIO39_U, FUN_PU, FUN_PD}
-};
-
-
 esp_err_t gpio_pullup_en(gpio_num_t gpio_num) {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu);
+    if(RTC_GPIO_IS_VALID_GPIO(gpio_num)){
+        rtc_gpio_pullup_en(gpio_num);
+    }else{
+         REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+    }
     return ESP_OK;
 }
 
 esp_err_t gpio_pullup_dis(gpio_num_t gpio_num) {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    REG_CLR_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu);
+    if(RTC_GPIO_IS_VALID_GPIO(gpio_num)){
+        rtc_gpio_pullup_dis(gpio_num);
+    }else{
+        REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
+    }
     return ESP_OK;
 }
 
 esp_err_t gpio_pulldown_en(gpio_num_t gpio_num) {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pd);
+    if(RTC_GPIO_IS_VALID_GPIO(gpio_num)){
+        rtc_gpio_pulldown_en(gpio_num);
+    }else{
+         REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+    }
     return ESP_OK;
 }
 
 esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num) {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    REG_CLR_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pd);
+    if(RTC_GPIO_IS_VALID_GPIO(gpio_num)){
+        rtc_gpio_pulldown_dis(gpio_num);   
+    }else{
+        REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
+    }
     return ESP_OK;
 }
-
 esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
@@ -148,7 +120,7 @@ esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
 esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    if(xPortGetCoreID() == 0) {
+    if (xPortGetCoreID() == 0) {
         GPIO.pin[gpio_num].int_ena = GPIO_PRO_CPU_INTR_ENA;     //enable pro cpu intr
     } else {
         GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
@@ -166,7 +138,7 @@ esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
 static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    if(gpio_num < 32) {
+    if (gpio_num < 32) {
         GPIO.enable_w1tc = (0x1 << gpio_num);
     } else {
         GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
@@ -177,7 +149,7 @@ static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
 static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
 {
     GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
-    if(gpio_num < 32) {
+    if (gpio_num < 32) {
         GPIO.enable_w1ts = (0x1 << gpio_num);
     } else {
         GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
@@ -188,14 +160,14 @@ static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
 esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    if(level) {
-        if(gpio_num < 32) {
+    if (level) {
+        if (gpio_num < 32) {
             GPIO.out_w1ts = (1 << gpio_num);
         } else {
             GPIO.out1_w1ts.data = (1 << (gpio_num - 32));
         }
     } else {
-        if(gpio_num < 32) {
+        if (gpio_num < 32) {
             GPIO.out_w1tc = (1 << gpio_num);
         } else {
             GPIO.out1_w1tc.data = (1 << (gpio_num - 32));
@@ -206,7 +178,7 @@ esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
 
 int gpio_get_level(gpio_num_t gpio_num)
 {
-    if(gpio_num < 32) {
+    if (gpio_num < 32) {
         return (GPIO.in >> gpio_num) & 0x1;
     } else {
         return (GPIO.in1.data >> (gpio_num - 32)) & 0x1;
@@ -218,27 +190,27 @@ esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
     GPIO_CHECK(pull <= GPIO_FLOATING, "GPIO pull mode error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
-    switch(pull) {
-        case GPIO_PULLUP_ONLY:
-            REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu);
-            REG_CLR_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pd);
-            break;
-        case GPIO_PULLDOWN_ONLY:
-            REG_CLR_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu);
-            REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pd);
-            break;
-        case GPIO_PULLUP_PULLDOWN:
-            REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu);
-            REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pd);
-            break;
-        case GPIO_FLOATING:
-            REG_CLR_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu);
-            REG_CLR_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pd);
-            break;
-        default:
-            ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u",gpio_num,pull);
-            ret = ESP_ERR_INVALID_ARG;
-            break;
+    switch (pull) {
+    case GPIO_PULLUP_ONLY:
+        gpio_pulldown_dis(gpio_num);
+        gpio_pullup_en(gpio_num);
+        break;
+    case GPIO_PULLDOWN_ONLY:
+        gpio_pulldown_en(gpio_num);
+        gpio_pullup_dis(gpio_num);
+        break;
+    case GPIO_PULLUP_PULLDOWN:
+        gpio_pulldown_en(gpio_num);
+        gpio_pullup_en(gpio_num);
+        break;
+    case GPIO_FLOATING:
+        gpio_pulldown_dis(gpio_num);
+        gpio_pullup_dis(gpio_num);
+        break;
+    default:
+        ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u", gpio_num, pull);
+        ret = ESP_ERR_INVALID_ARG;
+        break;
     }
     return ret;
 }
@@ -246,30 +218,30 @@ esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
 esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
-    if(gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) {
-        ESP_LOGE(GPIO_TAG, "io_num=%d can only be input",gpio_num);
+    if (gpio_num >= 34 && (mode & (GPIO_MODE_DEF_OUTPUT))) {
+        ESP_LOGE(GPIO_TAG, "io_num=%d can only be input", gpio_num);
         return ESP_ERR_INVALID_ARG;
     }
     esp_err_t ret = ESP_OK;
-    if(mode & GPIO_MODE_DEF_INPUT) {
+    if (mode & GPIO_MODE_DEF_INPUT) {
         PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
     } else {
         PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
     }
-    if(mode & GPIO_MODE_DEF_OUTPUT) {
-        if(gpio_num < 32) {
+    if (mode & GPIO_MODE_DEF_OUTPUT) {
+        if (gpio_num < 32) {
             GPIO.enable_w1ts = (0x1 << gpio_num);
         } else {
             GPIO.enable1_w1ts.data = (0x1 << (gpio_num - 32));
         }
     } else {
-        if(gpio_num < 32) {
+        if (gpio_num < 32) {
             GPIO.enable_w1tc = (0x1 << gpio_num);
         } else {
             GPIO.enable1_w1tc.data = (0x1 << (gpio_num - 32));
         }
     }
-    if(mode & GPIO_MODE_DEF_OD) {
+    if (mode & GPIO_MODE_DEF_OD) {
         GPIO.pin[gpio_num].pad_driver = 1;
     } else {
         GPIO.pin[gpio_num].pad_driver = 0;
@@ -287,53 +259,56 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig)
     uint8_t od_en = 0;
     uint8_t pu_en = 0;
     uint8_t pd_en = 0;
-    if(pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
+    if (pGPIOConfig->pin_bit_mask == 0 || pGPIOConfig->pin_bit_mask >= (((uint64_t) 1) << GPIO_PIN_COUNT)) {
         ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error ");
         return ESP_ERR_INVALID_ARG;
     }
-    if((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
+    if ((pGPIOConfig->mode) & (GPIO_MODE_DEF_OUTPUT)) {
         //GPIO 34/35/36/37/38/39 can only be used as input mode;
-        if((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
+        if ((gpio_pin_mask & ( GPIO_SEL_34 | GPIO_SEL_35 | GPIO_SEL_36 | GPIO_SEL_37 | GPIO_SEL_38 | GPIO_SEL_39))) {
             ESP_LOGE(GPIO_TAG, "GPIO34-39 can only be used as input mode");
             return ESP_ERR_INVALID_ARG;
         }
     }
     do {
         io_reg = GPIO_PIN_MUX_REG[io_num];
-        if(((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) {
-            if((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
+        if (((gpio_pin_mask >> io_num) & BIT(0)) && io_reg) {
+            if(RTC_GPIO_IS_VALID_GPIO(io_num)){
+                rtc_gpio_deinit(io_num);
+            }
+            if ((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
                 input_en = 1;
                 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[io_num]);
             } else {
                 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[io_num]);
             }
-            if((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
+            if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
                 od_en = 1;
                 GPIO.pin[io_num].pad_driver = 1; /*0x01 Open-drain */
             } else {
                 GPIO.pin[io_num].pad_driver = 0; /*0x00 Normal gpio output */
             }
-            if((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
+            if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
                 output_en = 1;
                 gpio_output_enable(io_num);
             } else {
                 gpio_output_disable(io_num);
             }
-            if(pGPIOConfig->pull_up_en) {
+            if (pGPIOConfig->pull_up_en) {
                 pu_en = 1;
-                REG_SET_BIT(gpio_pu_pd_desc[io_num].reg, gpio_pu_pd_desc[io_num].pu);
+                gpio_pullup_en(io_num);
             } else {
-                REG_CLR_BIT(gpio_pu_pd_desc[io_num].reg, gpio_pu_pd_desc[io_num].pu);
+                gpio_pullup_dis(io_num);
             }
-            if(pGPIOConfig->pull_down_en) {
+            if (pGPIOConfig->pull_down_en) {
                 pd_en = 1;
-                REG_SET_BIT(gpio_pu_pd_desc[io_num].reg, gpio_pu_pd_desc[io_num].pd);
+                gpio_pulldown_en(io_num);
             } else {
-                REG_CLR_BIT(gpio_pu_pd_desc[io_num].reg, gpio_pu_pd_desc[io_num].pd);
+                gpio_pulldown_dis(io_num);
             }
             ESP_LOGI(GPIO_TAG, "GPIO[%d]| InputEn: %d| OutputEn: %d| OpenDrain: %d| Pullup: %d| Pulldown: %d| Intr:%d ", io_num, input_en, output_en, od_en, pu_en, pd_en, pGPIOConfig->intr_type);
             gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
-            if(pGPIOConfig->intr_type) {
+            if (pGPIOConfig->intr_type) {
                 gpio_intr_enable(io_num);
             } else {
                 gpio_intr_disable(io_num);
@@ -341,7 +316,7 @@ esp_err_t gpio_config(gpio_config_t *pGPIOConfig)
             PIN_FUNC_SELECT(io_reg, PIN_FUNC_GPIO); /*function number 2 is GPIO_FUNC for each pin */
         }
         io_num++;
-    } while(io_num < GPIO_PIN_COUNT);
+    } while (io_num < GPIO_PIN_COUNT);
     return ESP_OK;
 }
 
@@ -360,11 +335,11 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
     GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
     esp_err_t ret = ESP_OK;
-    if((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
+    if ((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
         GPIO.pin[gpio_num].int_type = intr_type;
         GPIO.pin[gpio_num].wakeup_enable = 0x1;
     } else {
-        ESP_LOGE(GPIO_TAG, "GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u",gpio_num);
+        ESP_LOGE(GPIO_TAG, "GPIO wakeup only support Level mode,but edge mode set. gpio_num:%u", gpio_num);
         ret = ESP_ERR_INVALID_ARG;
     }
     return ret;

diff --git a/components/driver/include/driver/adc.h b/components/driver/include/driver/adc.h
new file mode 100644 (file)
index 0000000..56bdbc1
--- /dev/null
+++ b/components/driver/include/driver/adc.h
@@ -0,0 +1,122 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_ADC_H_
+#define _DRIVER_ADC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+
+typedef enum {
+    ADC_ATTEN_0db   = 0,  /*!<The input voltage of ADC will be reduced to about 1/1 */
+    ADC_ATTEN_2_5db = 1,  /*!<The input voltage of ADC will be reduced to about 1/1.34 */
+    ADC_ATTEN_6db   = 2,  /*!<The input voltage of ADC will be reduced to about 1/2 */
+    ADC_ATTEN_11db  = 3,  /*!<The input voltage of ADC will be reduced to about 1/3.6*/
+} adc_atten_t;
+
+typedef enum {
+    ADC_WIDTH_9Bit  = 0, /*!< ADC capture width is 9Bit*/
+    ADC_WIDTH_10Bit = 1, /*!< ADC capture width is 10Bit*/
+    ADC_WIDTH_11Bit = 2, /*!< ADC capture width is 11Bit*/
+    ADC_WIDTH_12Bit = 3, /*!< ADC capture width is 12Bit*/
+} adc_bits_width_t;
+
+typedef enum {
+    ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */
+    ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO37 */
+    ADC1_CHANNEL_2,     /*!< ADC1 channel 2 is GPIO38 */
+    ADC1_CHANNEL_3,     /*!< ADC1 channel 3 is GPIO39 */
+    ADC1_CHANNEL_4,     /*!< ADC1 channel 4 is GPIO32 */
+    ADC1_CHANNEL_5,     /*!< ADC1 channel 5 is GPIO33 */
+    ADC1_CHANNEL_6,     /*!< ADC1 channel 6 is GPIO34 */
+    ADC1_CHANNEL_7,     /*!< ADC1 channel 7 is GPIO35 */
+    ADC1_CHANNEL_MAX,
+} adc1_channel_t;
+
+/**
+ * @brief Configuration ADC1 capture width.
+ *
+ * The configuration is in effect for all channels of ADC1
+ *
+ * @param  width_bit ADC1
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc1_config_width(adc_bits_width_t width_bit);
+
+/**
+ * @brief Configuration ADC1 capture attenuation of channels.
+ *
+ * @param  channel the ADC1 channel
+ * @param  atten attenuation
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten);
+
+/**
+ * @brief ADC1 get the value of the voltage.
+ *
+ * @param  channel the ADC1 channel
+ *
+ * @return
+ *     - -1 Parameter error
+ *     -  Other the value of ADC1 channel
+ */
+int adc1_get_voltage(adc1_channel_t channel);
+
+/**
+ * @brief Hall  Sensor output value.
+ *        @note
+ *        The Hall Sensor uses Channel_0 and Channel_3 of ADC1.
+ *        So, firstly: please configure ADC1 module by calling adc1_config_width before calling hall_sensor_read.
+                 We recommend that the WIDTH ADC1 be configured as 12Bit, because the values of hall_sensor_read are small and almost the same if WIDTH ADC1 is configured as 9Bit, 10Bit or 11Bit.
+ *            secondly: when you use the hall sensor, please do not use Channel_0 and Channel_3 of ADC1 as
+ *                   ADC channels.
+ *
+ * @return the value of hall sensor
+ */
+int hall_sensor_read();
+
+/**
+ *----------EXAMPLE TO USE ADC1------------ *
+ * @code{c}
+ *     adc1_config_width(ADC_WIDTH_12Bit);//config adc1 width
+ *     adc1_config_channel_atten(ADC1_CHANNEL_0,ADC_ATTEN_0db);//config channel0 attenuation
+ *     int val=adc1_get_voltage(ADC1_CHANNEL_0);//get the  val of channel0
+ * @endcode
+ **/
+
+/**
+ *----------EXAMPLE TO USE HALL SENSOR------------ *
+ * @code{c}
+ *     adc1_config_width(ADC_WIDTH_12Bit);//config adc1 width
+ *     int val=hall_sensor_read();
+ * @endcode
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_ADC_H_*/
+

diff --git a/components/driver/include/driver/dac.h b/components/driver/include/driver/dac.h
new file mode 100644 (file)
index 0000000..49758f4
--- /dev/null
+++ b/components/driver/include/driver/dac.h
@@ -0,0 +1,57 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_DAC_H_
+#define _DRIVER_DAC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+
+typedef enum {
+    DAC_CHANNEL_1 = 1,  /*!< DAC channel 1 is GPIO25 */
+    DAC_CHANNEL_2,      /*!< DAC channel 2 is GPIO26 */
+    DAC_CHANNEL_MAX,
+} dac_channel_t;
+
+/**
+ * @brief Set Dac output voltage.
+ *
+ * Dac width is 8bit ,and the voltage max is vdd
+ *
+ * @param channel dac channel
+ * @param dac_value dac output value
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value);
+
+/**
+ *----------EXAMPLE TO USE DAC------------ *
+ * @code{c}
+ * dac_out_voltage(DAC_CHANNEL_1,200);//the dac out voltage ≈ 200*vdd/255
+ * @endcode
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_DAC_H_*/
+

diff --git a/components/driver/include/driver/gpio.h b/components/driver/include/driver/gpio.h
index de34ac4e3590dcfd8881af068c06f11619c69b2b..de7525bd5f19124403b7d8f928fa5d91e3a2b0aa 100644 (file)
--- a/components/driver/include/driver/gpio.h
+++ b/components/driver/include/driver/gpio.h
@@ -117,32 +117,6 @@ extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
 #define GPIO_IS_VALID_GPIO(gpio_num)      ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0))   //to decide whether it is a valid GPIO number
 #define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34))         //to decide whether it can be a valid GPIO number of output mode
 
-/**
- * @brief Pullup/pulldown information for a single GPIO pad
- */
-typedef struct {
-    uint32_t reg;       /*!< Register to modify to enable or disable pullups or pulldowns */
-    uint32_t pu;        /*!< Bit to set or clear in the above register to enable or disable the pullup, respectively */
-    uint32_t pd;        /*!< Bit to set or clear in the above register to enable or disable the pulldown, respectively */
-} gpio_pu_pd_desc_t;
-
-
-/**
- * Per-GPIO pullup/pulldown information
- * On the ESP32, some GPIOs need their pullups and pulldowns enabled and disabled in the RTC 
- * peripheral instead of in the GPIO peripheral. This array documents for every GPIO what bit
- * to set or clear.
- * 
- * This array is non-static, so if you need a very quick way of toggling the pull-up/downs, you can just
- * do e.g. REG_SET_BIT(gpio_pu_pd_desc[gpio_num].reg, gpio_pu_pd_desc[gpio_num].pu); inline.
- * 
- * ToDo: Functions using the contents of this array will do a read/modify/write on GPIO as well as RTC
- * registers. We may need to look into muxes/locks for other code that accesses these RTC registers when we
- * write drivers for the RTC stuff.
- */
-extern const gpio_pu_pd_desc_t gpio_pu_pd_desc[GPIO_PIN_COUNT];
-
-
 typedef enum {
     GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
     GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */

diff --git a/components/driver/include/driver/rtc_io.h b/components/driver/include/driver/rtc_io.h
new file mode 100644 (file)
index 0000000..5196b05
--- /dev/null
+++ b/components/driver/include/driver/rtc_io.h
@@ -0,0 +1,167 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_RTC_GPIO_H_
+#define _DRIVER_RTC_GPIO_H_
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Pullup/pulldown information for a single GPIO pad
+ */
+typedef struct {
+    uint32_t reg;       /*!< Register of Rtc Pad */
+    uint32_t mux;       /*!< Mux seletct the Rtc pad is Digital Pad or Rtc pad */
+    uint32_t func;      /*!< Select Rtc Pad Func */
+    uint32_t ie;        /*!< Input Enable */
+    uint32_t pullup;    /*!< Pullup Enable */
+    uint32_t pulldown;  /*!< PullDown Enable */
+    int rtc_num;        /*!< The Rtc number */
+} rtc_gpio_desc_t;
+
+typedef enum {
+    RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad output           */
+    RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad input          */
+    RTC_GPIO_MODE_INPUT_OUTUT, /*!< Pad pull output + input      */
+    RTC_GPIO_MODE_DISABLED, /*!< Pad (output + input) disable       */
+} rtc_gpio_mode_t;
+
+#define RTC_GPIO_IS_VALID_GPIO(gpio_num)      ((gpio_num < GPIO_PIN_COUNT && rtc_gpio_desc[gpio_num].reg != 0))   //to decide whether it is a valid GPIO number
+
+extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] ;
+
+/*
+ * @brief Init a gpio as rtc gpio
+ *
+ *        when init a pad as analog function,need to call this funciton
+ *
+ * @param  gpio_num gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t rtc_gpio_init(gpio_num_t gpio_num);
+
+/**
+ * @brief Init a gpio as digital gpio
+ *
+ * @param  gpio_num gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num);
+
+/**
+ * @brief Get the rtc io input level
+ *
+ * @param  gpio_num gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - 1 High level
+ *     - 0 Low level
+ */
+uint32_t rtc_gpio_get_level(gpio_num_t gpio_num);
+
+/**
+ * @brief Set the rtc io output level
+ *
+ * @param  gpio_num  GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_12 (12);
+ * @param  level output level;
+ *
+ * @return
+ *     - 1 High level
+ *     - 0 Low level
+ */
+esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level);
+
+/**
+ * @brief    Rtc gpio set direction
+ *
+ * Configure Rtc gpio direction,such as output_only,input_only,output_and_input
+ *
+ * @param  gpio_num  Configure GPIO pins number, it should be GPIO number. If you want to set direction of e.g. GPIO12, gpio_num should be GPIO_NUM_12 (12);
+ * @param  mode GPIO direction
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
+
+/**
+ * @brief  Rtc gpio pullup enable
+ *
+ * If the user needs to configure the GPIO pull ,Please call gpio_set_pull_mode.This function will be called in gpio_set_pull
+ *
+ * @param  gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO12, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - True  the gpio number is Rts pad
+ *     - False the gpio number is Digital pad
+ */
+esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num);
+
+/**
+ * @brief  Rtc gpio pulldown enable
+ *
+ * If the user needs to configure the GPIO pull ,Please call gpio_set_pull_mode.This function will be called in gpio_set_pull
+ *
+ * @param  gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO12, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - True  the gpio number is Rts pad
+ *     - False the gpio number is Digital pad
+ */
+esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num);
+
+/**
+ * @brief  Rtc gpio pullup clear
+ *
+ * If the user needs to configure the GPIO pull ,Please call gpio_set_pull_mode.This function will be called in gpio_set_pull
+ *
+ * @param  gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO12, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - True  the gpio number is Rts pad
+ *     - False the gpio number is Digital pad
+ */
+esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num);
+
+/**
+ * @brief  Rtc gpio pulldown clear
+ *
+ * If the user needs to configure the GPIO pull ,Please call gpio_set_pull_mode.This function will be called in gpio_set_pull
+ *
+ * @param  gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO12, gpio_num should be GPIO_NUM_12 (12);
+ *
+ * @return
+ *     - True  the gpio number is Rts pad
+ *     - False the gpio number is Digital pad
+ */
+esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

diff --git a/components/driver/include/driver/touch_pad.h b/components/driver/include/driver/touch_pad.h
new file mode 100644 (file)
index 0000000..b8dc6e7
--- /dev/null
+++ b/components/driver/include/driver/touch_pad.h
@@ -0,0 +1,165 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_TOUCH_PAD_H_
+#define _DRIVER_TOUCH_PAD_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "esp_intr.h"
+#include "esp_err.h"
+#define TOUCH_PAD_SLEEP_CYCLE_CONFIG   (0x1000)//The Time is 150Khz,the Max value is 0xffff
+#define TOUCH_PAD_MEASURE_CYCLE_CONFIG (0xffff)//The Time is 8Mhz,the Max value is 0xffff
+typedef enum {
+    TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4 */
+    TOUCH_PAD_NUM1,    /*!< Touch pad channel 0 is GPIO0 */
+    TOUCH_PAD_NUM2,    /*!< Touch pad channel 0 is GPIO2 */
+    TOUCH_PAD_NUM3,    /*!< Touch pad channel 0 is GPIO15 */
+    TOUCH_PAD_NUM4,    /*!< Touch pad channel 0 is GPIO13 */
+    TOUCH_PAD_NUM5,    /*!< Touch pad channel 0 is GPIO12 */
+    TOUCH_PAD_NUM6,    /*!< Touch pad channel 0 is GPIO14 */
+    TOUCH_PAD_NUM7,    /*!< Touch pad channel 0 is GPIO27*/
+    TOUCH_PAD_NUM8,    /*!< Touch pad channel 0 is GPIO33*/
+    TOUCH_PAD_NUM9,    /*!< Touch pad channel 0 is GPIO32*/
+    TOUCH_PAD_MAX,
+} touch_pad_t;
+/**
+ * @brief       Initialize touch module.
+ *
+ *This function int touch pad module ,enable touch module
+ *
+ * @return    None
+ *
+ */
+void touch_pad_init();
+
+/**
+ * @brief       Configure touch pad interrupt threshold.
+ *
+ *
+ * @param[in]  touch_num  : config touch num
+ *
+ * @param[in]  threshold : interrupt threshold  ,When the touch_pad_register less than threshold,
+ *                         will trigger the touch interrupt.User can use touch_pad_read function
+ *                         to determine the threshold.
+ *
+ * @return    - ESP_OK Success
+ *            - ESP_ERR_INVALID_ARG Touch pad error
+ *
+ */
+esp_err_t touch_pad_config(touch_pad_t touch_num, uint16_t threshold);
+
+/**
+ * @brief       get touch pad touch_pad_register counter.
+ *
+ *User can use this function to determine the the interrupt threshold .When you do not touch  the
+ *pad ,read the touch_pad_read number(NumNotTouch) by the touch_pad_register.When you touch the pad ,read the touch_pad_register
+ *number(NumTouch) by the touch_pad_read.Normal NumNotTouch>NumTouch,so you can select a interrupt threshold.
+ *
+ * @param[in]  touch_num    : touch num
+ * @param[out]  touch_value : touch output value
+ *
+ *  @return   - ESP_OK Success
+ *            - ESP_ERR_INVALID_ARG Touch pad error
+ *
+ */
+esp_err_t touch_pad_read(touch_pad_t touch_num, uint16_t * touch_value);
+
+/**
+ * @brief   register TouchPad interrupt handler, the handler is an ISR.
+ *          The handler will be attached to the same CPU core that this function is running on.
+ *          @note
+ *          Users should know that which CPU is running and then pick a INUM that is not used by system.
+ *          We can find the information of INUM and interrupt level in soc.h.
+ *
+ * @param  touch_intr_num  Touch interrupt number,check the info in soc.h, and please see the core-isa.h for more details
+ * @param  fn  Interrupt handler function.
+ *
+ *         @note
+ *         Note that the handler function MUST be defined with attribution of "IRAM_ATTR".
+ *
+ * @param  arg  Parameter for handler function
+ *
+ * @return
+ *     - ESP_OK Success ;
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t touch_pad_isr_handler_register(uint32_t touch_intr_num, void(*fn)(void*), void *arg);
+
+
+/**
+ * ***************        ATTENTION       ********************/
+/**
+ *@attention
+*Touch button is through the body's capacitive characteristics, 
+*there is a charge discharge circuit inside the. When the hands touch, 
+*the charge and discharge time will be slow.
+*Because of the different hardware, each pad needs to be calibrated at the factory.
+*We use touch_pad_read to determine factory parament.
+*/
+/**
+ *----------EXAMPLE TO CONIFGURE GPIO AS OUTPUT ------------ *
+ * @code{c}
+ *  touch_pad_init();                            
+ *  void taskA(void* arg)
+ *  {
+ *      for(;;){
+ *          vtaskDelay(20/portTICK_PERIOD_MS);
+ *          ets_printf("tocuch pad value %u\n",touch_pad_read(0));//Take the touched status and untouched status value
+ *      } 
+ *  }
+ * @endcode
+ **/
+/**
+ *----------EXAMPLE TO SET ISR HANDLER ----------------------
+ * @code{c}
+ * //the first parameter is INUM, you can pick one form interrupt level 1/2 which is not used by the system.
+ * touch_pad_isr_handler_register(19,rtc_intr,NULL);    //hook the isr handler for TouchPad interrupt
+ * @endcode
+ * @note
+ *     1. user should arrange the INUMs that used, better not to use a same INUM for different interrupt.
+ *     2. do not pick the INUM that already occupied by the system.
+ *     3. refer to soc.h to check which INUMs that can be used.
+ */
+/**
+ *----------EXAMPLE TO USE TOUCH_PAD------------ *
+ * @code{c}
+ *   touch_pad_init();//only init one time
+ *   touch_pad_config(0,300);//set the intr threshold,use touch_pad_read to determine this threshold 
+ *   touch_pad_isr_handler_register(19,rtc_intr,NULL)
+ *   #include "esp_attr.h"
+ *   void IRAM_ATTR rtc_intr(void * arg)
+ *   {
+ *       uint32_t pad_intr = READ_PERI_REG(SARADC_SAR_TOUCH_CTRL2_REG) & 0x3ff;
+ *       uint8_t i = 0;
+ *       uint32_t rtc_intr = READ_PERI_REG(RTC_CNTL_INT_ST_REG);
+ *       WRITE_PERI_REG(RTC_CNTL_INT_CLR_REG, rtc_intr);
+ *       SET_PERI_REG_MASK(SARADC_SAR_TOUCH_CTRL2_REG, SARADC_TOUCH_MEAS_EN_CLR);
+ *       if (rtc_intr & RTC_CNTL_TOUCH_INT_ST) {
+ *           for (i = 0; i < TOUCH_PAD_MAX; ++i) {
+ *               if ((pad_intr >> i) & 0x01) {
+ *                   ets_printf("touch pad intr %u\n",i);
+ *               }
+ *           }
+ *       }
+ *  }
+ * @endcode
+ **/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif/*_DRIVER_TOUCH_PAD_H_*/
+

diff --git a/components/driver/rtc_module.c b/components/driver/rtc_module.c
new file mode 100644 (file)
index 0000000..5da738b
--- /dev/null
+++ b/components/driver/rtc_module.c
@@ -0,0 +1,699 @@
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <esp_types.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include "rom/ets_sys.h"
+#include "esp_log.h"
+#include "soc/rtc_io_reg.h"
+#include "soc/sens_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "rtc_io.h"
+#include "touch_pad.h"
+#include "adc.h"
+#include "dac.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/xtensa_api.h"
+
+static const char *RTC_MODULE_TAG = "RTC_MODULE";
+
+#define RTC_MODULE_CHECK(a, str, ret_val) if (!(a)) {                                \
+    ESP_LOGE(RTC_MODULE_TAG,"%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \
+    return (ret_val);                                                              \
+}
+
+#define ADC1_CHECK_FUNCTION_RET(fun_ret) if(fun_ret!=ESP_OK){\
+    ESP_LOGE(RTC_MODULE_TAG,"%s:%d\n",__FUNCTION__,__LINE__);\
+    return ESP_FAIL;\
+}
+
+portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;
+
+//Reg,Mux,Fun,IE,Up,Down,Rtc_number
+const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT] = {
+    {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, 11}, //0
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //1
+    {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, 12}, //2
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //3
+    {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, 10}, //4
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //5
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //6
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //7
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //8
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //9
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //10
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //11
+    {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, 15}, //12
+    {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, 14}, //13
+    {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, 16}, //14
+    {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, 13}, //15
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //16
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //17
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //18
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //19
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //20
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //21
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //22
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //23
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //24
+    {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, 6},                           //25
+    {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, 7},                           //26
+    {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, 17}, //27
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //28
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //29
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //30
+    {0, 0, 0, 0, 0, 0, -1},                                                                                                                                            //31
+    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, 9},                            //32
+    {RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, 8},                            //33
+    {RTC_IO_ADC_PAD_REG, RTC_IO_ADC1_MUX_SEL_M, RTC_IO_ADC1_FUN_SEL_S, RTC_IO_ADC1_FUN_IE_M, 0, 0, 4},                                                                //34
+    {RTC_IO_ADC_PAD_REG, RTC_IO_ADC2_MUX_SEL_M, RTC_IO_ADC2_FUN_SEL_S, RTC_IO_ADC2_FUN_IE_M, 0, 0, 5},                                                                //35
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE1_MUX_SEL_M, RTC_IO_SENSE1_FUN_SEL_S, RTC_IO_SENSE1_FUN_IE_M, 0, 0, 0},                                                      //36
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE2_MUX_SEL_M, RTC_IO_SENSE2_FUN_SEL_S, RTC_IO_SENSE2_FUN_IE_M, 0, 0, 1},                                                      //37
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE3_MUX_SEL_M, RTC_IO_SENSE3_FUN_SEL_S, RTC_IO_SENSE3_FUN_IE_M, 0, 0, 2},                                                       //38
+    {RTC_IO_SENSOR_PADS_REG, RTC_IO_SENSE4_MUX_SEL_M, RTC_IO_SENSE4_FUN_SEL_S, RTC_IO_SENSE4_FUN_IE_M, 0, 0, 3},                                                      //39
+};
+
+/*---------------------------------------------------------------
+                        RTC IO
+---------------------------------------------------------------*/
+esp_err_t rtc_gpio_init(gpio_num_t gpio_num)
+{
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
+    SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux));
+    //0:RTC FUNCIOTN 1,2,3:Reserved
+    SET_PERI_REG_BITS(rtc_gpio_desc[gpio_num].reg, RTC_IO_TOUCH_PAD1_FUN_SEL_V, 0x0, rtc_gpio_desc[gpio_num].func);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
+{
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    //Select Gpio as Digital Gpio
+    CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, (rtc_gpio_desc[gpio_num].mux));
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+static esp_err_t rtc_gpio_output_enable(gpio_num_t gpio_num)
+{
+    int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
+    RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S)));
+    CLEAR_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S)));
+
+    return ESP_OK;
+}
+
+static esp_err_t rtc_gpio_output_disable(gpio_num_t gpio_num)
+{
+    int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
+    RTC_MODULE_CHECK(rtc_gpio_num != -1, "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    CLEAR_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_ENABLE_W1TS_S)));
+    SET_PERI_REG_MASK(RTC_GPIO_ENABLE_W1TC_REG, (1 << ( rtc_gpio_num + RTC_GPIO_ENABLE_W1TC_S)));
+
+    return ESP_OK;
+}
+
+static esp_err_t rtc_gpio_input_enable(gpio_num_t gpio_num)
+{
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+static esp_err_t rtc_gpio_input_disable(gpio_num_t gpio_num)
+{
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].ie);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level)
+{
+    int rtc_gpio_num = rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;;
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+
+    if (level) {
+        WRITE_PERI_REG(RTC_GPIO_OUT_W1TS_REG, (1 << (rtc_gpio_num + RTC_GPIO_OUT_DATA_W1TS_S)));
+    } else {
+        WRITE_PERI_REG(RTC_GPIO_OUT_W1TC_REG, (1 << (rtc_gpio_num + RTC_GPIO_OUT_DATA_W1TC_S)));
+    }
+
+    return ESP_OK;
+}
+
+uint32_t rtc_gpio_get_level(gpio_num_t gpio_num)
+{
+    uint32_t level = 0;
+    int rtc_gpio_num = rtc_gpio_desc[gpio_num].rtc_num;
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+
+    portENTER_CRITICAL(&rtc_spinlock);
+    level = READ_PERI_REG(RTC_GPIO_IN_REG);
+    portEXIT_CRITICAL(&rtc_spinlock);
+    return ((level >> (RTC_GPIO_IN_NEXT_S + rtc_gpio_num)) & 0x01);
+}
+
+esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode)
+{
+    RTC_MODULE_CHECK(RTC_GPIO_IS_VALID_GPIO(gpio_num), "RTC_GPIO number error", ESP_ERR_INVALID_ARG);
+
+    switch (mode) {
+    case RTC_GPIO_MODE_INPUT_ONLY:
+        rtc_gpio_output_disable(gpio_num);
+        rtc_gpio_input_enable(gpio_num);
+        break;
+    case RTC_GPIO_MODE_OUTPUT_ONLY:
+        rtc_gpio_output_enable(gpio_num);
+        rtc_gpio_input_disable(gpio_num);
+        break;
+    case RTC_GPIO_MODE_INPUT_OUTUT:
+        rtc_gpio_output_enable(gpio_num);
+        rtc_gpio_input_enable(gpio_num);
+        break;
+    case RTC_GPIO_MODE_DISABLED:
+        rtc_gpio_output_disable(gpio_num);
+        rtc_gpio_input_disable(gpio_num);
+        break;
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num)
+{
+    //this is a digital pad
+    if (rtc_gpio_desc[gpio_num].pullup == 0) {
+        return ESP_FAIL;
+    }
+
+    //this is a rtc pad
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num)
+{
+    //this is a digital pad
+    if (rtc_gpio_desc[gpio_num].pulldown == 0) {
+        return ESP_FAIL;
+    }
+
+    //this is a rtc pad
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num)
+{
+    //this is a digital pad
+    if ( rtc_gpio_desc[gpio_num].pullup == 0 ) {
+        return ESP_FAIL;
+    }
+
+    //this is a rtc pad
+    portENTER_CRITICAL(&rtc_spinlock);
+    CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pullup);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num)
+{
+    //this is a digital pad
+    if (rtc_gpio_desc[gpio_num].pulldown == 0) {
+        return ESP_FAIL;
+    }
+
+    //this is a rtc pad
+    portENTER_CRITICAL(&rtc_spinlock);
+    CLEAR_PERI_REG_MASK(rtc_gpio_desc[gpio_num].reg, rtc_gpio_desc[gpio_num].pulldown);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+/*---------------------------------------------------------------
+                    Touch Pad
+---------------------------------------------------------------*/
+esp_err_t touch_pad_isr_handler_register(uint32_t touch_intr_num, void(*fn)(void *), void *arg)
+{
+    RTC_MODULE_CHECK(fn, "Touch_Pad ISR null", ESP_ERR_INVALID_ARG);
+    ESP_INTR_DISABLE(touch_intr_num);
+    intr_matrix_set(xPortGetCoreID(), ETS_RTC_CORE_INTR_SOURCE, touch_intr_num);
+    xt_set_interrupt_handler(touch_intr_num, fn, arg);
+    ESP_INTR_ENABLE(touch_intr_num);
+
+    return ESP_OK;
+}
+
+static esp_err_t touch_pad_get_io_num(touch_pad_t touch_num, gpio_num_t *gpio_num)
+{
+    switch (touch_num) {
+    case TOUCH_PAD_NUM0:
+        *gpio_num = 4;
+        break;
+    case TOUCH_PAD_NUM1:
+        *gpio_num = 0;
+        break;
+    case TOUCH_PAD_NUM2:
+        *gpio_num = 2;
+        break;
+    case TOUCH_PAD_NUM3:
+        *gpio_num = 15;
+        break;
+    case TOUCH_PAD_NUM4:
+        *gpio_num = 13;
+        break;
+    case TOUCH_PAD_NUM5:
+        *gpio_num = 12;
+        break;
+    case TOUCH_PAD_NUM6:
+        *gpio_num = 14;
+        break;
+    case TOUCH_PAD_NUM7:
+        *gpio_num = 27;
+        break;
+    case TOUCH_PAD_NUM8:
+        *gpio_num = 33;
+        break;
+    case TOUCH_PAD_NUM9:
+        *gpio_num = 32;
+        break;
+    default:
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    return ESP_OK;
+}
+
+static esp_err_t touch_pad_init_config(uint16_t sleep_cycle, uint16_t sample_cycle_num)
+{
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS, 1, RTC_IO_TOUCH_XPD_BIAS_S);
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_EN_CLR);
+    //clear touch enable
+    WRITE_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG, 0x0);
+    //enable Rtc Touch pad Timer
+    SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_TOUCH_SLP_TIMER_EN);
+    //config pad module sleep time and sample num
+    //Touch pad SleepCycle Time = 150Khz
+    SET_PERI_REG_BITS(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_SLEEP_CYCLES, sleep_cycle, SENS_TOUCH_SLEEP_CYCLES_S);//150kHZ
+    //Touch Pad Measure Time= 8Mhz
+    SET_PERI_REG_BITS(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_MEAS_DELAY, sample_cycle_num, SENS_TOUCH_MEAS_DELAY_S); //8Mhz
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+void touch_pad_init()
+{
+    touch_pad_init_config(TOUCH_PAD_SLEEP_CYCLE_CONFIG, TOUCH_PAD_MEASURE_CYCLE_CONFIG);
+}
+
+static void touch_pad_counter_init(touch_pad_t touch_num)
+{
+    portENTER_CRITICAL(&rtc_spinlock);
+    //Enable Tie,Init Level(Counter)
+    SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + touch_num * 4, RTC_IO_TOUCH_PAD0_TIE_OPT_M);
+    //Touch Set Slop(Counter)
+    SET_PERI_REG_BITS(RTC_IO_TOUCH_PAD0_REG + touch_num * 4, RTC_IO_TOUCH_PAD0_DAC_V, 7, RTC_IO_TOUCH_PAD0_DAC_S);
+    //Enable Touch Pad IO
+    SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + touch_num * 4, RTC_IO_TOUCH_PAD0_START_M);
+    portEXIT_CRITICAL(&rtc_spinlock);
+}
+
+static void touch_pad_power_on(touch_pad_t touch_num)
+{
+    portENTER_CRITICAL(&rtc_spinlock);
+    //Enable Touch Pad Power on
+    SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + touch_num * 4, RTC_IO_TOUCH_PAD0_XPD_M);
+    portEXIT_CRITICAL(&rtc_spinlock);
+}
+
+static void toch_pad_io_init(touch_pad_t touch_num)
+{
+    gpio_num_t gpio_num = GPIO_NUM_0;
+    touch_pad_get_io_num(touch_num, &gpio_num);
+    rtc_gpio_init(gpio_num);
+    rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
+    rtc_gpio_pulldown_dis(gpio_num);
+    rtc_gpio_pullup_dis(gpio_num);
+}
+
+static esp_err_t touch_start(touch_pad_t touch_num)
+{
+    RTC_MODULE_CHECK(touch_num < TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+
+    //Enable Digital rtc control :work mode and out mode
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_ENABLE_REG, (1 << (touch_num + SENS_TOUCH_PAD_WORKEN_S)) | \
+                      (1 << (touch_num + SENS_TOUCH_PAD_OUTEN2_S)) | \
+                      (1 << (touch_num + SENS_TOUCH_PAD_OUTEN1_S)));
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+static esp_err_t touch_stop(touch_pad_t touch_num)
+{
+    RTC_MODULE_CHECK(touch_num < TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+
+    //Disable Digital rtc control :work mode and out mode
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_ENABLE_REG, (1 << (touch_num + SENS_TOUCH_PAD_WORKEN_S)) | \
+                        (1 << (touch_num + SENS_TOUCH_PAD_OUTEN2_S)) | \
+                        (1 << (touch_num + SENS_TOUCH_PAD_OUTEN1_S)));
+
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t touch_pad_config(touch_pad_t touch_num, uint16_t threshold)
+{
+    RTC_MODULE_CHECK(touch_num < TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    //clear touch force ,select the Touch mode is Timer
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_EN_M);
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FORCE_M);
+    //set threshold
+    uint8_t shift;
+    shift = (touch_num & 1) ? SENS_TOUCH_OUT_TH1_S : SENS_TOUCH_OUT_TH0_S;
+    SET_PERI_REG_BITS((SENS_SAR_TOUCH_THRES1_REG + (touch_num / 2) * 4), SENS_TOUCH_OUT_TH0, threshold, shift);
+    //When touch value < threshold ,the Intr will give
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_OUT_SEL);
+    //Intr will give ,when SET0 < threshold
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_OUT_1EN);
+    //Enable Rtc Touch Module Intr,the Interrupt need Rtc out  Enable
+    SET_PERI_REG_MASK(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_INT_ENA);
+    portEXIT_CRITICAL(&rtc_spinlock);
+    touch_pad_power_on(touch_num);
+    toch_pad_io_init(touch_num);
+    touch_pad_counter_init(touch_num);
+    touch_start(touch_num);
+
+    return ESP_OK;
+}
+
+esp_err_t touch_pad_read(touch_pad_t touch_num, uint16_t *touch_value)
+{
+    RTC_MODULE_CHECK(touch_num < TOUCH_PAD_MAX, "Touch_Pad Num Err", ESP_ERR_INVALID_ARG);
+    RTC_MODULE_CHECK(touch_value!=NULL, "touch_value", ESP_ERR_INVALID_ARG);
+    uint32_t v0 = READ_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_ENABLE_REG, (1 << (touch_num)));
+    //Disable Intr
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_ENABLE_REG, (1 << (touch_num + SENS_TOUCH_PAD_OUTEN2_S)) | \
+                        ((1 << (touch_num + SENS_TOUCH_PAD_OUTEN1_S))));
+    toch_pad_io_init(touch_num);
+    touch_pad_counter_init(touch_num);
+    touch_pad_power_on(touch_num);
+    //force oneTime test start
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_EN_M);
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FORCE_M);
+    SET_PERI_REG_BITS(SENS_SAR_TOUCH_CTRL1_REG, SENS_TOUCH_XPD_WAIT, 10, SENS_TOUCH_XPD_WAIT_S);
+    while (GET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_MEAS_DONE) == 0) {};
+    uint8_t shift = (touch_num & 1) ? SENS_TOUCH_MEAS_OUT1_S : SENS_TOUCH_MEAS_OUT0_S;
+    *touch_value = READ_PERI_REG(SENS_SAR_TOUCH_OUT1_REG + (touch_num / 2) * 4) >> shift;
+    WRITE_PERI_REG(SENS_SAR_TOUCH_ENABLE_REG, v0);
+    //force oneTime test end
+    //clear touch force ,select the Touch mode is Timer
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_EN_M);
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL2_REG, SENS_TOUCH_START_FORCE_M);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+/*---------------------------------------------------------------
+                    ADC
+---------------------------------------------------------------*/
+static esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
+{
+    RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
+
+    switch (channel) {
+    case ADC1_CHANNEL_0:
+        *gpio_num = 36;
+        break;
+    case ADC1_CHANNEL_1:
+        *gpio_num = 37;
+        break;
+    case ADC1_CHANNEL_2:
+        *gpio_num = 38;
+        break;
+    case ADC1_CHANNEL_3:
+        *gpio_num = 39;
+        break;
+    case ADC1_CHANNEL_4:
+        *gpio_num = 32;
+        break;
+    case ADC1_CHANNEL_5:
+        *gpio_num = 33;
+        break;
+    case ADC1_CHANNEL_6:
+        *gpio_num = 34;
+        break;
+    case ADC1_CHANNEL_7:
+        *gpio_num = 35;
+        break;
+    default:
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    return ESP_OK;
+}
+
+static esp_err_t adc1_pad_init(adc1_channel_t channel)
+{
+    gpio_num_t gpio_num = 0;
+    ADC1_CHECK_FUNCTION_RET(adc1_pad_get_io_num(channel, &gpio_num));
+    ADC1_CHECK_FUNCTION_RET(rtc_gpio_init(gpio_num));
+    ADC1_CHECK_FUNCTION_RET(rtc_gpio_output_disable(gpio_num));
+    ADC1_CHECK_FUNCTION_RET(rtc_gpio_input_disable(gpio_num));
+    ADC1_CHECK_FUNCTION_RET(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
+
+    return ESP_OK;
+}
+
+esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
+{
+    RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
+    RTC_MODULE_CHECK(atten <= ADC_ATTEN_11db, "ADC Atten Err", ESP_ERR_INVALID_ARG);
+    adc1_pad_init(channel);
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_BITS(SENS_SAR_ATTEN1_REG, 3, atten, (channel * 2)); //SAR1_atten
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+esp_err_t adc1_config_width(adc_bits_width_t width_bit)
+{
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH_V, width_bit, SENS_SAR1_BIT_WIDTH_S);  //SAR2_BIT_WIDTH[1:0]=0x3, SAR1_BIT_WIDTH[1:0]=0x3
+    //Invert the adc value,the Output value is invert
+    SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DATA_INV);
+    //Set The adc sample width,invert adc value,must
+    SET_PERI_REG_BITS(SENS_SAR_READ_CTRL_REG, SENS_SAR1_SAMPLE_BIT_V, width_bit, SENS_SAR1_SAMPLE_BIT_S); //digital sar1_bit_width[1:0]=3
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return ESP_OK;
+}
+
+int adc1_get_voltage(adc1_channel_t channel)
+{
+    uint16_t adc_value;
+    uint8_t atten = 0;
+
+    RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    //Adc Controler is Rtc module,not ulp coprocessor
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_START1_REG, 1, 1, SENS_MEAS1_START_FORCE_S); //force pad mux and force start
+    //Bit1=0:Fsm  Bit1=1(Bit0=0:PownDown Bit10=1:Powerup)
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); //force XPD_SAR=0, use XPD_FSM
+    //Disable Amp Bit1=0:Fsm  Bit1=1(Bit0=0:PownDown Bit10=1:Powerup)
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_AMP, 0x2, SENS_FORCE_XPD_AMP_S); //force XPD_AMP=0
+    //Open the ADC1 Data port Not ulp coprocessor
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_START1_REG, 1, 1, SENS_SAR1_EN_PAD_FORCE_S); //open the ADC1 data port
+    //Select channel
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_START1_REG, SENS_SAR1_EN_PAD, (1 << channel), SENS_SAR1_EN_PAD_S); //pad enable
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_CTRL_REG, 0xfff, 0x0, SENS_AMP_RST_FB_FSM_S);  //[11:8]:short ref ground, [7:4]:short ref, [3:0]:rst fb
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT1_REG, SENS_SAR_AMP_WAIT1, 0x1, SENS_SAR_AMP_WAIT1_S);
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT1_REG, SENS_SAR_AMP_WAIT2, 0x1, SENS_SAR_AMP_WAIT2_S);
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_SAR_AMP_WAIT3, 0x1, SENS_SAR_AMP_WAIT3_S);
+    while (GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR1_REG, 0x7, SENS_MEAS_STATUS_S) != 0); //wait det_fsm==0
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_START1_REG, 1, 0, SENS_MEAS1_START_SAR_S); //start force 0
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_START1_REG, 1, 1, SENS_MEAS1_START_SAR_S); //start force 1
+    while (GET_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_DONE_SAR) == 0) {}; //read done
+    adc_value = GET_PERI_REG_BITS2(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_DATA_SAR, SENS_MEAS1_DATA_SAR_S);
+    portEXIT_CRITICAL(&rtc_spinlock);
+
+    return adc_value;
+}
+
+/*---------------------------------------------------------------
+                    DAC
+---------------------------------------------------------------*/
+static esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num)
+{
+    RTC_MODULE_CHECK(channel < DAC_CHANNEL_MAX, "DAC Channel Err", ESP_ERR_INVALID_ARG);
+
+    switch (channel) {
+    case DAC_CHANNEL_1:
+        *gpio_num = 25;
+        break;
+    case DAC_CHANNEL_2:
+        *gpio_num = 26;
+        break;
+    default:
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    return ESP_OK;
+}
+
+static esp_err_t dac_rtc_pad_init(dac_channel_t channel)
+{
+    RTC_MODULE_CHECK(channel < DAC_CHANNEL_MAX, "DAC Channel Err", ESP_ERR_INVALID_ARG);
+    gpio_num_t gpio_num = 0;
+    dac_pad_get_io_num(channel, &gpio_num);
+    rtc_gpio_init(gpio_num);
+    rtc_gpio_output_disable(gpio_num);
+    rtc_gpio_input_disable(gpio_num);
+    rtc_gpio_pullup_dis(gpio_num);
+    rtc_gpio_pulldown_dis(gpio_num);
+
+    return ESP_OK;
+}
+
+static esp_err_t dac_out_enable(dac_channel_t channel)
+{
+    if (channel == DAC_CHANNEL_1) {
+        portENTER_CRITICAL(&rtc_spinlock);
+        SET_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE);
+        portEXIT_CRITICAL(&rtc_spinlock);
+    } else if (channel == DAC_CHANNEL_2) {
+        portENTER_CRITICAL(&rtc_spinlock);
+        SET_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE);
+        portEXIT_CRITICAL(&rtc_spinlock);
+    } else {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    return ESP_OK;
+}
+
+static esp_err_t  dac_out_disable(dac_channel_t channel)
+{
+    if (channel == DAC_CHANNEL_1) {
+        portENTER_CRITICAL(&rtc_spinlock);
+        CLEAR_PERI_REG_MASK(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_XPD_DAC | RTC_IO_PDAC1_DAC_XPD_FORCE);
+        portEXIT_CRITICAL(&rtc_spinlock);
+    } else if (channel == DAC_CHANNEL_2) {
+        portENTER_CRITICAL(&rtc_spinlock);
+        CLEAR_PERI_REG_MASK(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_XPD_DAC | RTC_IO_PDAC2_DAC_XPD_FORCE);
+        portEXIT_CRITICAL(&rtc_spinlock);
+    } else {
+        return ESP_ERR_INVALID_ARG;
+    }
+
+    return ESP_OK;
+}
+
+esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value)
+{
+    RTC_MODULE_CHECK(channel < DAC_CHANNEL_MAX, "DAC Channel Err", ESP_ERR_INVALID_ARG);
+    portENTER_CRITICAL(&rtc_spinlock);
+    //Disable Tone
+    CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL1_REG, SENS_SW_TONE_EN);
+
+    //Disable Channel Tone
+    if (channel == DAC_CHANNEL_1) {
+        CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1_M);
+    } else if (channel == DAC_CHANNEL_2) {
+        CLEAR_PERI_REG_MASK(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2_M);
+    }
+
+    //Set the Dac value
+    if (channel == DAC_CHANNEL_1) {
+        SET_PERI_REG_BITS(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC, dac_value, RTC_IO_PDAC1_DAC_S);   //dac_output
+    } else if (channel == DAC_CHANNEL_2) {
+        SET_PERI_REG_BITS(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC, dac_value, RTC_IO_PDAC2_DAC_S);   //dac_output
+    }
+
+    portEXIT_CRITICAL(&rtc_spinlock);
+    //dac pad init
+    dac_rtc_pad_init(channel);
+    dac_out_enable(channel);
+
+    return ESP_OK;
+}
+
+/*---------------------------------------------------------------
+                        HALL SENSOR
+---------------------------------------------------------------*/
+static int hall_sensor_get_value()    //hall sensor without LNA
+{
+    int Sens_Vp0;
+    int Sens_Vn0;
+    int Sens_Vp1;
+    int Sens_Vn1;
+    int hall_value;
+
+    portENTER_CRITICAL(&rtc_spinlock);
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_XPD_HALL_FORCE_M);     // hall sens force enable
+    SET_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_XPD_HALL);      // xpd hall
+    SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_HALL_PHASE_FORCE_M);   // phase force
+    CLEAR_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_HALL_PHASE);      // hall phase
+    Sens_Vp0 = adc1_get_voltage(ADC1_CHANNEL_0);
+    Sens_Vn0 = adc1_get_voltage(ADC1_CHANNEL_3);
+    SET_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_HALL_PHASE);
+    Sens_Vp1 = adc1_get_voltage(ADC1_CHANNEL_0);
+    Sens_Vn1 = adc1_get_voltage(ADC1_CHANNEL_3);
+    SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_XPD_HALL_FORCE);
+    CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_HALL_PHASE_FORCE);
+    portEXIT_CRITICAL(&rtc_spinlock);
+    hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
+
+    return hall_value;
+}
+
+int hall_sensor_read()
+{
+    adc1_pad_init(ADC1_CHANNEL_0);
+    adc1_pad_init(ADC1_CHANNEL_3);
+    adc1_config_channel_atten(ADC1_CHANNEL_0, ADC_ATTEN_0db);
+    adc1_config_channel_atten(ADC1_CHANNEL_3, ADC_ATTEN_0db);
+    return hall_sensor_get_value();
+}

diff --git a/components/esp32/include/soc/rtc_io_reg.h b/components/esp32/include/soc/rtc_io_reg.h
index 086e8b7674aa44b5966cfbd12cd539417fd2c792..345bb8045c1f74abcc26feea11bc62dc0061974f 100644 (file)
--- a/components/esp32/include/soc/rtc_io_reg.h
+++ b/components/esp32/include/soc/rtc_io_reg.h
@@ -1,1951 +1,1951 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _SOC_RTC_IO_REG_H_
-#define _SOC_RTC_IO_REG_H_
-
-
-#include "soc.h"
-#define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)
-/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output value*/
-#define RTC_GPIO_OUT_DATA  0x0003FFFF
-#define RTC_GPIO_OUT_DATA_M  ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))
-#define RTC_GPIO_OUT_DATA_V  0x3FFFF
-#define RTC_GPIO_OUT_DATA_S  14
-
-#define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x4)
-/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output value write 1 to set*/
-#define RTC_GPIO_OUT_DATA_W1TS  0x0003FFFF
-#define RTC_GPIO_OUT_DATA_W1TS_M  ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
-#define RTC_GPIO_OUT_DATA_W1TS_V  0x3FFFF
-#define RTC_GPIO_OUT_DATA_W1TS_S  14
-
-#define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x8)
-/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output value write 1 to clear*/
-#define RTC_GPIO_OUT_DATA_W1TC  0x0003FFFF
-#define RTC_GPIO_OUT_DATA_W1TC_M  ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))
-#define RTC_GPIO_OUT_DATA_W1TC_V  0x3FFFF
-#define RTC_GPIO_OUT_DATA_W1TC_S  14
-
-#define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0xc)
-/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output enable*/
-#define RTC_GPIO_ENABLE  0x0003FFFF
-#define RTC_GPIO_ENABLE_M  ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))
-#define RTC_GPIO_ENABLE_V  0x3FFFF
-#define RTC_GPIO_ENABLE_S  14
-
-#define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)
-/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output enable write 1 to set*/
-#define RTC_GPIO_ENABLE_W1TS  0x0003FFFF
-#define RTC_GPIO_ENABLE_W1TS_M  ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
-#define RTC_GPIO_ENABLE_W1TS_V  0x3FFFF
-#define RTC_GPIO_ENABLE_W1TS_S  14
-
-#define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x14)
-/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 output enable write 1 to clear*/
-#define RTC_GPIO_ENABLE_W1TC  0x0003FFFF
-#define RTC_GPIO_ENABLE_W1TC_M  ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))
-#define RTC_GPIO_ENABLE_W1TC_V  0x3FFFF
-#define RTC_GPIO_ENABLE_W1TC_S  14
-
-#define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x18)
-/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 interrupt status*/
-#define RTC_GPIO_STATUS_INT  0x0003FFFF
-#define RTC_GPIO_STATUS_INT_M  ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))
-#define RTC_GPIO_STATUS_INT_V  0x3FFFF
-#define RTC_GPIO_STATUS_INT_S  14
-
-#define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x1c)
-/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 interrupt status write 1 to set*/
-#define RTC_GPIO_STATUS_INT_W1TS  0x0003FFFF
-#define RTC_GPIO_STATUS_INT_W1TS_M  ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
-#define RTC_GPIO_STATUS_INT_W1TS_V  0x3FFFF
-#define RTC_GPIO_STATUS_INT_W1TS_S  14
-
-#define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)
-/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */
-/*description: GPIO0~17 interrupt status write 1 to clear*/
-#define RTC_GPIO_STATUS_INT_W1TC  0x0003FFFF
-#define RTC_GPIO_STATUS_INT_W1TC_M  ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))
-#define RTC_GPIO_STATUS_INT_W1TC_V  0x3FFFF
-#define RTC_GPIO_STATUS_INT_W1TC_S  14
-
-#define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x24)
-/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default:  ; */
-/*description: GPIO0~17 input value*/
-#define RTC_GPIO_IN_NEXT  0x0003FFFF
-#define RTC_GPIO_IN_NEXT_M  ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))
-#define RTC_GPIO_IN_NEXT_V  0x3FFFF
-#define RTC_GPIO_IN_NEXT_S  14
-
-#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0x28)
-/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN0_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN0_INT_TYPE_M  ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
-#define RTC_GPIO_PIN0_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN0_INT_TYPE_S  7
-/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN0_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN0_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN0_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0x2c)
-/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN1_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN1_INT_TYPE_M  ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
-#define RTC_GPIO_PIN1_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN1_INT_TYPE_S  7
-/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN1_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN1_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN1_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0x30)
-/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN2_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN2_INT_TYPE_M  ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
-#define RTC_GPIO_PIN2_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN2_INT_TYPE_S  7
-/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN2_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN2_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN2_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0x34)
-/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN3_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN3_INT_TYPE_M  ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
-#define RTC_GPIO_PIN3_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN3_INT_TYPE_S  7
-/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN3_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN3_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN3_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0x38)
-/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN4_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN4_INT_TYPE_M  ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
-#define RTC_GPIO_PIN4_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN4_INT_TYPE_S  7
-/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN4_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN4_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN4_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0x3c)
-/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN5_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN5_INT_TYPE_M  ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
-#define RTC_GPIO_PIN5_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN5_INT_TYPE_S  7
-/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN5_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN5_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN5_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x40)
-/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN6_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN6_INT_TYPE_M  ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
-#define RTC_GPIO_PIN6_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN6_INT_TYPE_S  7
-/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN6_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN6_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN6_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x44)
-/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN7_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN7_INT_TYPE_M  ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
-#define RTC_GPIO_PIN7_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN7_INT_TYPE_S  7
-/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN7_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN7_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN7_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x48)
-/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN8_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN8_INT_TYPE_M  ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
-#define RTC_GPIO_PIN8_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN8_INT_TYPE_S  7
-/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN8_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN8_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN8_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x4c)
-/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN9_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN9_INT_TYPE_M  ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
-#define RTC_GPIO_PIN9_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN9_INT_TYPE_S  7
-/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN9_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN9_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN9_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x50)
-/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN10_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN10_INT_TYPE_M  ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
-#define RTC_GPIO_PIN10_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN10_INT_TYPE_S  7
-/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN10_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN10_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN10_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x54)
-/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN11_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN11_INT_TYPE_M  ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
-#define RTC_GPIO_PIN11_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN11_INT_TYPE_S  7
-/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN11_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN11_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN11_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x58)
-/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN12_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN12_INT_TYPE_M  ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
-#define RTC_GPIO_PIN12_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN12_INT_TYPE_S  7
-/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN12_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN12_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN12_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x5c)
-/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN13_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN13_INT_TYPE_M  ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
-#define RTC_GPIO_PIN13_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN13_INT_TYPE_S  7
-/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN13_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN13_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN13_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x60)
-/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN14_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN14_INT_TYPE_M  ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
-#define RTC_GPIO_PIN14_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN14_INT_TYPE_S  7
-/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN14_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN14_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN14_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x64)
-/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN15_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN15_INT_TYPE_M  ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
-#define RTC_GPIO_PIN15_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN15_INT_TYPE_S  7
-/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN15_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN15_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN15_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x68)
-/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN16_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN16_INT_TYPE_M  ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
-#define RTC_GPIO_PIN16_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN16_INT_TYPE_S  7
-/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN16_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN16_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN16_PAD_DRIVER_S  2
-
-#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x6c)
-/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
-/*description: GPIO wake up enable  only available in light sleep*/
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V  0x1
-#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S  10
-/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
-/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge
- trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/
-#define RTC_GPIO_PIN17_INT_TYPE  0x00000007
-#define RTC_GPIO_PIN17_INT_TYPE_M  ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
-#define RTC_GPIO_PIN17_INT_TYPE_V  0x7
-#define RTC_GPIO_PIN17_INT_TYPE_S  7
-/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
-/*description: if set to 0: normal output  if set to 1: open drain*/
-#define RTC_GPIO_PIN17_PAD_DRIVER  (BIT(2))
-#define RTC_GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
-#define RTC_GPIO_PIN17_PAD_DRIVER_V  0x1
-#define RTC_GPIO_PIN17_PAD_DRIVER_S  2
-
-#define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x70)
-/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_12M_NO_GATING  (BIT(25))
-#define RTC_IO_DEBUG_12M_NO_GATING_M  (BIT(25))
-#define RTC_IO_DEBUG_12M_NO_GATING_V  0x1
-#define RTC_IO_DEBUG_12M_NO_GATING_S  25
-/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL4  0x0000001F
-#define RTC_IO_DEBUG_SEL4_M  ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))
-#define RTC_IO_DEBUG_SEL4_V  0x1F
-#define RTC_IO_DEBUG_SEL4_S  20
-/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL3  0x0000001F
-#define RTC_IO_DEBUG_SEL3_M  ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))
-#define RTC_IO_DEBUG_SEL3_V  0x1F
-#define RTC_IO_DEBUG_SEL3_S  15
-/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL2  0x0000001F
-#define RTC_IO_DEBUG_SEL2_M  ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))
-#define RTC_IO_DEBUG_SEL2_V  0x1F
-#define RTC_IO_DEBUG_SEL2_S  10
-/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL1  0x0000001F
-#define RTC_IO_DEBUG_SEL1_M  ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
-#define RTC_IO_DEBUG_SEL1_V  0x1F
-#define RTC_IO_DEBUG_SEL1_S  5
-/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define RTC_IO_DEBUG_SEL0  0x0000001F
-#define RTC_IO_DEBUG_SEL0_M  ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
-#define RTC_IO_DEBUG_SEL0_V  0x1F
-#define RTC_IO_DEBUG_SEL0_S  0
-
-#define RTC_IO_DIG_PAD_HOLD_REG          (DR_REG_RTCIO_BASE + 0x74)
-/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */
-/*description: select the digital pad hold value.*/
-#define RTC_IO_DIG_PAD_HOLD  0xFFFFFFFF
-#define RTC_IO_DIG_PAD_HOLD_M  ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))
-#define RTC_IO_DIG_PAD_HOLD_V  0xFFFFFFFF
-#define RTC_IO_DIG_PAD_HOLD_S  0
-
-#define RTC_IO_HALL_SENS_REG          (DR_REG_RTCIO_BASE + 0x78)
-/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: Power on hall sensor and connect to VP and VN*/
-#define RTC_IO_XPD_HALL  (BIT(31))
-#define RTC_IO_XPD_HALL_M  (BIT(31))
-#define RTC_IO_XPD_HALL_V  0x1
-#define RTC_IO_XPD_HALL_S  31
-/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: Reverse phase of hall sensor*/
-#define RTC_IO_HALL_PHASE  (BIT(30))
-#define RTC_IO_HALL_PHASE_M  (BIT(30))
-#define RTC_IO_HALL_PHASE_V  0x1
-#define RTC_IO_HALL_PHASE_S  30
-
-#define RTC_IO_SENSOR_PADS_REG          (DR_REG_RTCIO_BASE + 0x7c)
-/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE1_HOLD  (BIT(31))
-#define RTC_IO_SENSE1_HOLD_M  (BIT(31))
-#define RTC_IO_SENSE1_HOLD_V  0x1
-#define RTC_IO_SENSE1_HOLD_S  31
-/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE2_HOLD  (BIT(30))
-#define RTC_IO_SENSE2_HOLD_M  (BIT(30))
-#define RTC_IO_SENSE2_HOLD_V  0x1
-#define RTC_IO_SENSE2_HOLD_S  30
-/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE3_HOLD  (BIT(29))
-#define RTC_IO_SENSE3_HOLD_M  (BIT(29))
-#define RTC_IO_SENSE3_HOLD_V  0x1
-#define RTC_IO_SENSE3_HOLD_S  29
-/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_SENSE4_HOLD  (BIT(28))
-#define RTC_IO_SENSE4_HOLD_M  (BIT(28))
-#define RTC_IO_SENSE4_HOLD_V  0x1
-#define RTC_IO_SENSE4_HOLD_S  28
-/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE1_MUX_SEL  (BIT(27))
-#define RTC_IO_SENSE1_MUX_SEL_M  (BIT(27))
-#define RTC_IO_SENSE1_MUX_SEL_V  0x1
-#define RTC_IO_SENSE1_MUX_SEL_S  27
-/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE2_MUX_SEL  (BIT(26))
-#define RTC_IO_SENSE2_MUX_SEL_M  (BIT(26))
-#define RTC_IO_SENSE2_MUX_SEL_V  0x1
-#define RTC_IO_SENSE2_MUX_SEL_S  26
-/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE3_MUX_SEL  (BIT(25))
-#define RTC_IO_SENSE3_MUX_SEL_M  (BIT(25))
-#define RTC_IO_SENSE3_MUX_SEL_V  0x1
-#define RTC_IO_SENSE3_MUX_SEL_S  25
-/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_SENSE4_MUX_SEL  (BIT(24))
-#define RTC_IO_SENSE4_MUX_SEL_M  (BIT(24))
-#define RTC_IO_SENSE4_MUX_SEL_V  0x1
-#define RTC_IO_SENSE4_MUX_SEL_S  24
-/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE1_FUN_SEL  0x00000003
-#define RTC_IO_SENSE1_FUN_SEL_M  ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))
-#define RTC_IO_SENSE1_FUN_SEL_V  0x3
-#define RTC_IO_SENSE1_FUN_SEL_S  22
-/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE1_SLP_SEL  (BIT(21))
-#define RTC_IO_SENSE1_SLP_SEL_M  (BIT(21))
-#define RTC_IO_SENSE1_SLP_SEL_V  0x1
-#define RTC_IO_SENSE1_SLP_SEL_S  21
-/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE1_SLP_IE  (BIT(20))
-#define RTC_IO_SENSE1_SLP_IE_M  (BIT(20))
-#define RTC_IO_SENSE1_SLP_IE_V  0x1
-#define RTC_IO_SENSE1_SLP_IE_S  20
-/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE1_FUN_IE  (BIT(19))
-#define RTC_IO_SENSE1_FUN_IE_M  (BIT(19))
-#define RTC_IO_SENSE1_FUN_IE_V  0x1
-#define RTC_IO_SENSE1_FUN_IE_S  19
-/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE2_FUN_SEL  0x00000003
-#define RTC_IO_SENSE2_FUN_SEL_M  ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))
-#define RTC_IO_SENSE2_FUN_SEL_V  0x3
-#define RTC_IO_SENSE2_FUN_SEL_S  17
-/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE2_SLP_SEL  (BIT(16))
-#define RTC_IO_SENSE2_SLP_SEL_M  (BIT(16))
-#define RTC_IO_SENSE2_SLP_SEL_V  0x1
-#define RTC_IO_SENSE2_SLP_SEL_S  16
-/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE2_SLP_IE  (BIT(15))
-#define RTC_IO_SENSE2_SLP_IE_M  (BIT(15))
-#define RTC_IO_SENSE2_SLP_IE_V  0x1
-#define RTC_IO_SENSE2_SLP_IE_S  15
-/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE2_FUN_IE  (BIT(14))
-#define RTC_IO_SENSE2_FUN_IE_M  (BIT(14))
-#define RTC_IO_SENSE2_FUN_IE_V  0x1
-#define RTC_IO_SENSE2_FUN_IE_S  14
-/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE3_FUN_SEL  0x00000003
-#define RTC_IO_SENSE3_FUN_SEL_M  ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))
-#define RTC_IO_SENSE3_FUN_SEL_V  0x3
-#define RTC_IO_SENSE3_FUN_SEL_S  12
-/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE3_SLP_SEL  (BIT(11))
-#define RTC_IO_SENSE3_SLP_SEL_M  (BIT(11))
-#define RTC_IO_SENSE3_SLP_SEL_V  0x1
-#define RTC_IO_SENSE3_SLP_SEL_S  11
-/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE3_SLP_IE  (BIT(10))
-#define RTC_IO_SENSE3_SLP_IE_M  (BIT(10))
-#define RTC_IO_SENSE3_SLP_IE_V  0x1
-#define RTC_IO_SENSE3_SLP_IE_S  10
-/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE3_FUN_IE  (BIT(9))
-#define RTC_IO_SENSE3_FUN_IE_M  (BIT(9))
-#define RTC_IO_SENSE3_FUN_IE_V  0x1
-#define RTC_IO_SENSE3_FUN_IE_S  9
-/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_SENSE4_FUN_SEL  0x00000003
-#define RTC_IO_SENSE4_FUN_SEL_M  ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))
-#define RTC_IO_SENSE4_FUN_SEL_V  0x3
-#define RTC_IO_SENSE4_FUN_SEL_S  7
-/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_SENSE4_SLP_SEL  (BIT(6))
-#define RTC_IO_SENSE4_SLP_SEL_M  (BIT(6))
-#define RTC_IO_SENSE4_SLP_SEL_V  0x1
-#define RTC_IO_SENSE4_SLP_SEL_S  6
-/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_SENSE4_SLP_IE  (BIT(5))
-#define RTC_IO_SENSE4_SLP_IE_M  (BIT(5))
-#define RTC_IO_SENSE4_SLP_IE_V  0x1
-#define RTC_IO_SENSE4_SLP_IE_S  5
-/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_SENSE4_FUN_IE  (BIT(4))
-#define RTC_IO_SENSE4_FUN_IE_M  (BIT(4))
-#define RTC_IO_SENSE4_FUN_IE_V  0x1
-#define RTC_IO_SENSE4_FUN_IE_S  4
-
-#define RTC_IO_ADC_PAD_REG          (DR_REG_RTCIO_BASE + 0x80)
-/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_ADC1_HOLD  (BIT(31))
-#define RTC_IO_ADC1_HOLD_M  (BIT(31))
-#define RTC_IO_ADC1_HOLD_V  0x1
-#define RTC_IO_ADC1_HOLD_S  31
-/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_ADC2_HOLD  (BIT(30))
-#define RTC_IO_ADC2_HOLD_M  (BIT(30))
-#define RTC_IO_ADC2_HOLD_V  0x1
-#define RTC_IO_ADC2_HOLD_S  30
-/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_ADC1_MUX_SEL  (BIT(29))
-#define RTC_IO_ADC1_MUX_SEL_M  (BIT(29))
-#define RTC_IO_ADC1_MUX_SEL_V  0x1
-#define RTC_IO_ADC1_MUX_SEL_S  29
-/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_ADC2_MUX_SEL  (BIT(28))
-#define RTC_IO_ADC2_MUX_SEL_M  (BIT(28))
-#define RTC_IO_ADC2_MUX_SEL_V  0x1
-#define RTC_IO_ADC2_MUX_SEL_S  28
-/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_ADC1_FUN_SEL  0x00000003
-#define RTC_IO_ADC1_FUN_SEL_M  ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))
-#define RTC_IO_ADC1_FUN_SEL_V  0x3
-#define RTC_IO_ADC1_FUN_SEL_S  26
-/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_ADC1_SLP_SEL  (BIT(25))
-#define RTC_IO_ADC1_SLP_SEL_M  (BIT(25))
-#define RTC_IO_ADC1_SLP_SEL_V  0x1
-#define RTC_IO_ADC1_SLP_SEL_S  25
-/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_ADC1_SLP_IE  (BIT(24))
-#define RTC_IO_ADC1_SLP_IE_M  (BIT(24))
-#define RTC_IO_ADC1_SLP_IE_V  0x1
-#define RTC_IO_ADC1_SLP_IE_S  24
-/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_ADC1_FUN_IE  (BIT(23))
-#define RTC_IO_ADC1_FUN_IE_M  (BIT(23))
-#define RTC_IO_ADC1_FUN_IE_V  0x1
-#define RTC_IO_ADC1_FUN_IE_S  23
-/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_ADC2_FUN_SEL  0x00000003
-#define RTC_IO_ADC2_FUN_SEL_M  ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))
-#define RTC_IO_ADC2_FUN_SEL_V  0x3
-#define RTC_IO_ADC2_FUN_SEL_S  21
-/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_ADC2_SLP_SEL  (BIT(20))
-#define RTC_IO_ADC2_SLP_SEL_M  (BIT(20))
-#define RTC_IO_ADC2_SLP_SEL_V  0x1
-#define RTC_IO_ADC2_SLP_SEL_S  20
-/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_ADC2_SLP_IE  (BIT(19))
-#define RTC_IO_ADC2_SLP_IE_M  (BIT(19))
-#define RTC_IO_ADC2_SLP_IE_V  0x1
-#define RTC_IO_ADC2_SLP_IE_S  19
-/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_ADC2_FUN_IE  (BIT(18))
-#define RTC_IO_ADC2_FUN_IE_M  (BIT(18))
-#define RTC_IO_ADC2_FUN_IE_V  0x1
-#define RTC_IO_ADC2_FUN_IE_S  18
-
-#define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0x84)
-/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_PDAC1_DRV  0x00000003
-#define RTC_IO_PDAC1_DRV_M  ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
-#define RTC_IO_PDAC1_DRV_V  0x3
-#define RTC_IO_PDAC1_DRV_S  30
-/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_PDAC1_HOLD  (BIT(29))
-#define RTC_IO_PDAC1_HOLD_M  (BIT(29))
-#define RTC_IO_PDAC1_HOLD_V  0x1
-#define RTC_IO_PDAC1_HOLD_S  29
-/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_PDAC1_RDE  (BIT(28))
-#define RTC_IO_PDAC1_RDE_M  (BIT(28))
-#define RTC_IO_PDAC1_RDE_V  0x1
-#define RTC_IO_PDAC1_RDE_S  28
-/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_PDAC1_RUE  (BIT(27))
-#define RTC_IO_PDAC1_RUE_M  (BIT(27))
-#define RTC_IO_PDAC1_RUE_V  0x1
-#define RTC_IO_PDAC1_RUE_S  27
-/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
-/*description: PAD DAC1 control code.*/
-#define RTC_IO_PDAC1_DAC  0x000000FF
-#define RTC_IO_PDAC1_DAC_M  ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
-#define RTC_IO_PDAC1_DAC_V  0xFF
-#define RTC_IO_PDAC1_DAC_S  19
-/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC1_XPD_DAC  (BIT(18))
-#define RTC_IO_PDAC1_XPD_DAC_M  (BIT(18))
-#define RTC_IO_PDAC1_XPD_DAC_V  0x1
-#define RTC_IO_PDAC1_XPD_DAC_S  18
-/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_PDAC1_MUX_SEL  (BIT(17))
-#define RTC_IO_PDAC1_MUX_SEL_M  (BIT(17))
-#define RTC_IO_PDAC1_MUX_SEL_V  0x1
-#define RTC_IO_PDAC1_MUX_SEL_S  17
-/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_PDAC1_FUN_SEL  0x00000003
-#define RTC_IO_PDAC1_FUN_SEL_M  ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
-#define RTC_IO_PDAC1_FUN_SEL_V  0x3
-#define RTC_IO_PDAC1_FUN_SEL_S  15
-/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_PDAC1_SLP_SEL  (BIT(14))
-#define RTC_IO_PDAC1_SLP_SEL_M  (BIT(14))
-#define RTC_IO_PDAC1_SLP_SEL_V  0x1
-#define RTC_IO_PDAC1_SLP_SEL_S  14
-/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_PDAC1_SLP_IE  (BIT(13))
-#define RTC_IO_PDAC1_SLP_IE_M  (BIT(13))
-#define RTC_IO_PDAC1_SLP_IE_V  0x1
-#define RTC_IO_PDAC1_SLP_IE_S  13
-/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_PDAC1_SLP_OE  (BIT(12))
-#define RTC_IO_PDAC1_SLP_OE_M  (BIT(12))
-#define RTC_IO_PDAC1_SLP_OE_V  0x1
-#define RTC_IO_PDAC1_SLP_OE_S  12
-/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_PDAC1_FUN_IE  (BIT(11))
-#define RTC_IO_PDAC1_FUN_IE_M  (BIT(11))
-#define RTC_IO_PDAC1_FUN_IE_V  0x1
-#define RTC_IO_PDAC1_FUN_IE_S  11
-/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC1_DAC_XPD_FORCE  (BIT(10))
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_M  (BIT(10))
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_V  0x1
-#define RTC_IO_PDAC1_DAC_XPD_FORCE_S  10
-
-#define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0x88)
-/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_PDAC2_DRV  0x00000003
-#define RTC_IO_PDAC2_DRV_M  ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
-#define RTC_IO_PDAC2_DRV_V  0x3
-#define RTC_IO_PDAC2_DRV_S  30
-/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_PDAC2_HOLD  (BIT(29))
-#define RTC_IO_PDAC2_HOLD_M  (BIT(29))
-#define RTC_IO_PDAC2_HOLD_V  0x1
-#define RTC_IO_PDAC2_HOLD_S  29
-/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_PDAC2_RDE  (BIT(28))
-#define RTC_IO_PDAC2_RDE_M  (BIT(28))
-#define RTC_IO_PDAC2_RDE_V  0x1
-#define RTC_IO_PDAC2_RDE_S  28
-/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_PDAC2_RUE  (BIT(27))
-#define RTC_IO_PDAC2_RUE_M  (BIT(27))
-#define RTC_IO_PDAC2_RUE_V  0x1
-#define RTC_IO_PDAC2_RUE_S  27
-/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
-/*description: PAD DAC2 control code.*/
-#define RTC_IO_PDAC2_DAC  0x000000FF
-#define RTC_IO_PDAC2_DAC_M  ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
-#define RTC_IO_PDAC2_DAC_V  0xFF
-#define RTC_IO_PDAC2_DAC_S  19
-/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Power on DAC2. Usually  we need to tristate PDAC1 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC2_XPD_DAC  (BIT(18))
-#define RTC_IO_PDAC2_XPD_DAC_M  (BIT(18))
-#define RTC_IO_PDAC2_XPD_DAC_V  0x1
-#define RTC_IO_PDAC2_XPD_DAC_S  18
-/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_PDAC2_MUX_SEL  (BIT(17))
-#define RTC_IO_PDAC2_MUX_SEL_M  (BIT(17))
-#define RTC_IO_PDAC2_MUX_SEL_V  0x1
-#define RTC_IO_PDAC2_MUX_SEL_S  17
-/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_PDAC2_FUN_SEL  0x00000003
-#define RTC_IO_PDAC2_FUN_SEL_M  ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
-#define RTC_IO_PDAC2_FUN_SEL_V  0x3
-#define RTC_IO_PDAC2_FUN_SEL_S  15
-/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_PDAC2_SLP_SEL  (BIT(14))
-#define RTC_IO_PDAC2_SLP_SEL_M  (BIT(14))
-#define RTC_IO_PDAC2_SLP_SEL_V  0x1
-#define RTC_IO_PDAC2_SLP_SEL_S  14
-/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_PDAC2_SLP_IE  (BIT(13))
-#define RTC_IO_PDAC2_SLP_IE_M  (BIT(13))
-#define RTC_IO_PDAC2_SLP_IE_V  0x1
-#define RTC_IO_PDAC2_SLP_IE_S  13
-/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_PDAC2_SLP_OE  (BIT(12))
-#define RTC_IO_PDAC2_SLP_OE_M  (BIT(12))
-#define RTC_IO_PDAC2_SLP_OE_V  0x1
-#define RTC_IO_PDAC2_SLP_OE_S  12
-/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_PDAC2_FUN_IE  (BIT(11))
-#define RTC_IO_PDAC2_FUN_IE_M  (BIT(11))
-#define RTC_IO_PDAC2_FUN_IE_V  0x1
-#define RTC_IO_PDAC2_FUN_IE_S  11
-/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
-/*description: Power on DAC2. Usually  we need to tristate PDAC2 if we power
- on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/
-#define RTC_IO_PDAC2_DAC_XPD_FORCE  (BIT(10))
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_M  (BIT(10))
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_V  0x1
-#define RTC_IO_PDAC2_DAC_XPD_FORCE_S  10
-
-#define RTC_IO_XTAL_32K_PAD_REG          (DR_REG_RTCIO_BASE + 0x8c)
-/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_X32N_DRV  0x00000003
-#define RTC_IO_X32N_DRV_M  ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))
-#define RTC_IO_X32N_DRV_V  0x3
-#define RTC_IO_X32N_DRV_S  30
-/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_X32N_HOLD  (BIT(29))
-#define RTC_IO_X32N_HOLD_M  (BIT(29))
-#define RTC_IO_X32N_HOLD_V  0x1
-#define RTC_IO_X32N_HOLD_S  29
-/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_X32N_RDE  (BIT(28))
-#define RTC_IO_X32N_RDE_M  (BIT(28))
-#define RTC_IO_X32N_RDE_V  0x1
-#define RTC_IO_X32N_RDE_S  28
-/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_X32N_RUE  (BIT(27))
-#define RTC_IO_X32N_RUE_M  (BIT(27))
-#define RTC_IO_X32N_RUE_V  0x1
-#define RTC_IO_X32N_RUE_S  27
-/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_X32P_DRV  0x00000003
-#define RTC_IO_X32P_DRV_M  ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))
-#define RTC_IO_X32P_DRV_V  0x3
-#define RTC_IO_X32P_DRV_S  25
-/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_X32P_HOLD  (BIT(24))
-#define RTC_IO_X32P_HOLD_M  (BIT(24))
-#define RTC_IO_X32P_HOLD_V  0x1
-#define RTC_IO_X32P_HOLD_S  24
-/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_X32P_RDE  (BIT(23))
-#define RTC_IO_X32P_RDE_M  (BIT(23))
-#define RTC_IO_X32P_RDE_V  0x1
-#define RTC_IO_X32P_RDE_S  23
-/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_X32P_RUE  (BIT(22))
-#define RTC_IO_X32P_RUE_M  (BIT(22))
-#define RTC_IO_X32P_RUE_V  0x1
-#define RTC_IO_X32P_RUE_S  22
-/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */
-/*description: 32K XTAL bias current DAC.*/
-#define RTC_IO_DAC_XTAL_32K  0x00000003
-#define RTC_IO_DAC_XTAL_32K_M  ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
-#define RTC_IO_DAC_XTAL_32K_V  0x3
-#define RTC_IO_DAC_XTAL_32K_S  20
-/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Power up 32kHz crystal oscillator*/
-#define RTC_IO_XPD_XTAL_32K  (BIT(19))
-#define RTC_IO_XPD_XTAL_32K_M  (BIT(19))
-#define RTC_IO_XPD_XTAL_32K_V  0x1
-#define RTC_IO_XPD_XTAL_32K_S  19
-/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_X32N_MUX_SEL  (BIT(18))
-#define RTC_IO_X32N_MUX_SEL_M  (BIT(18))
-#define RTC_IO_X32N_MUX_SEL_V  0x1
-#define RTC_IO_X32N_MUX_SEL_S  18
-/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_X32P_MUX_SEL  (BIT(17))
-#define RTC_IO_X32P_MUX_SEL_M  (BIT(17))
-#define RTC_IO_X32P_MUX_SEL_V  0x1
-#define RTC_IO_X32P_MUX_SEL_S  17
-/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_X32N_FUN_SEL  0x00000003
-#define RTC_IO_X32N_FUN_SEL_M  ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))
-#define RTC_IO_X32N_FUN_SEL_V  0x3
-#define RTC_IO_X32N_FUN_SEL_S  15
-/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_X32N_SLP_SEL  (BIT(14))
-#define RTC_IO_X32N_SLP_SEL_M  (BIT(14))
-#define RTC_IO_X32N_SLP_SEL_V  0x1
-#define RTC_IO_X32N_SLP_SEL_S  14
-/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_X32N_SLP_IE  (BIT(13))
-#define RTC_IO_X32N_SLP_IE_M  (BIT(13))
-#define RTC_IO_X32N_SLP_IE_V  0x1
-#define RTC_IO_X32N_SLP_IE_S  13
-/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_X32N_SLP_OE  (BIT(12))
-#define RTC_IO_X32N_SLP_OE_M  (BIT(12))
-#define RTC_IO_X32N_SLP_OE_V  0x1
-#define RTC_IO_X32N_SLP_OE_S  12
-/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_X32N_FUN_IE  (BIT(11))
-#define RTC_IO_X32N_FUN_IE_M  (BIT(11))
-#define RTC_IO_X32N_FUN_IE_V  0x1
-#define RTC_IO_X32N_FUN_IE_S  11
-/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_X32P_FUN_SEL  0x00000003
-#define RTC_IO_X32P_FUN_SEL_M  ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))
-#define RTC_IO_X32P_FUN_SEL_V  0x3
-#define RTC_IO_X32P_FUN_SEL_S  9
-/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_X32P_SLP_SEL  (BIT(8))
-#define RTC_IO_X32P_SLP_SEL_M  (BIT(8))
-#define RTC_IO_X32P_SLP_SEL_V  0x1
-#define RTC_IO_X32P_SLP_SEL_S  8
-/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_X32P_SLP_IE  (BIT(7))
-#define RTC_IO_X32P_SLP_IE_M  (BIT(7))
-#define RTC_IO_X32P_SLP_IE_V  0x1
-#define RTC_IO_X32P_SLP_IE_S  7
-/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_X32P_SLP_OE  (BIT(6))
-#define RTC_IO_X32P_SLP_OE_M  (BIT(6))
-#define RTC_IO_X32P_SLP_OE_V  0x1
-#define RTC_IO_X32P_SLP_OE_S  6
-/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_X32P_FUN_IE  (BIT(5))
-#define RTC_IO_X32P_FUN_IE_M  (BIT(5))
-#define RTC_IO_X32P_FUN_IE_V  0x1
-#define RTC_IO_X32P_FUN_IE_S  5
-/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */
-/*description: 32K XTAL resistor bias control.*/
-#define RTC_IO_DRES_XTAL_32K  0x00000003
-#define RTC_IO_DRES_XTAL_32K_M  ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
-#define RTC_IO_DRES_XTAL_32K_V  0x3
-#define RTC_IO_DRES_XTAL_32K_S  3
-/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
-/*description: 32K XTAL self-bias reference control.*/
-#define RTC_IO_DBIAS_XTAL_32K  0x00000003
-#define RTC_IO_DBIAS_XTAL_32K_M  ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))
-#define RTC_IO_DBIAS_XTAL_32K_V  0x3
-#define RTC_IO_DBIAS_XTAL_32K_S  1
-
-#define RTC_IO_TOUCH_CFG_REG          (DR_REG_RTCIO_BASE + 0x90)
-/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: touch sensor bias power on.*/
-#define RTC_IO_TOUCH_XPD_BIAS  (BIT(31))
-#define RTC_IO_TOUCH_XPD_BIAS_M  (BIT(31))
-#define RTC_IO_TOUCH_XPD_BIAS_V  0x1
-#define RTC_IO_TOUCH_XPD_BIAS_S  31
-/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */
-/*description: touch sensor saw wave top voltage.*/
-#define RTC_IO_TOUCH_DREFH  0x00000003
-#define RTC_IO_TOUCH_DREFH_M  ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))
-#define RTC_IO_TOUCH_DREFH_V  0x3
-#define RTC_IO_TOUCH_DREFH_S  29
-/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
-/*description: touch sensor saw wave bottom voltage.*/
-#define RTC_IO_TOUCH_DREFL  0x00000003
-#define RTC_IO_TOUCH_DREFL_M  ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))
-#define RTC_IO_TOUCH_DREFL_V  0x3
-#define RTC_IO_TOUCH_DREFL_S  27
-/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */
-/*description: touch sensor saw wave voltage range.*/
-#define RTC_IO_TOUCH_DRANGE  0x00000003
-#define RTC_IO_TOUCH_DRANGE_M  ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))
-#define RTC_IO_TOUCH_DRANGE_V  0x3
-#define RTC_IO_TOUCH_DRANGE_S  25
-/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */
-/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When
- BIAS_SLEEP  this setting is available*/
-#define RTC_IO_TOUCH_DCUR  0x00000003
-#define RTC_IO_TOUCH_DCUR_M  ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))
-#define RTC_IO_TOUCH_DCUR_V  0x3
-#define RTC_IO_TOUCH_DCUR_S  23
-
-#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x94)
-/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD0_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD0_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD0_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD0_HOLD_S  31
-/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD0_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD0_DRV_M  ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))
-#define RTC_IO_TOUCH_PAD0_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD0_DRV_S  29
-/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD0_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD0_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD0_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD0_RDE_S  28
-/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD0_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD0_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD0_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD0_RUE_S  27
-/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD0_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD0_DAC_M  ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
-#define RTC_IO_TOUCH_PAD0_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD0_DAC_S  23
-/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD0_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD0_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD0_START_V  0x1
-#define RTC_IO_TOUCH_PAD0_START_S  22
-/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD0_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD0_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD0_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD0_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD0_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD0_XPD_S  20
-/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD0_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD0_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD0_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_M  ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD0_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD0_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD0_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD0_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD0_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD0_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD0_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD0_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD0_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD0_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD0_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD0_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD0_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD0_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD0_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/
-#define RTC_IO_TOUCH_PAD0_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD0_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x98)
-/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: */
-#define RTC_IO_TOUCH_PAD1_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD1_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD1_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD1_HOLD_S  31
-/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD1_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD1_DRV_M  ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))
-#define RTC_IO_TOUCH_PAD1_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD1_DRV_S  29
-/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD1_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD1_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD1_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD1_RDE_S  28
-/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD1_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD1_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD1_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD1_RUE_S  27
-/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD1_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD1_DAC_M  ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
-#define RTC_IO_TOUCH_PAD1_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD1_DAC_S  23
-/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD1_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD1_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD1_START_V  0x1
-#define RTC_IO_TOUCH_PAD1_START_S  22
-/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD1_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD1_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD1_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD1_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD1_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD1_XPD_S  20
-/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD1_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD1_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD1_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_M  ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD1_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD1_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD1_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD1_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD1_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD1_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD1_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD1_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD1_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD1_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD1_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD1_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD1_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD1_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD1_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/
-#define RTC_IO_TOUCH_PAD1_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD1_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x9c)
-/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD2_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD2_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD2_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD2_HOLD_S  31
-/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD2_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD2_DRV_M  ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))
-#define RTC_IO_TOUCH_PAD2_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD2_DRV_S  29
-/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD2_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD2_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD2_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD2_RDE_S  28
-/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD2_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD2_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD2_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD2_RUE_S  27
-/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD2_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD2_DAC_M  ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
-#define RTC_IO_TOUCH_PAD2_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD2_DAC_S  23
-/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD2_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD2_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD2_START_V  0x1
-#define RTC_IO_TOUCH_PAD2_START_S  22
-/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD2_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD2_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD2_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD2_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD2_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD2_XPD_S  20
-/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD2_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD2_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD2_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_M  ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD2_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD2_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD2_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD2_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD2_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD2_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD2_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD2_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD2_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD2_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD2_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD2_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD2_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD2_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD2_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/
-#define RTC_IO_TOUCH_PAD2_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD2_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0xa0)
-/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD3_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD3_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD3_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD3_HOLD_S  31
-/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD3_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD3_DRV_M  ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))
-#define RTC_IO_TOUCH_PAD3_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD3_DRV_S  29
-/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD3_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD3_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD3_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD3_RDE_S  28
-/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD3_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD3_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD3_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD3_RUE_S  27
-/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD3_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD3_DAC_M  ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
-#define RTC_IO_TOUCH_PAD3_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD3_DAC_S  23
-/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD3_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD3_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD3_START_V  0x1
-#define RTC_IO_TOUCH_PAD3_START_S  22
-/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD3_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD3_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD3_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD3_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD3_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD3_XPD_S  20
-/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD3_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD3_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD3_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_M  ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD3_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD3_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD3_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD3_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD3_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD3_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD3_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD3_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD3_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD3_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD3_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD3_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD3_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD3_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD3_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/
-#define RTC_IO_TOUCH_PAD3_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD3_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0xa4)
-/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD4_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD4_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD4_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD4_HOLD_S  31
-/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD4_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD4_DRV_M  ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))
-#define RTC_IO_TOUCH_PAD4_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD4_DRV_S  29
-/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD4_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD4_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD4_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD4_RDE_S  28
-/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD4_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD4_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD4_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD4_RUE_S  27
-/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD4_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD4_DAC_M  ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
-#define RTC_IO_TOUCH_PAD4_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD4_DAC_S  23
-/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD4_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD4_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD4_START_V  0x1
-#define RTC_IO_TOUCH_PAD4_START_S  22
-/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD4_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD4_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD4_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD4_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD4_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD4_XPD_S  20
-/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD4_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD4_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD4_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_M  ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD4_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD4_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD4_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD4_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD4_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD4_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD4_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD4_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD4_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD4_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD4_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD4_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD4_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD4_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD4_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/
-#define RTC_IO_TOUCH_PAD4_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD4_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0xa8)
-/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD5_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD5_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD5_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD5_HOLD_S  31
-/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD5_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD5_DRV_M  ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))
-#define RTC_IO_TOUCH_PAD5_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD5_DRV_S  29
-/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD5_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD5_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD5_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD5_RDE_S  28
-/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD5_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD5_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD5_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD5_RUE_S  27
-/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD5_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD5_DAC_M  ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
-#define RTC_IO_TOUCH_PAD5_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD5_DAC_S  23
-/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD5_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD5_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD5_START_V  0x1
-#define RTC_IO_TOUCH_PAD5_START_S  22
-/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD5_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD5_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD5_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD5_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD5_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD5_XPD_S  20
-/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD5_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD5_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD5_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_M  ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD5_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD5_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD5_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD5_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD5_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD5_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD5_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD5_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD5_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD5_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD5_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD5_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD5_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD5_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD5_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/
-#define RTC_IO_TOUCH_PAD5_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD5_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0xac)
-/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD6_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD6_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD6_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD6_HOLD_S  31
-/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD6_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD6_DRV_M  ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))
-#define RTC_IO_TOUCH_PAD6_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD6_DRV_S  29
-/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD6_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD6_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD6_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD6_RDE_S  28
-/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD6_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD6_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD6_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD6_RUE_S  27
-/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD6_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD6_DAC_M  ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
-#define RTC_IO_TOUCH_PAD6_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD6_DAC_S  23
-/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD6_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD6_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD6_START_V  0x1
-#define RTC_IO_TOUCH_PAD6_START_S  22
-/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD6_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD6_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD6_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD6_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD6_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD6_XPD_S  20
-/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD6_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD6_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD6_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_M  ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD6_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD6_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD6_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD6_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD6_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD6_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD6_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD6_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD6_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD6_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD6_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD6_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD6_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD6_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD6_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/
-#define RTC_IO_TOUCH_PAD6_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD6_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0xb0)
-/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */
-/*description: hold the current value of the output when setting the hold to Ò1Ó*/
-#define RTC_IO_TOUCH_PAD7_HOLD  (BIT(31))
-#define RTC_IO_TOUCH_PAD7_HOLD_M  (BIT(31))
-#define RTC_IO_TOUCH_PAD7_HOLD_V  0x1
-#define RTC_IO_TOUCH_PAD7_HOLD_S  31
-/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
-/*description: the driver strength of the pad*/
-#define RTC_IO_TOUCH_PAD7_DRV  0x00000003
-#define RTC_IO_TOUCH_PAD7_DRV_M  ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))
-#define RTC_IO_TOUCH_PAD7_DRV_V  0x3
-#define RTC_IO_TOUCH_PAD7_DRV_S  29
-/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
-/*description: the pull down enable of the pad*/
-#define RTC_IO_TOUCH_PAD7_RDE  (BIT(28))
-#define RTC_IO_TOUCH_PAD7_RDE_M  (BIT(28))
-#define RTC_IO_TOUCH_PAD7_RDE_V  0x1
-#define RTC_IO_TOUCH_PAD7_RDE_S  28
-/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
-/*description: the pull up enable of the pad*/
-#define RTC_IO_TOUCH_PAD7_RUE  (BIT(27))
-#define RTC_IO_TOUCH_PAD7_RUE_M  (BIT(27))
-#define RTC_IO_TOUCH_PAD7_RUE_V  0x1
-#define RTC_IO_TOUCH_PAD7_RUE_S  27
-/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD7_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD7_DAC_M  ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
-#define RTC_IO_TOUCH_PAD7_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD7_DAC_S  23
-/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD7_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD7_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD7_START_V  0x1
-#define RTC_IO_TOUCH_PAD7_START_S  22
-/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD7_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD7_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD7_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD7_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD7_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD7_XPD_S  20
-/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/
-#define RTC_IO_TOUCH_PAD7_MUX_SEL  (BIT(19))
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD7_MUX_SEL_S  19
-/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
-/*description: the functional selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD7_FUN_SEL  0x00000003
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_M  ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_V  0x3
-#define RTC_IO_TOUCH_PAD7_FUN_SEL_S  17
-/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
-/*description: the sleep status selection signal of the pad*/
-#define RTC_IO_TOUCH_PAD7_SLP_SEL  (BIT(16))
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_M  (BIT(16))
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_V  0x1
-#define RTC_IO_TOUCH_PAD7_SLP_SEL_S  16
-/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
-/*description: the input enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD7_SLP_IE  (BIT(15))
-#define RTC_IO_TOUCH_PAD7_SLP_IE_M  (BIT(15))
-#define RTC_IO_TOUCH_PAD7_SLP_IE_V  0x1
-#define RTC_IO_TOUCH_PAD7_SLP_IE_S  15
-/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
-/*description: the output enable of the pad in sleep status*/
-#define RTC_IO_TOUCH_PAD7_SLP_OE  (BIT(14))
-#define RTC_IO_TOUCH_PAD7_SLP_OE_M  (BIT(14))
-#define RTC_IO_TOUCH_PAD7_SLP_OE_V  0x1
-#define RTC_IO_TOUCH_PAD7_SLP_OE_S  14
-/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
-/*description: the input enable of the pad*/
-#define RTC_IO_TOUCH_PAD7_FUN_IE  (BIT(13))
-#define RTC_IO_TOUCH_PAD7_FUN_IE_M  (BIT(13))
-#define RTC_IO_TOUCH_PAD7_FUN_IE_V  0x1
-#define RTC_IO_TOUCH_PAD7_FUN_IE_S  13
-/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/
-#define RTC_IO_TOUCH_PAD7_TO_GPIO  (BIT(12))
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_M  (BIT(12))
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD7_TO_GPIO_S  12
-
-#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0xb4)
-/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD8_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD8_DAC_M  ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))
-#define RTC_IO_TOUCH_PAD8_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD8_DAC_S  23
-/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD8_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD8_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD8_START_V  0x1
-#define RTC_IO_TOUCH_PAD8_START_S  22
-/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD8_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD8_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD8_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD8_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD8_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD8_XPD_S  20
-/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
-#define RTC_IO_TOUCH_PAD8_TO_GPIO  (BIT(19))
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD8_TO_GPIO_S  19
-
-#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0xb8)
-/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
-/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/
-#define RTC_IO_TOUCH_PAD9_DAC  0x00000007
-#define RTC_IO_TOUCH_PAD9_DAC_M  ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))
-#define RTC_IO_TOUCH_PAD9_DAC_V  0x7
-#define RTC_IO_TOUCH_PAD9_DAC_S  23
-/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
-/*description: start touch sensor.*/
-#define RTC_IO_TOUCH_PAD9_START  (BIT(22))
-#define RTC_IO_TOUCH_PAD9_START_M  (BIT(22))
-#define RTC_IO_TOUCH_PAD9_START_V  0x1
-#define RTC_IO_TOUCH_PAD9_START_S  22
-/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
-/*description: default touch sensor tie option. 0: tie low  1: tie high.*/
-#define RTC_IO_TOUCH_PAD9_TIE_OPT  (BIT(21))
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_M  (BIT(21))
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_V  0x1
-#define RTC_IO_TOUCH_PAD9_TIE_OPT_S  21
-/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
-/*description: touch sensor power on.*/
-#define RTC_IO_TOUCH_PAD9_XPD  (BIT(20))
-#define RTC_IO_TOUCH_PAD9_XPD_M  (BIT(20))
-#define RTC_IO_TOUCH_PAD9_XPD_V  0x1
-#define RTC_IO_TOUCH_PAD9_XPD_S  20
-/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */
-/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/
-#define RTC_IO_TOUCH_PAD9_TO_GPIO  (BIT(19))
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_M  (BIT(19))
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_V  0x1
-#define RTC_IO_TOUCH_PAD9_TO_GPIO_S  19
-
-#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0xbc)
-/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/
-#define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F
-#define RTC_IO_EXT_WAKEUP0_SEL_M  ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
-#define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F
-#define RTC_IO_EXT_WAKEUP0_SEL_S  27
-
-#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0xc0)
-/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
-/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select
- GPIO2 ...Ò17Ó select GPIO17*/
-#define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F
-#define RTC_IO_XTL_EXT_CTR_SEL_M  ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
-#define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F
-#define RTC_IO_XTL_EXT_CTR_SEL_S  27
-
-#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0xc4)
-/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
-/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/
-#define RTC_IO_SAR_I2C_SDA_SEL  0x00000003
-#define RTC_IO_SAR_I2C_SDA_SEL_M  ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))
-#define RTC_IO_SAR_I2C_SDA_SEL_V  0x3
-#define RTC_IO_SAR_I2C_SDA_SEL_S  30
-/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
-/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/
-#define RTC_IO_SAR_I2C_SCL_SEL  0x00000003
-#define RTC_IO_SAR_I2C_SCL_SEL_M  ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
-#define RTC_IO_SAR_I2C_SCL_SEL_V  0x3
-#define RTC_IO_SAR_I2C_SCL_SEL_S  28
-/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
-/*description: */
-#define RTC_IO_SAR_DEBUG_BIT_SEL  0x0000001F
-#define RTC_IO_SAR_DEBUG_BIT_SEL_M  ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))
-#define RTC_IO_SAR_DEBUG_BIT_SEL_V  0x1F
-#define RTC_IO_SAR_DEBUG_BIT_SEL_S  23
-
-#define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0xc8)
-/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */
-/*description: date*/
-#define RTC_IO_IO_DATE  0x0FFFFFFF
-#define RTC_IO_IO_DATE_M  ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))
-#define RTC_IO_IO_DATE_V  0xFFFFFFF
-#define RTC_IO_IO_DATE_S  0
-#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160
-
-
-
-
-#endif /*_SOC_RTC_IO_REG_H_ */
-
-
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
+//\r
+// Licensed under the Apache License, Version 2.0 (the "License");\r
+// you may not use this file except in compliance with the License.\r
+// You may obtain a copy of the License at\r
+\r
+//     http://www.apache.org/licenses/LICENSE-2.0\r
+//\r
+// Unless required by applicable law or agreed to in writing, software\r
+// distributed under the License is distributed on an "AS IS" BASIS,\r
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+// See the License for the specific language governing permissions and\r
+// limitations under the License.\r
+#ifndef _SOC_RTC_IO_REG_H_\r
+#define _SOC_RTC_IO_REG_H_\r
+\r
+\r
+#include "soc.h"\r
+#define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)\r
+/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 output value*/\r
+#define RTC_GPIO_OUT_DATA  0x0003FFFF\r
+#define RTC_GPIO_OUT_DATA_M  ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))\r
+#define RTC_GPIO_OUT_DATA_V  0x3FFFF\r
+#define RTC_GPIO_OUT_DATA_S  14\r
+\r
+#define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x4)\r
+/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 output value write 1 to set*/\r
+#define RTC_GPIO_OUT_DATA_W1TS  0x0003FFFF\r
+#define RTC_GPIO_OUT_DATA_W1TS_M  ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))\r
+#define RTC_GPIO_OUT_DATA_W1TS_V  0x3FFFF\r
+#define RTC_GPIO_OUT_DATA_W1TS_S  14\r
+\r
+#define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x8)\r
+/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 output value write 1 to clear*/\r
+#define RTC_GPIO_OUT_DATA_W1TC  0x0003FFFF\r
+#define RTC_GPIO_OUT_DATA_W1TC_M  ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))\r
+#define RTC_GPIO_OUT_DATA_W1TC_V  0x3FFFF\r
+#define RTC_GPIO_OUT_DATA_W1TC_S  14\r
+\r
+#define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0xc)\r
+/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 output enable*/\r
+#define RTC_GPIO_ENABLE  0x0003FFFF\r
+#define RTC_GPIO_ENABLE_M  ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))\r
+#define RTC_GPIO_ENABLE_V  0x3FFFF\r
+#define RTC_GPIO_ENABLE_S  14\r
+\r
+#define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)\r
+/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 output enable write 1 to set*/\r
+#define RTC_GPIO_ENABLE_W1TS  0x0003FFFF\r
+#define RTC_GPIO_ENABLE_W1TS_M  ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))\r
+#define RTC_GPIO_ENABLE_W1TS_V  0x3FFFF\r
+#define RTC_GPIO_ENABLE_W1TS_S  14\r
+\r
+#define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x14)\r
+/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 output enable write 1 to clear*/\r
+#define RTC_GPIO_ENABLE_W1TC  0x0003FFFF\r
+#define RTC_GPIO_ENABLE_W1TC_M  ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))\r
+#define RTC_GPIO_ENABLE_W1TC_V  0x3FFFF\r
+#define RTC_GPIO_ENABLE_W1TC_S  14\r
+\r
+#define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x18)\r
+/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 interrupt status*/\r
+#define RTC_GPIO_STATUS_INT  0x0003FFFF\r
+#define RTC_GPIO_STATUS_INT_M  ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))\r
+#define RTC_GPIO_STATUS_INT_V  0x3FFFF\r
+#define RTC_GPIO_STATUS_INT_S  14\r
+\r
+#define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x1c)\r
+/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 interrupt status write 1 to set*/\r
+#define RTC_GPIO_STATUS_INT_W1TS  0x0003FFFF\r
+#define RTC_GPIO_STATUS_INT_W1TS_M  ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))\r
+#define RTC_GPIO_STATUS_INT_W1TS_V  0x3FFFF\r
+#define RTC_GPIO_STATUS_INT_W1TS_S  14\r
+\r
+#define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)\r
+/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:14] ;default: 0 ; */\r
+/*description: GPIO0~17 interrupt status write 1 to clear*/\r
+#define RTC_GPIO_STATUS_INT_W1TC  0x0003FFFF\r
+#define RTC_GPIO_STATUS_INT_W1TC_M  ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))\r
+#define RTC_GPIO_STATUS_INT_W1TC_V  0x3FFFF\r
+#define RTC_GPIO_STATUS_INT_W1TC_S  14\r
+\r
+#define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x24)\r
+/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:14] ;default:  ; */\r
+/*description: GPIO0~17 input value*/\r
+#define RTC_GPIO_IN_NEXT  0x0003FFFF\r
+#define RTC_GPIO_IN_NEXT_M  ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))\r
+#define RTC_GPIO_IN_NEXT_V  0x3FFFF\r
+#define RTC_GPIO_IN_NEXT_S  14\r
+\r
+#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0x28)\r
+/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN0_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN0_INT_TYPE_M  ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))\r
+#define RTC_GPIO_PIN0_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN0_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN0_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN0_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN0_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN0_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0x2c)\r
+/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN1_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN1_INT_TYPE_M  ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))\r
+#define RTC_GPIO_PIN1_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN1_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN1_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN1_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN1_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN1_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0x30)\r
+/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN2_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN2_INT_TYPE_M  ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))\r
+#define RTC_GPIO_PIN2_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN2_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN2_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN2_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN2_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN2_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0x34)\r
+/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN3_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN3_INT_TYPE_M  ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))\r
+#define RTC_GPIO_PIN3_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN3_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN3_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN3_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN3_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN3_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0x38)\r
+/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN4_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN4_INT_TYPE_M  ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))\r
+#define RTC_GPIO_PIN4_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN4_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN4_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN4_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN4_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN4_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0x3c)\r
+/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN5_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN5_INT_TYPE_M  ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))\r
+#define RTC_GPIO_PIN5_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN5_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN5_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN5_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN5_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN5_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x40)\r
+/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN6_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN6_INT_TYPE_M  ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))\r
+#define RTC_GPIO_PIN6_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN6_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN6_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN6_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN6_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN6_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x44)\r
+/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN7_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN7_INT_TYPE_M  ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))\r
+#define RTC_GPIO_PIN7_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN7_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN7_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN7_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN7_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN7_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x48)\r
+/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN8_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN8_INT_TYPE_M  ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))\r
+#define RTC_GPIO_PIN8_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN8_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN8_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN8_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN8_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN8_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x4c)\r
+/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN9_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN9_INT_TYPE_M  ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))\r
+#define RTC_GPIO_PIN9_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN9_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN9_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN9_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN9_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN9_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x50)\r
+/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN10_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN10_INT_TYPE_M  ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))\r
+#define RTC_GPIO_PIN10_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN10_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN10_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN10_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN10_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN10_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x54)\r
+/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN11_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN11_INT_TYPE_M  ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))\r
+#define RTC_GPIO_PIN11_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN11_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN11_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN11_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN11_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN11_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x58)\r
+/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN12_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN12_INT_TYPE_M  ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))\r
+#define RTC_GPIO_PIN12_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN12_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN12_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN12_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN12_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN12_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x5c)\r
+/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN13_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN13_INT_TYPE_M  ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))\r
+#define RTC_GPIO_PIN13_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN13_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN13_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN13_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN13_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN13_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x60)\r
+/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN14_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN14_INT_TYPE_M  ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))\r
+#define RTC_GPIO_PIN14_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN14_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN14_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN14_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN14_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN14_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x64)\r
+/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN15_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN15_INT_TYPE_M  ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))\r
+#define RTC_GPIO_PIN15_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN15_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN15_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN15_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN15_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN15_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x68)\r
+/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN16_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN16_INT_TYPE_M  ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))\r
+#define RTC_GPIO_PIN16_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN16_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN16_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN16_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN16_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN16_PAD_DRIVER_S  2\r
+\r
+#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x6c)\r
+/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */\r
+/*description: GPIO wake up enable  only available in light sleep*/\r
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))\r
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))\r
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V  0x1\r
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S  10\r
+/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */\r
+/*description: if set to 0: GPIO interrupt disable  if set to 1: rising edge\r
+ trigger  if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger  if set to 5: high level trigger*/\r
+#define RTC_GPIO_PIN17_INT_TYPE  0x00000007\r
+#define RTC_GPIO_PIN17_INT_TYPE_M  ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))\r
+#define RTC_GPIO_PIN17_INT_TYPE_V  0x7\r
+#define RTC_GPIO_PIN17_INT_TYPE_S  7\r
+/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */\r
+/*description: if set to 0: normal output  if set to 1: open drain*/\r
+#define RTC_GPIO_PIN17_PAD_DRIVER  (BIT(2))\r
+#define RTC_GPIO_PIN17_PAD_DRIVER_M  (BIT(2))\r
+#define RTC_GPIO_PIN17_PAD_DRIVER_V  0x1\r
+#define RTC_GPIO_PIN17_PAD_DRIVER_S  2\r
+\r
+#define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x70)\r
+/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */\r
+/*description: */\r
+#define RTC_IO_DEBUG_12M_NO_GATING  (BIT(25))\r
+#define RTC_IO_DEBUG_12M_NO_GATING_M  (BIT(25))\r
+#define RTC_IO_DEBUG_12M_NO_GATING_V  0x1\r
+#define RTC_IO_DEBUG_12M_NO_GATING_S  25\r
+/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */\r
+/*description: */\r
+#define RTC_IO_DEBUG_SEL4  0x0000001F\r
+#define RTC_IO_DEBUG_SEL4_M  ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))\r
+#define RTC_IO_DEBUG_SEL4_V  0x1F\r
+#define RTC_IO_DEBUG_SEL4_S  20\r
+/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */\r
+/*description: */\r
+#define RTC_IO_DEBUG_SEL3  0x0000001F\r
+#define RTC_IO_DEBUG_SEL3_M  ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))\r
+#define RTC_IO_DEBUG_SEL3_V  0x1F\r
+#define RTC_IO_DEBUG_SEL3_S  15\r
+/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */\r
+/*description: */\r
+#define RTC_IO_DEBUG_SEL2  0x0000001F\r
+#define RTC_IO_DEBUG_SEL2_M  ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))\r
+#define RTC_IO_DEBUG_SEL2_V  0x1F\r
+#define RTC_IO_DEBUG_SEL2_S  10\r
+/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */\r
+/*description: */\r
+#define RTC_IO_DEBUG_SEL1  0x0000001F\r
+#define RTC_IO_DEBUG_SEL1_M  ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))\r
+#define RTC_IO_DEBUG_SEL1_V  0x1F\r
+#define RTC_IO_DEBUG_SEL1_S  5\r
+/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */\r
+/*description: */\r
+#define RTC_IO_DEBUG_SEL0  0x0000001F\r
+#define RTC_IO_DEBUG_SEL0_M  ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))\r
+#define RTC_IO_DEBUG_SEL0_V  0x1F\r
+#define RTC_IO_DEBUG_SEL0_S  0\r
+\r
+#define RTC_IO_DIG_PAD_HOLD_REG          (DR_REG_RTCIO_BASE + 0x74)\r
+/* RTC_IO_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 1'd0 ; */\r
+/*description: select the digital pad hold value.*/\r
+#define RTC_IO_DIG_PAD_HOLD  0xFFFFFFFF\r
+#define RTC_IO_DIG_PAD_HOLD_M  ((RTC_IO_DIG_PAD_HOLD_V)<<(RTC_IO_DIG_PAD_HOLD_S))\r
+#define RTC_IO_DIG_PAD_HOLD_V  0xFFFFFFFF\r
+#define RTC_IO_DIG_PAD_HOLD_S  0\r
+\r
+#define RTC_IO_HALL_SENS_REG          (DR_REG_RTCIO_BASE + 0x78)\r
+/* RTC_IO_XPD_HALL : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: Power on hall sensor and connect to VP and VN*/\r
+#define RTC_IO_XPD_HALL  (BIT(31))\r
+#define RTC_IO_XPD_HALL_M  (BIT(31))\r
+#define RTC_IO_XPD_HALL_V  0x1\r
+#define RTC_IO_XPD_HALL_S  31\r
+/* RTC_IO_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'd0 ; */\r
+/*description: Reverse phase of hall sensor*/\r
+#define RTC_IO_HALL_PHASE  (BIT(30))\r
+#define RTC_IO_HALL_PHASE_M  (BIT(30))\r
+#define RTC_IO_HALL_PHASE_V  0x1\r
+#define RTC_IO_HALL_PHASE_S  30\r
+\r
+#define RTC_IO_SENSOR_PADS_REG          (DR_REG_RTCIO_BASE + 0x7c)\r
+/* RTC_IO_SENSE1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_SENSE1_HOLD  (BIT(31))\r
+#define RTC_IO_SENSE1_HOLD_M  (BIT(31))\r
+#define RTC_IO_SENSE1_HOLD_V  0x1\r
+#define RTC_IO_SENSE1_HOLD_S  31\r
+/* RTC_IO_SENSE2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_SENSE2_HOLD  (BIT(30))\r
+#define RTC_IO_SENSE2_HOLD_M  (BIT(30))\r
+#define RTC_IO_SENSE2_HOLD_V  0x1\r
+#define RTC_IO_SENSE2_HOLD_S  30\r
+/* RTC_IO_SENSE3_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_SENSE3_HOLD  (BIT(29))\r
+#define RTC_IO_SENSE3_HOLD_M  (BIT(29))\r
+#define RTC_IO_SENSE3_HOLD_V  0x1\r
+#define RTC_IO_SENSE3_HOLD_S  29\r
+/* RTC_IO_SENSE4_HOLD : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_SENSE4_HOLD  (BIT(28))\r
+#define RTC_IO_SENSE4_HOLD_M  (BIT(28))\r
+#define RTC_IO_SENSE4_HOLD_V  0x1\r
+#define RTC_IO_SENSE4_HOLD_S  28\r
+/* RTC_IO_SENSE1_MUX_SEL : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_SENSE1_MUX_SEL  (BIT(27))\r
+#define RTC_IO_SENSE1_MUX_SEL_M  (BIT(27))\r
+#define RTC_IO_SENSE1_MUX_SEL_V  0x1\r
+#define RTC_IO_SENSE1_MUX_SEL_S  27\r
+/* RTC_IO_SENSE2_MUX_SEL : R/W ;bitpos:[26] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_SENSE2_MUX_SEL  (BIT(26))\r
+#define RTC_IO_SENSE2_MUX_SEL_M  (BIT(26))\r
+#define RTC_IO_SENSE2_MUX_SEL_V  0x1\r
+#define RTC_IO_SENSE2_MUX_SEL_S  26\r
+/* RTC_IO_SENSE3_MUX_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_SENSE3_MUX_SEL  (BIT(25))\r
+#define RTC_IO_SENSE3_MUX_SEL_M  (BIT(25))\r
+#define RTC_IO_SENSE3_MUX_SEL_V  0x1\r
+#define RTC_IO_SENSE3_MUX_SEL_S  25\r
+/* RTC_IO_SENSE4_MUX_SEL : R/W ;bitpos:[24] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_SENSE4_MUX_SEL  (BIT(24))\r
+#define RTC_IO_SENSE4_MUX_SEL_M  (BIT(24))\r
+#define RTC_IO_SENSE4_MUX_SEL_V  0x1\r
+#define RTC_IO_SENSE4_MUX_SEL_S  24\r
+/* RTC_IO_SENSE1_FUN_SEL : R/W ;bitpos:[23:22] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_SENSE1_FUN_SEL  0x00000003\r
+#define RTC_IO_SENSE1_FUN_SEL_M  ((RTC_IO_SENSE1_FUN_SEL_V)<<(RTC_IO_SENSE1_FUN_SEL_S))\r
+#define RTC_IO_SENSE1_FUN_SEL_V  0x3\r
+#define RTC_IO_SENSE1_FUN_SEL_S  22\r
+/* RTC_IO_SENSE1_SLP_SEL : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_SENSE1_SLP_SEL  (BIT(21))\r
+#define RTC_IO_SENSE1_SLP_SEL_M  (BIT(21))\r
+#define RTC_IO_SENSE1_SLP_SEL_V  0x1\r
+#define RTC_IO_SENSE1_SLP_SEL_S  21\r
+/* RTC_IO_SENSE1_SLP_IE : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_SENSE1_SLP_IE  (BIT(20))\r
+#define RTC_IO_SENSE1_SLP_IE_M  (BIT(20))\r
+#define RTC_IO_SENSE1_SLP_IE_V  0x1\r
+#define RTC_IO_SENSE1_SLP_IE_S  20\r
+/* RTC_IO_SENSE1_FUN_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_SENSE1_FUN_IE  (BIT(19))\r
+#define RTC_IO_SENSE1_FUN_IE_M  (BIT(19))\r
+#define RTC_IO_SENSE1_FUN_IE_V  0x1\r
+#define RTC_IO_SENSE1_FUN_IE_S  19\r
+/* RTC_IO_SENSE2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_SENSE2_FUN_SEL  0x00000003\r
+#define RTC_IO_SENSE2_FUN_SEL_M  ((RTC_IO_SENSE2_FUN_SEL_V)<<(RTC_IO_SENSE2_FUN_SEL_S))\r
+#define RTC_IO_SENSE2_FUN_SEL_V  0x3\r
+#define RTC_IO_SENSE2_FUN_SEL_S  17\r
+/* RTC_IO_SENSE2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_SENSE2_SLP_SEL  (BIT(16))\r
+#define RTC_IO_SENSE2_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_SENSE2_SLP_SEL_V  0x1\r
+#define RTC_IO_SENSE2_SLP_SEL_S  16\r
+/* RTC_IO_SENSE2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_SENSE2_SLP_IE  (BIT(15))\r
+#define RTC_IO_SENSE2_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_SENSE2_SLP_IE_V  0x1\r
+#define RTC_IO_SENSE2_SLP_IE_S  15\r
+/* RTC_IO_SENSE2_FUN_IE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_SENSE2_FUN_IE  (BIT(14))\r
+#define RTC_IO_SENSE2_FUN_IE_M  (BIT(14))\r
+#define RTC_IO_SENSE2_FUN_IE_V  0x1\r
+#define RTC_IO_SENSE2_FUN_IE_S  14\r
+/* RTC_IO_SENSE3_FUN_SEL : R/W ;bitpos:[13:12] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_SENSE3_FUN_SEL  0x00000003\r
+#define RTC_IO_SENSE3_FUN_SEL_M  ((RTC_IO_SENSE3_FUN_SEL_V)<<(RTC_IO_SENSE3_FUN_SEL_S))\r
+#define RTC_IO_SENSE3_FUN_SEL_V  0x3\r
+#define RTC_IO_SENSE3_FUN_SEL_S  12\r
+/* RTC_IO_SENSE3_SLP_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_SENSE3_SLP_SEL  (BIT(11))\r
+#define RTC_IO_SENSE3_SLP_SEL_M  (BIT(11))\r
+#define RTC_IO_SENSE3_SLP_SEL_V  0x1\r
+#define RTC_IO_SENSE3_SLP_SEL_S  11\r
+/* RTC_IO_SENSE3_SLP_IE : R/W ;bitpos:[10] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_SENSE3_SLP_IE  (BIT(10))\r
+#define RTC_IO_SENSE3_SLP_IE_M  (BIT(10))\r
+#define RTC_IO_SENSE3_SLP_IE_V  0x1\r
+#define RTC_IO_SENSE3_SLP_IE_S  10\r
+/* RTC_IO_SENSE3_FUN_IE : R/W ;bitpos:[9] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_SENSE3_FUN_IE  (BIT(9))\r
+#define RTC_IO_SENSE3_FUN_IE_M  (BIT(9))\r
+#define RTC_IO_SENSE3_FUN_IE_V  0x1\r
+#define RTC_IO_SENSE3_FUN_IE_S  9\r
+/* RTC_IO_SENSE4_FUN_SEL : R/W ;bitpos:[8:7] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_SENSE4_FUN_SEL  0x00000003\r
+#define RTC_IO_SENSE4_FUN_SEL_M  ((RTC_IO_SENSE4_FUN_SEL_V)<<(RTC_IO_SENSE4_FUN_SEL_S))\r
+#define RTC_IO_SENSE4_FUN_SEL_V  0x3\r
+#define RTC_IO_SENSE4_FUN_SEL_S  7\r
+/* RTC_IO_SENSE4_SLP_SEL : R/W ;bitpos:[6] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_SENSE4_SLP_SEL  (BIT(6))\r
+#define RTC_IO_SENSE4_SLP_SEL_M  (BIT(6))\r
+#define RTC_IO_SENSE4_SLP_SEL_V  0x1\r
+#define RTC_IO_SENSE4_SLP_SEL_S  6\r
+/* RTC_IO_SENSE4_SLP_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_SENSE4_SLP_IE  (BIT(5))\r
+#define RTC_IO_SENSE4_SLP_IE_M  (BIT(5))\r
+#define RTC_IO_SENSE4_SLP_IE_V  0x1\r
+#define RTC_IO_SENSE4_SLP_IE_S  5\r
+/* RTC_IO_SENSE4_FUN_IE : R/W ;bitpos:[4] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_SENSE4_FUN_IE  (BIT(4))\r
+#define RTC_IO_SENSE4_FUN_IE_M  (BIT(4))\r
+#define RTC_IO_SENSE4_FUN_IE_V  0x1\r
+#define RTC_IO_SENSE4_FUN_IE_S  4\r
+\r
+#define RTC_IO_ADC_PAD_REG          (DR_REG_RTCIO_BASE + 0x80)\r
+/* RTC_IO_ADC1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_ADC1_HOLD  (BIT(31))\r
+#define RTC_IO_ADC1_HOLD_M  (BIT(31))\r
+#define RTC_IO_ADC1_HOLD_V  0x1\r
+#define RTC_IO_ADC1_HOLD_S  31\r
+/* RTC_IO_ADC2_HOLD : R/W ;bitpos:[30] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_ADC2_HOLD  (BIT(30))\r
+#define RTC_IO_ADC2_HOLD_M  (BIT(30))\r
+#define RTC_IO_ADC2_HOLD_V  0x1\r
+#define RTC_IO_ADC2_HOLD_S  30\r
+/* RTC_IO_ADC1_MUX_SEL : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_ADC1_MUX_SEL  (BIT(29))\r
+#define RTC_IO_ADC1_MUX_SEL_M  (BIT(29))\r
+#define RTC_IO_ADC1_MUX_SEL_V  0x1\r
+#define RTC_IO_ADC1_MUX_SEL_S  29\r
+/* RTC_IO_ADC2_MUX_SEL : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_ADC2_MUX_SEL  (BIT(28))\r
+#define RTC_IO_ADC2_MUX_SEL_M  (BIT(28))\r
+#define RTC_IO_ADC2_MUX_SEL_V  0x1\r
+#define RTC_IO_ADC2_MUX_SEL_S  28\r
+/* RTC_IO_ADC1_FUN_SEL : R/W ;bitpos:[27:26] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_ADC1_FUN_SEL  0x00000003\r
+#define RTC_IO_ADC1_FUN_SEL_M  ((RTC_IO_ADC1_FUN_SEL_V)<<(RTC_IO_ADC1_FUN_SEL_S))\r
+#define RTC_IO_ADC1_FUN_SEL_V  0x3\r
+#define RTC_IO_ADC1_FUN_SEL_S  26\r
+/* RTC_IO_ADC1_SLP_SEL : R/W ;bitpos:[25] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_ADC1_SLP_SEL  (BIT(25))\r
+#define RTC_IO_ADC1_SLP_SEL_M  (BIT(25))\r
+#define RTC_IO_ADC1_SLP_SEL_V  0x1\r
+#define RTC_IO_ADC1_SLP_SEL_S  25\r
+/* RTC_IO_ADC1_SLP_IE : R/W ;bitpos:[24] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_ADC1_SLP_IE  (BIT(24))\r
+#define RTC_IO_ADC1_SLP_IE_M  (BIT(24))\r
+#define RTC_IO_ADC1_SLP_IE_V  0x1\r
+#define RTC_IO_ADC1_SLP_IE_S  24\r
+/* RTC_IO_ADC1_FUN_IE : R/W ;bitpos:[23] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_ADC1_FUN_IE  (BIT(23))\r
+#define RTC_IO_ADC1_FUN_IE_M  (BIT(23))\r
+#define RTC_IO_ADC1_FUN_IE_V  0x1\r
+#define RTC_IO_ADC1_FUN_IE_S  23\r
+/* RTC_IO_ADC2_FUN_SEL : R/W ;bitpos:[22:21] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_ADC2_FUN_SEL  0x00000003\r
+#define RTC_IO_ADC2_FUN_SEL_M  ((RTC_IO_ADC2_FUN_SEL_V)<<(RTC_IO_ADC2_FUN_SEL_S))\r
+#define RTC_IO_ADC2_FUN_SEL_V  0x3\r
+#define RTC_IO_ADC2_FUN_SEL_S  21\r
+/* RTC_IO_ADC2_SLP_SEL : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_ADC2_SLP_SEL  (BIT(20))\r
+#define RTC_IO_ADC2_SLP_SEL_M  (BIT(20))\r
+#define RTC_IO_ADC2_SLP_SEL_V  0x1\r
+#define RTC_IO_ADC2_SLP_SEL_S  20\r
+/* RTC_IO_ADC2_SLP_IE : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_ADC2_SLP_IE  (BIT(19))\r
+#define RTC_IO_ADC2_SLP_IE_M  (BIT(19))\r
+#define RTC_IO_ADC2_SLP_IE_V  0x1\r
+#define RTC_IO_ADC2_SLP_IE_S  19\r
+/* RTC_IO_ADC2_FUN_IE : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_ADC2_FUN_IE  (BIT(18))\r
+#define RTC_IO_ADC2_FUN_IE_M  (BIT(18))\r
+#define RTC_IO_ADC2_FUN_IE_V  0x1\r
+#define RTC_IO_ADC2_FUN_IE_S  18\r
+\r
+#define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0x84)\r
+/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_PDAC1_DRV  0x00000003\r
+#define RTC_IO_PDAC1_DRV_M  ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))\r
+#define RTC_IO_PDAC1_DRV_V  0x3\r
+#define RTC_IO_PDAC1_DRV_S  30\r
+/* RTC_IO_PDAC1_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_PDAC1_HOLD  (BIT(29))\r
+#define RTC_IO_PDAC1_HOLD_M  (BIT(29))\r
+#define RTC_IO_PDAC1_HOLD_V  0x1\r
+#define RTC_IO_PDAC1_HOLD_S  29\r
+/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_PDAC1_RDE  (BIT(28))\r
+#define RTC_IO_PDAC1_RDE_M  (BIT(28))\r
+#define RTC_IO_PDAC1_RDE_V  0x1\r
+#define RTC_IO_PDAC1_RDE_S  28\r
+/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_PDAC1_RUE  (BIT(27))\r
+#define RTC_IO_PDAC1_RUE_M  (BIT(27))\r
+#define RTC_IO_PDAC1_RUE_V  0x1\r
+#define RTC_IO_PDAC1_RUE_S  27\r
+/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
+/*description: PAD DAC1 control code.*/\r
+#define RTC_IO_PDAC1_DAC  0x000000FF\r
+#define RTC_IO_PDAC1_DAC_M  ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))\r
+#define RTC_IO_PDAC1_DAC_V  0xFF\r
+#define RTC_IO_PDAC1_DAC_S  19\r
+/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
+/*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power\r
+ on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/\r
+#define RTC_IO_PDAC1_XPD_DAC  (BIT(18))\r
+#define RTC_IO_PDAC1_XPD_DAC_M  (BIT(18))\r
+#define RTC_IO_PDAC1_XPD_DAC_V  0x1\r
+#define RTC_IO_PDAC1_XPD_DAC_S  18\r
+/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_PDAC1_MUX_SEL  (BIT(17))\r
+#define RTC_IO_PDAC1_MUX_SEL_M  (BIT(17))\r
+#define RTC_IO_PDAC1_MUX_SEL_V  0x1\r
+#define RTC_IO_PDAC1_MUX_SEL_S  17\r
+/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_PDAC1_FUN_SEL  0x00000003\r
+#define RTC_IO_PDAC1_FUN_SEL_M  ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))\r
+#define RTC_IO_PDAC1_FUN_SEL_V  0x3\r
+#define RTC_IO_PDAC1_FUN_SEL_S  15\r
+/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_PDAC1_SLP_SEL  (BIT(14))\r
+#define RTC_IO_PDAC1_SLP_SEL_M  (BIT(14))\r
+#define RTC_IO_PDAC1_SLP_SEL_V  0x1\r
+#define RTC_IO_PDAC1_SLP_SEL_S  14\r
+/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_PDAC1_SLP_IE  (BIT(13))\r
+#define RTC_IO_PDAC1_SLP_IE_M  (BIT(13))\r
+#define RTC_IO_PDAC1_SLP_IE_V  0x1\r
+#define RTC_IO_PDAC1_SLP_IE_S  13\r
+/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_PDAC1_SLP_OE  (BIT(12))\r
+#define RTC_IO_PDAC1_SLP_OE_M  (BIT(12))\r
+#define RTC_IO_PDAC1_SLP_OE_V  0x1\r
+#define RTC_IO_PDAC1_SLP_OE_S  12\r
+/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_PDAC1_FUN_IE  (BIT(11))\r
+#define RTC_IO_PDAC1_FUN_IE_M  (BIT(11))\r
+#define RTC_IO_PDAC1_FUN_IE_V  0x1\r
+#define RTC_IO_PDAC1_FUN_IE_S  11\r
+/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */\r
+/*description: Power on DAC1. Usually  we need to tristate PDAC1 if we power\r
+ on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/\r
+#define RTC_IO_PDAC1_DAC_XPD_FORCE  (BIT(10))\r
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_M  (BIT(10))\r
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_V  0x1\r
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_S  10\r
+\r
+#define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0x88)\r
+/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_PDAC2_DRV  0x00000003\r
+#define RTC_IO_PDAC2_DRV_M  ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))\r
+#define RTC_IO_PDAC2_DRV_V  0x3\r
+#define RTC_IO_PDAC2_DRV_S  30\r
+/* RTC_IO_PDAC2_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_PDAC2_HOLD  (BIT(29))\r
+#define RTC_IO_PDAC2_HOLD_M  (BIT(29))\r
+#define RTC_IO_PDAC2_HOLD_V  0x1\r
+#define RTC_IO_PDAC2_HOLD_S  29\r
+/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_PDAC2_RDE  (BIT(28))\r
+#define RTC_IO_PDAC2_RDE_M  (BIT(28))\r
+#define RTC_IO_PDAC2_RDE_V  0x1\r
+#define RTC_IO_PDAC2_RDE_S  28\r
+/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_PDAC2_RUE  (BIT(27))\r
+#define RTC_IO_PDAC2_RUE_M  (BIT(27))\r
+#define RTC_IO_PDAC2_RUE_V  0x1\r
+#define RTC_IO_PDAC2_RUE_S  27\r
+/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
+/*description: PAD DAC2 control code.*/\r
+#define RTC_IO_PDAC2_DAC  0x000000FF\r
+#define RTC_IO_PDAC2_DAC_M  ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))\r
+#define RTC_IO_PDAC2_DAC_V  0xFF\r
+#define RTC_IO_PDAC2_DAC_S  19\r
+/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
+/*description: Power on DAC2. Usually  we need to tristate PDAC1 if we power\r
+ on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/\r
+#define RTC_IO_PDAC2_XPD_DAC  (BIT(18))\r
+#define RTC_IO_PDAC2_XPD_DAC_M  (BIT(18))\r
+#define RTC_IO_PDAC2_XPD_DAC_V  0x1\r
+#define RTC_IO_PDAC2_XPD_DAC_S  18\r
+/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_PDAC2_MUX_SEL  (BIT(17))\r
+#define RTC_IO_PDAC2_MUX_SEL_M  (BIT(17))\r
+#define RTC_IO_PDAC2_MUX_SEL_V  0x1\r
+#define RTC_IO_PDAC2_MUX_SEL_S  17\r
+/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_PDAC2_FUN_SEL  0x00000003\r
+#define RTC_IO_PDAC2_FUN_SEL_M  ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))\r
+#define RTC_IO_PDAC2_FUN_SEL_V  0x3\r
+#define RTC_IO_PDAC2_FUN_SEL_S  15\r
+/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_PDAC2_SLP_SEL  (BIT(14))\r
+#define RTC_IO_PDAC2_SLP_SEL_M  (BIT(14))\r
+#define RTC_IO_PDAC2_SLP_SEL_V  0x1\r
+#define RTC_IO_PDAC2_SLP_SEL_S  14\r
+/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_PDAC2_SLP_IE  (BIT(13))\r
+#define RTC_IO_PDAC2_SLP_IE_M  (BIT(13))\r
+#define RTC_IO_PDAC2_SLP_IE_V  0x1\r
+#define RTC_IO_PDAC2_SLP_IE_S  13\r
+/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_PDAC2_SLP_OE  (BIT(12))\r
+#define RTC_IO_PDAC2_SLP_OE_M  (BIT(12))\r
+#define RTC_IO_PDAC2_SLP_OE_V  0x1\r
+#define RTC_IO_PDAC2_SLP_OE_S  12\r
+/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_PDAC2_FUN_IE  (BIT(11))\r
+#define RTC_IO_PDAC2_FUN_IE_M  (BIT(11))\r
+#define RTC_IO_PDAC2_FUN_IE_V  0x1\r
+#define RTC_IO_PDAC2_FUN_IE_S  11\r
+/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */\r
+/*description: Power on DAC2. Usually  we need to tristate PDAC2 if we power\r
+ on the DAC  i.e. IE=0  OE=0  RDE=0  RUE=0*/\r
+#define RTC_IO_PDAC2_DAC_XPD_FORCE  (BIT(10))\r
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_M  (BIT(10))\r
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_V  0x1\r
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_S  10\r
+\r
+#define RTC_IO_XTAL_32K_PAD_REG          (DR_REG_RTCIO_BASE + 0x8c)\r
+/* RTC_IO_X32N_DRV : R/W ;bitpos:[31:30] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_X32N_DRV  0x00000003\r
+#define RTC_IO_X32N_DRV_M  ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))\r
+#define RTC_IO_X32N_DRV_V  0x3\r
+#define RTC_IO_X32N_DRV_S  30\r
+/* RTC_IO_X32N_HOLD : R/W ;bitpos:[29] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_X32N_HOLD  (BIT(29))\r
+#define RTC_IO_X32N_HOLD_M  (BIT(29))\r
+#define RTC_IO_X32N_HOLD_V  0x1\r
+#define RTC_IO_X32N_HOLD_S  29\r
+/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_X32N_RDE  (BIT(28))\r
+#define RTC_IO_X32N_RDE_M  (BIT(28))\r
+#define RTC_IO_X32N_RDE_V  0x1\r
+#define RTC_IO_X32N_RDE_S  28\r
+/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_X32N_RUE  (BIT(27))\r
+#define RTC_IO_X32N_RUE_M  (BIT(27))\r
+#define RTC_IO_X32N_RUE_V  0x1\r
+#define RTC_IO_X32N_RUE_S  27\r
+/* RTC_IO_X32P_DRV : R/W ;bitpos:[26:25] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_X32P_DRV  0x00000003\r
+#define RTC_IO_X32P_DRV_M  ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))\r
+#define RTC_IO_X32P_DRV_V  0x3\r
+#define RTC_IO_X32P_DRV_S  25\r
+/* RTC_IO_X32P_HOLD : R/W ;bitpos:[24] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_X32P_HOLD  (BIT(24))\r
+#define RTC_IO_X32P_HOLD_M  (BIT(24))\r
+#define RTC_IO_X32P_HOLD_V  0x1\r
+#define RTC_IO_X32P_HOLD_S  24\r
+/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_X32P_RDE  (BIT(23))\r
+#define RTC_IO_X32P_RDE_M  (BIT(23))\r
+#define RTC_IO_X32P_RDE_V  0x1\r
+#define RTC_IO_X32P_RDE_S  23\r
+/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_X32P_RUE  (BIT(22))\r
+#define RTC_IO_X32P_RUE_M  (BIT(22))\r
+#define RTC_IO_X32P_RUE_V  0x1\r
+#define RTC_IO_X32P_RUE_S  22\r
+/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */\r
+/*description: 32K XTAL bias current DAC.*/\r
+#define RTC_IO_DAC_XTAL_32K  0x00000003\r
+#define RTC_IO_DAC_XTAL_32K_M  ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))\r
+#define RTC_IO_DAC_XTAL_32K_V  0x3\r
+#define RTC_IO_DAC_XTAL_32K_S  20\r
+/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Power up 32kHz crystal oscillator*/\r
+#define RTC_IO_XPD_XTAL_32K  (BIT(19))\r
+#define RTC_IO_XPD_XTAL_32K_M  (BIT(19))\r
+#define RTC_IO_XPD_XTAL_32K_V  0x1\r
+#define RTC_IO_XPD_XTAL_32K_S  19\r
+/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_X32N_MUX_SEL  (BIT(18))\r
+#define RTC_IO_X32N_MUX_SEL_M  (BIT(18))\r
+#define RTC_IO_X32N_MUX_SEL_V  0x1\r
+#define RTC_IO_X32N_MUX_SEL_S  18\r
+/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_X32P_MUX_SEL  (BIT(17))\r
+#define RTC_IO_X32P_MUX_SEL_M  (BIT(17))\r
+#define RTC_IO_X32P_MUX_SEL_V  0x1\r
+#define RTC_IO_X32P_MUX_SEL_S  17\r
+/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[16:15] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_X32N_FUN_SEL  0x00000003\r
+#define RTC_IO_X32N_FUN_SEL_M  ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))\r
+#define RTC_IO_X32N_FUN_SEL_V  0x3\r
+#define RTC_IO_X32N_FUN_SEL_S  15\r
+/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_X32N_SLP_SEL  (BIT(14))\r
+#define RTC_IO_X32N_SLP_SEL_M  (BIT(14))\r
+#define RTC_IO_X32N_SLP_SEL_V  0x1\r
+#define RTC_IO_X32N_SLP_SEL_S  14\r
+/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_X32N_SLP_IE  (BIT(13))\r
+#define RTC_IO_X32N_SLP_IE_M  (BIT(13))\r
+#define RTC_IO_X32N_SLP_IE_V  0x1\r
+#define RTC_IO_X32N_SLP_IE_S  13\r
+/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_X32N_SLP_OE  (BIT(12))\r
+#define RTC_IO_X32N_SLP_OE_M  (BIT(12))\r
+#define RTC_IO_X32N_SLP_OE_V  0x1\r
+#define RTC_IO_X32N_SLP_OE_S  12\r
+/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_X32N_FUN_IE  (BIT(11))\r
+#define RTC_IO_X32N_FUN_IE_M  (BIT(11))\r
+#define RTC_IO_X32N_FUN_IE_V  0x1\r
+#define RTC_IO_X32N_FUN_IE_S  11\r
+/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_X32P_FUN_SEL  0x00000003\r
+#define RTC_IO_X32P_FUN_SEL_M  ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))\r
+#define RTC_IO_X32P_FUN_SEL_V  0x3\r
+#define RTC_IO_X32P_FUN_SEL_S  9\r
+/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[8] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_X32P_SLP_SEL  (BIT(8))\r
+#define RTC_IO_X32P_SLP_SEL_M  (BIT(8))\r
+#define RTC_IO_X32P_SLP_SEL_V  0x1\r
+#define RTC_IO_X32P_SLP_SEL_S  8\r
+/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[7] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_X32P_SLP_IE  (BIT(7))\r
+#define RTC_IO_X32P_SLP_IE_M  (BIT(7))\r
+#define RTC_IO_X32P_SLP_IE_V  0x1\r
+#define RTC_IO_X32P_SLP_IE_S  7\r
+/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[6] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_X32P_SLP_OE  (BIT(6))\r
+#define RTC_IO_X32P_SLP_OE_M  (BIT(6))\r
+#define RTC_IO_X32P_SLP_OE_V  0x1\r
+#define RTC_IO_X32P_SLP_OE_S  6\r
+/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_X32P_FUN_IE  (BIT(5))\r
+#define RTC_IO_X32P_FUN_IE_M  (BIT(5))\r
+#define RTC_IO_X32P_FUN_IE_V  0x1\r
+#define RTC_IO_X32P_FUN_IE_S  5\r
+/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */\r
+/*description: 32K XTAL resistor bias control.*/\r
+#define RTC_IO_DRES_XTAL_32K  0x00000003\r
+#define RTC_IO_DRES_XTAL_32K_M  ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))\r
+#define RTC_IO_DRES_XTAL_32K_V  0x3\r
+#define RTC_IO_DRES_XTAL_32K_S  3\r
+/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */\r
+/*description: 32K XTAL self-bias reference control.*/\r
+#define RTC_IO_DBIAS_XTAL_32K  0x00000003\r
+#define RTC_IO_DBIAS_XTAL_32K_M  ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))\r
+#define RTC_IO_DBIAS_XTAL_32K_V  0x3\r
+#define RTC_IO_DBIAS_XTAL_32K_S  1\r
+\r
+#define RTC_IO_TOUCH_CFG_REG          (DR_REG_RTCIO_BASE + 0x90)\r
+/* RTC_IO_TOUCH_XPD_BIAS : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: touch sensor bias power on.*/\r
+#define RTC_IO_TOUCH_XPD_BIAS  (BIT(31))\r
+#define RTC_IO_TOUCH_XPD_BIAS_M  (BIT(31))\r
+#define RTC_IO_TOUCH_XPD_BIAS_V  0x1\r
+#define RTC_IO_TOUCH_XPD_BIAS_S  31\r
+/* RTC_IO_TOUCH_DREFH : R/W ;bitpos:[30:29] ;default: 2'b11 ; */\r
+/*description: touch sensor saw wave top voltage.*/\r
+#define RTC_IO_TOUCH_DREFH  0x00000003\r
+#define RTC_IO_TOUCH_DREFH_M  ((RTC_IO_TOUCH_DREFH_V)<<(RTC_IO_TOUCH_DREFH_S))\r
+#define RTC_IO_TOUCH_DREFH_V  0x3\r
+#define RTC_IO_TOUCH_DREFH_S  29\r
+/* RTC_IO_TOUCH_DREFL : R/W ;bitpos:[28:27] ;default: 2'b00 ; */\r
+/*description: touch sensor saw wave bottom voltage.*/\r
+#define RTC_IO_TOUCH_DREFL  0x00000003\r
+#define RTC_IO_TOUCH_DREFL_M  ((RTC_IO_TOUCH_DREFL_V)<<(RTC_IO_TOUCH_DREFL_S))\r
+#define RTC_IO_TOUCH_DREFL_V  0x3\r
+#define RTC_IO_TOUCH_DREFL_S  27\r
+/* RTC_IO_TOUCH_DRANGE : R/W ;bitpos:[26:25] ;default: 2'b11 ; */\r
+/*description: touch sensor saw wave voltage range.*/\r
+#define RTC_IO_TOUCH_DRANGE  0x00000003\r
+#define RTC_IO_TOUCH_DRANGE_M  ((RTC_IO_TOUCH_DRANGE_V)<<(RTC_IO_TOUCH_DRANGE_S))\r
+#define RTC_IO_TOUCH_DRANGE_V  0x3\r
+#define RTC_IO_TOUCH_DRANGE_S  25\r
+/* RTC_IO_TOUCH_DCUR : R/W ;bitpos:[24:23] ;default: 2'b00 ; */\r
+/*description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When\r
+ BIAS_SLEEP  this setting is available*/\r
+#define RTC_IO_TOUCH_DCUR  0x00000003\r
+#define RTC_IO_TOUCH_DCUR_M  ((RTC_IO_TOUCH_DCUR_V)<<(RTC_IO_TOUCH_DCUR_S))\r
+#define RTC_IO_TOUCH_DCUR_V  0x3\r
+#define RTC_IO_TOUCH_DCUR_S  23\r
+\r
+#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x94)\r
+/* RTC_IO_TOUCH_PAD0_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD0_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD0_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD0_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD0_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD0_DRV_M  ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))\r
+#define RTC_IO_TOUCH_PAD0_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD0_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD0_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD0_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD0_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD0_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD0_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD0_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD0_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD0_DAC_M  ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))\r
+#define RTC_IO_TOUCH_PAD0_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD0_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD0_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD0_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD0_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_START_S  22\r
+/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD0_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD0_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD0_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD0_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD0_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD0_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_M  ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD0_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD0_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD0_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD0_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD0_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD0_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD0_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD0_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD0_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD0_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD0_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4*/\r
+#define RTC_IO_TOUCH_PAD0_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD0_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x98)\r
+/* RTC_IO_TOUCH_PAD1_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: */\r
+#define RTC_IO_TOUCH_PAD1_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD1_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD1_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD1_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD1_DRV_M  ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))\r
+#define RTC_IO_TOUCH_PAD1_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD1_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD1_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD1_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD1_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD1_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD1_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD1_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD1_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD1_DAC_M  ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))\r
+#define RTC_IO_TOUCH_PAD1_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD1_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD1_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD1_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD1_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_START_S  22\r
+/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD1_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD1_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD1_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD1_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD1_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD1_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_M  ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD1_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD1_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD1_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD1_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD1_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD1_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD1_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD1_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD1_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD1_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD1_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0*/\r
+#define RTC_IO_TOUCH_PAD1_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD1_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x9c)\r
+/* RTC_IO_TOUCH_PAD2_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD2_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD2_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD2_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD2_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD2_DRV_M  ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))\r
+#define RTC_IO_TOUCH_PAD2_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD2_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD2_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD2_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD2_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD2_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD2_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD2_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD2_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD2_DAC_M  ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))\r
+#define RTC_IO_TOUCH_PAD2_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD2_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD2_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD2_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD2_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_START_S  22\r
+/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD2_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD2_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD2_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD2_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD2_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD2_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_M  ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD2_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD2_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD2_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD2_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD2_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD2_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD2_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD2_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD2_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD2_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD2_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2*/\r
+#define RTC_IO_TOUCH_PAD2_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD2_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0xa0)\r
+/* RTC_IO_TOUCH_PAD3_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD3_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD3_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD3_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD3_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD3_DRV_M  ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))\r
+#define RTC_IO_TOUCH_PAD3_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD3_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD3_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD3_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD3_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD3_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD3_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD3_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD3_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD3_DAC_M  ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))\r
+#define RTC_IO_TOUCH_PAD3_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD3_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD3_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD3_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD3_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_START_S  22\r
+/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD3_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD3_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD3_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD3_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD3_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD3_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_M  ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD3_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD3_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD3_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD3_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD3_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD3_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD3_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD3_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD3_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD3_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD3_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO*/\r
+#define RTC_IO_TOUCH_PAD3_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD3_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0xa4)\r
+/* RTC_IO_TOUCH_PAD4_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD4_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD4_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD4_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD4_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD4_DRV_M  ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))\r
+#define RTC_IO_TOUCH_PAD4_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD4_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD4_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD4_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD4_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD4_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD4_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD4_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD4_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD4_DAC_M  ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))\r
+#define RTC_IO_TOUCH_PAD4_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD4_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD4_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD4_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD4_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_START_S  22\r
+/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD4_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD4_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD4_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD4_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD4_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD4_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_M  ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD4_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD4_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD4_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD4_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD4_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD4_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD4_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD4_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD4_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD4_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD4_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK*/\r
+#define RTC_IO_TOUCH_PAD4_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD4_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0xa8)\r
+/* RTC_IO_TOUCH_PAD5_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD5_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD5_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD5_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD5_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD5_DRV_M  ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))\r
+#define RTC_IO_TOUCH_PAD5_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD5_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD5_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD5_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD5_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD5_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD5_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD5_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD5_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD5_DAC_M  ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))\r
+#define RTC_IO_TOUCH_PAD5_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD5_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD5_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD5_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD5_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_START_S  22\r
+/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD5_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD5_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD5_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD5_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD5_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD5_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_M  ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD5_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD5_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD5_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD5_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD5_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD5_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD5_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD5_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD5_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD5_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD5_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI*/\r
+#define RTC_IO_TOUCH_PAD5_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD5_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0xac)\r
+/* RTC_IO_TOUCH_PAD6_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD6_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD6_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD6_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD6_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD6_DRV_M  ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))\r
+#define RTC_IO_TOUCH_PAD6_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD6_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD6_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD6_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD6_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD6_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD6_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD6_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD6_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD6_DAC_M  ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))\r
+#define RTC_IO_TOUCH_PAD6_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD6_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD6_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD6_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD6_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_START_S  22\r
+/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD6_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD6_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD6_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD6_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD6_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD6_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_M  ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD6_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD6_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD6_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD6_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD6_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD6_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD6_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD6_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD6_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD6_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD6_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS*/\r
+#define RTC_IO_TOUCH_PAD6_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD6_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0xb0)\r
+/* RTC_IO_TOUCH_PAD7_HOLD : R/W ;bitpos:[31] ;default: 1'd0 ; */\r
+/*description: hold the current value of the output when setting the hold to Ò1Ó*/\r
+#define RTC_IO_TOUCH_PAD7_HOLD  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD7_HOLD_M  (BIT(31))\r
+#define RTC_IO_TOUCH_PAD7_HOLD_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_HOLD_S  31\r
+/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */\r
+/*description: the driver strength of the pad*/\r
+#define RTC_IO_TOUCH_PAD7_DRV  0x00000003\r
+#define RTC_IO_TOUCH_PAD7_DRV_M  ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))\r
+#define RTC_IO_TOUCH_PAD7_DRV_V  0x3\r
+#define RTC_IO_TOUCH_PAD7_DRV_S  29\r
+/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
+/*description: the pull down enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD7_RDE  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD7_RDE_M  (BIT(28))\r
+#define RTC_IO_TOUCH_PAD7_RDE_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_RDE_S  28\r
+/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
+/*description: the pull up enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD7_RUE  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD7_RUE_M  (BIT(27))\r
+#define RTC_IO_TOUCH_PAD7_RUE_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_RUE_S  27\r
+/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD7_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD7_DAC_M  ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))\r
+#define RTC_IO_TOUCH_PAD7_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD7_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD7_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD7_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD7_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_START_S  22\r
+/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD7_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD7_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD7_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD7_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: Ò1Ó select the digital function  Ó0Óslection the rtc function*/\r
+#define RTC_IO_TOUCH_PAD7_MUX_SEL  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_S  19\r
+/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */\r
+/*description: the functional selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD7_FUN_SEL  0x00000003\r
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_M  ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))\r
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_V  0x3\r
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_S  17\r
+/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */\r
+/*description: the sleep status selection signal of the pad*/\r
+#define RTC_IO_TOUCH_PAD7_SLP_SEL  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_M  (BIT(16))\r
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_S  16\r
+/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD7_SLP_IE  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD7_SLP_IE_M  (BIT(15))\r
+#define RTC_IO_TOUCH_PAD7_SLP_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_SLP_IE_S  15\r
+/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */\r
+/*description: the output enable of the pad in sleep status*/\r
+#define RTC_IO_TOUCH_PAD7_SLP_OE  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD7_SLP_OE_M  (BIT(14))\r
+#define RTC_IO_TOUCH_PAD7_SLP_OE_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_SLP_OE_S  14\r
+/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */\r
+/*description: the input enable of the pad*/\r
+#define RTC_IO_TOUCH_PAD7_FUN_IE  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD7_FUN_IE_M  (BIT(13))\r
+#define RTC_IO_TOUCH_PAD7_FUN_IE_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_FUN_IE_S  13\r
+/* RTC_IO_TOUCH_PAD7_TO_GPIO : R/W ;bitpos:[12] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27*/\r
+#define RTC_IO_TOUCH_PAD7_TO_GPIO  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_M  (BIT(12))\r
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD7_TO_GPIO_S  12\r
+\r
+#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0xb4)\r
+/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD8_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD8_DAC_M  ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))\r
+#define RTC_IO_TOUCH_PAD8_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD8_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD8_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD8_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD8_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD8_START_S  22\r
+/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD8_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD8_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD8_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD8_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD8_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD8_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/\r
+#define RTC_IO_TOUCH_PAD8_TO_GPIO  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD8_TO_GPIO_S  19\r
+\r
+#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0xb8)\r
+/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */\r
+/*description: touch sensor slope control. 3-bit for each touch panel  default 100.*/\r
+#define RTC_IO_TOUCH_PAD9_DAC  0x00000007\r
+#define RTC_IO_TOUCH_PAD9_DAC_M  ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))\r
+#define RTC_IO_TOUCH_PAD9_DAC_V  0x7\r
+#define RTC_IO_TOUCH_PAD9_DAC_S  23\r
+/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */\r
+/*description: start touch sensor.*/\r
+#define RTC_IO_TOUCH_PAD9_START  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD9_START_M  (BIT(22))\r
+#define RTC_IO_TOUCH_PAD9_START_V  0x1\r
+#define RTC_IO_TOUCH_PAD9_START_S  22\r
+/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */\r
+/*description: default touch sensor tie option. 0: tie low  1: tie high.*/\r
+#define RTC_IO_TOUCH_PAD9_TIE_OPT  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_M  (BIT(21))\r
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_V  0x1\r
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_S  21\r
+/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */\r
+/*description: touch sensor power on.*/\r
+#define RTC_IO_TOUCH_PAD9_XPD  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD9_XPD_M  (BIT(20))\r
+#define RTC_IO_TOUCH_PAD9_XPD_V  0x1\r
+#define RTC_IO_TOUCH_PAD9_XPD_S  20\r
+/* RTC_IO_TOUCH_PAD9_TO_GPIO : R/W ;bitpos:[19] ;default: 1'd0 ; */\r
+/*description: connect the rtc pad input to digital pad input Ó0Ó is availbale*/\r
+#define RTC_IO_TOUCH_PAD9_TO_GPIO  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_M  (BIT(19))\r
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_V  0x1\r
+#define RTC_IO_TOUCH_PAD9_TO_GPIO_S  19\r
+\r
+#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0xbc)\r
+/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */\r
+/*description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17*/\r
+#define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F\r
+#define RTC_IO_EXT_WAKEUP0_SEL_M  ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))\r
+#define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F\r
+#define RTC_IO_EXT_WAKEUP0_SEL_S  27\r
+\r
+#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0xc0)\r
+/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */\r
+/*description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select\r
+ GPIO2 ...Ò17Ó select GPIO17*/\r
+#define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F\r
+#define RTC_IO_XTL_EXT_CTR_SEL_M  ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))\r
+#define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F\r
+#define RTC_IO_XTL_EXT_CTR_SEL_S  27\r
+\r
+#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0xc4)\r
+/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */\r
+/*description: Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda*/\r
+#define RTC_IO_SAR_I2C_SDA_SEL  0x00000003\r
+#define RTC_IO_SAR_I2C_SDA_SEL_M  ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))\r
+#define RTC_IO_SAR_I2C_SDA_SEL_V  0x3\r
+#define RTC_IO_SAR_I2C_SDA_SEL_S  30\r
+/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */\r
+/*description: Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk*/\r
+#define RTC_IO_SAR_I2C_SCL_SEL  0x00000003\r
+#define RTC_IO_SAR_I2C_SCL_SEL_M  ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))\r
+#define RTC_IO_SAR_I2C_SCL_SEL_V  0x3\r
+#define RTC_IO_SAR_I2C_SCL_SEL_S  28\r
+/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */\r
+/*description: */\r
+#define RTC_IO_SAR_DEBUG_BIT_SEL  0x0000001F\r
+#define RTC_IO_SAR_DEBUG_BIT_SEL_M  ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))\r
+#define RTC_IO_SAR_DEBUG_BIT_SEL_V  0x1F\r
+#define RTC_IO_SAR_DEBUG_BIT_SEL_S  23\r
+\r
+#define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0xc8)\r
+/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1603160 ; */\r
+/*description: date*/\r
+#define RTC_IO_IO_DATE  0x0FFFFFFF\r
+#define RTC_IO_IO_DATE_M  ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))\r
+#define RTC_IO_IO_DATE_V  0xFFFFFFF\r
+#define RTC_IO_IO_DATE_S  0\r
+#define RTC_IO_RTC_IO_DATE_VERSION 0x1703160\r
+\r
+\r
+\r
+\r
+#endif /*_SOC_RTC_IO_REG_H_ */\r
+\r
+\r

diff --git a/components/esp32/include/soc/saradc_reg.h b/components/esp32/include/soc/saradc_reg.h
deleted file mode 100644 (file)
index 5190329..0000000
--- a/components/esp32/include/soc/saradc_reg.h
+++ /dev/null
@@ -1,1047 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD\r
-//\r
-// Licensed under the Apache License, Version 2.0 (the "License");\r
-// you may not use this file except in compliance with the License.\r
-// You may obtain a copy of the License at\r
-\r
-//     http://www.apache.org/licenses/LICENSE-2.0\r
-//\r
-// Unless required by applicable law or agreed to in writing, software\r
-// distributed under the License is distributed on an "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
-// See the License for the specific language governing permissions and\r
-// limitations under the License.\r
-#ifndef _SOC_SARADC_REG_H_\r
-#define _SOC_SARADC_REG_H_\r
-\r
-\r
-#include "soc.h"\r
-#define SARADC_SAR_READ_CTRL_REG          (DR_REG_SARADC_BASE + 0x0000)\r
-/* SARADC_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */\r
-/*description: Invert SAR ADC1 data*/\r
-#define SARADC_SAR1_DATA_INV  (BIT(28))\r
-#define SARADC_SAR1_DATA_INV_M  (BIT(28))\r
-#define SARADC_SAR1_DATA_INV_V  0x1\r
-#define SARADC_SAR1_DATA_INV_S  28\r
-/* SARADC_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */\r
-/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL  0: SAR ADC1 controlled by RTC ADC1 CTRL*/\r
-#define SARADC_SAR1_DIG_FORCE  (BIT(27))\r
-#define SARADC_SAR1_DIG_FORCE_M  (BIT(27))\r
-#define SARADC_SAR1_DIG_FORCE_V  0x1\r
-#define SARADC_SAR1_DIG_FORCE_S  27\r
-/* SARADC_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
-/*description: */\r
-#define SARADC_SAR1_SAMPLE_NUM  0x000000FF\r
-#define SARADC_SAR1_SAMPLE_NUM_M  ((SARADC_SAR1_SAMPLE_NUM_V)<<(SARADC_SAR1_SAMPLE_NUM_S))\r
-#define SARADC_SAR1_SAMPLE_NUM_V  0xFF\r
-#define SARADC_SAR1_SAMPLE_NUM_S  19\r
-/* SARADC_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */\r
-/*description: */\r
-#define SARADC_SAR1_CLK_GATED  (BIT(18))\r
-#define SARADC_SAR1_CLK_GATED_M  (BIT(18))\r
-#define SARADC_SAR1_CLK_GATED_V  0x1\r
-#define SARADC_SAR1_CLK_GATED_S  18\r
-/* SARADC_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */\r
-/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width\r
-  11: for 12-bit width*/\r
-#define SARADC_SAR1_SAMPLE_BIT  0x00000003\r
-#define SARADC_SAR1_SAMPLE_BIT_M  ((SARADC_SAR1_SAMPLE_BIT_V)<<(SARADC_SAR1_SAMPLE_BIT_S))\r
-#define SARADC_SAR1_SAMPLE_BIT_V  0x3\r
-#define SARADC_SAR1_SAMPLE_BIT_S  16\r
-/* SARADC_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */\r
-/*description: sample cycles for SAR ADC1*/\r
-#define SARADC_SAR1_SAMPLE_CYCLE  0x000000FF\r
-#define SARADC_SAR1_SAMPLE_CYCLE_M  ((SARADC_SAR1_SAMPLE_CYCLE_V)<<(SARADC_SAR1_SAMPLE_CYCLE_S))\r
-#define SARADC_SAR1_SAMPLE_CYCLE_V  0xFF\r
-#define SARADC_SAR1_SAMPLE_CYCLE_S  8\r
-/* SARADC_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */\r
-/*description: clock divider*/\r
-#define SARADC_SAR1_CLK_DIV  0x000000FF\r
-#define SARADC_SAR1_CLK_DIV_M  ((SARADC_SAR1_CLK_DIV_V)<<(SARADC_SAR1_CLK_DIV_S))\r
-#define SARADC_SAR1_CLK_DIV_V  0xFF\r
-#define SARADC_SAR1_CLK_DIV_S  0\r
-\r
-#define SARADC_SAR_READ_STATUS1_REG          (DR_REG_SARADC_BASE + 0x0004)\r
-/* SARADC_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define SARADC_SAR1_READER_STATUS  0xFFFFFFFF\r
-#define SARADC_SAR1_READER_STATUS_M  ((SARADC_SAR1_READER_STATUS_V)<<(SARADC_SAR1_READER_STATUS_S))\r
-#define SARADC_SAR1_READER_STATUS_V  0xFFFFFFFF\r
-#define SARADC_SAR1_READER_STATUS_S  0\r
-\r
-#define SARADC_SAR_MEAS_WAIT1_REG          (DR_REG_SARADC_BASE + 0x0008)\r
-/* SARADC_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */\r
-/*description: */\r
-#define SARADC_SAR_AMP_WAIT2  0x0000FFFF\r
-#define SARADC_SAR_AMP_WAIT2_M  ((SARADC_SAR_AMP_WAIT2_V)<<(SARADC_SAR_AMP_WAIT2_S))\r
-#define SARADC_SAR_AMP_WAIT2_V  0xFFFF\r
-#define SARADC_SAR_AMP_WAIT2_S  16\r
-/* SARADC_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */\r
-/*description: */\r
-#define SARADC_SAR_AMP_WAIT1  0x0000FFFF\r
-#define SARADC_SAR_AMP_WAIT1_M  ((SARADC_SAR_AMP_WAIT1_V)<<(SARADC_SAR_AMP_WAIT1_S))\r
-#define SARADC_SAR_AMP_WAIT1_V  0xFFFF\r
-#define SARADC_SAR_AMP_WAIT1_S  0\r
-\r
-#define SARADC_SAR_MEAS_WAIT2_REG          (DR_REG_SARADC_BASE + 0x000c)\r
-/* SARADC_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */\r
-/*description: */\r
-#define SARADC_SAR2_RSTB_WAIT  0x000000FF\r
-#define SARADC_SAR2_RSTB_WAIT_M  ((SARADC_SAR2_RSTB_WAIT_V)<<(SARADC_SAR2_RSTB_WAIT_S))\r
-#define SARADC_SAR2_RSTB_WAIT_V  0xFF\r
-#define SARADC_SAR2_RSTB_WAIT_S  20\r
-/* SARADC_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */\r
-/*description: */\r
-#define SARADC_FORCE_XPD_SAR  0x00000003\r
-#define SARADC_FORCE_XPD_SAR_M  ((SARADC_FORCE_XPD_SAR_V)<<(SARADC_FORCE_XPD_SAR_S))\r
-#define SARADC_FORCE_XPD_SAR_V  0x3\r
-#define SARADC_FORCE_XPD_SAR_S  18\r
-/* SARADC_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */\r
-/*description: */\r
-#define SARADC_FORCE_XPD_AMP  0x00000003\r
-#define SARADC_FORCE_XPD_AMP_M  ((SARADC_FORCE_XPD_AMP_V)<<(SARADC_FORCE_XPD_AMP_S))\r
-#define SARADC_FORCE_XPD_AMP_V  0x3\r
-#define SARADC_FORCE_XPD_AMP_S  16\r
-/* SARADC_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */\r
-/*description: */\r
-#define SARADC_SAR_AMP_WAIT3  0x0000FFFF\r
-#define SARADC_SAR_AMP_WAIT3_M  ((SARADC_SAR_AMP_WAIT3_V)<<(SARADC_SAR_AMP_WAIT3_S))\r
-#define SARADC_SAR_AMP_WAIT3_V  0xFFFF\r
-#define SARADC_SAR_AMP_WAIT3_S  0\r
-\r
-#define SARADC_SAR_MEAS_CTRL_REG          (DR_REG_SARADC_BASE + 0x0010)\r
-/* SARADC_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */\r
-/*description: */\r
-#define SARADC_SAR2_XPD_WAIT  0x000000FF\r
-#define SARADC_SAR2_XPD_WAIT_M  ((SARADC_SAR2_XPD_WAIT_V)<<(SARADC_SAR2_XPD_WAIT_S))\r
-#define SARADC_SAR2_XPD_WAIT_V  0xFF\r
-#define SARADC_SAR2_XPD_WAIT_S  24\r
-/* SARADC_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */\r
-/*description: */\r
-#define SARADC_SAR_RSTB_FSM  0x0000000F\r
-#define SARADC_SAR_RSTB_FSM_M  ((SARADC_SAR_RSTB_FSM_V)<<(SARADC_SAR_RSTB_FSM_S))\r
-#define SARADC_SAR_RSTB_FSM_V  0xF\r
-#define SARADC_SAR_RSTB_FSM_S  20\r
-/* SARADC_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */\r
-/*description: */\r
-#define SARADC_XPD_SAR_FSM  0x0000000F\r
-#define SARADC_XPD_SAR_FSM_M  ((SARADC_XPD_SAR_FSM_V)<<(SARADC_XPD_SAR_FSM_S))\r
-#define SARADC_XPD_SAR_FSM_V  0xF\r
-#define SARADC_XPD_SAR_FSM_S  16\r
-/* SARADC_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */\r
-/*description: */\r
-#define SARADC_AMP_SHORT_REF_GND_FSM  0x0000000F\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_M  ((SARADC_AMP_SHORT_REF_GND_FSM_V)<<(SARADC_AMP_SHORT_REF_GND_FSM_S))\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_V  0xF\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_S  12\r
-/* SARADC_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */\r
-/*description: */\r
-#define SARADC_AMP_SHORT_REF_FSM  0x0000000F\r
-#define SARADC_AMP_SHORT_REF_FSM_M  ((SARADC_AMP_SHORT_REF_FSM_V)<<(SARADC_AMP_SHORT_REF_FSM_S))\r
-#define SARADC_AMP_SHORT_REF_FSM_V  0xF\r
-#define SARADC_AMP_SHORT_REF_FSM_S  8\r
-/* SARADC_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */\r
-/*description: */\r
-#define SARADC_AMP_RST_FB_FSM  0x0000000F\r
-#define SARADC_AMP_RST_FB_FSM_M  ((SARADC_AMP_RST_FB_FSM_V)<<(SARADC_AMP_RST_FB_FSM_S))\r
-#define SARADC_AMP_RST_FB_FSM_V  0xF\r
-#define SARADC_AMP_RST_FB_FSM_S  4\r
-/* SARADC_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */\r
-/*description: */\r
-#define SARADC_XPD_SAR_AMP_FSM  0x0000000F\r
-#define SARADC_XPD_SAR_AMP_FSM_M  ((SARADC_XPD_SAR_AMP_FSM_V)<<(SARADC_XPD_SAR_AMP_FSM_S))\r
-#define SARADC_XPD_SAR_AMP_FSM_V  0xF\r
-#define SARADC_XPD_SAR_AMP_FSM_S  0\r
-\r
-#define SARADC_SAR_READ_STATUS2_REG          (DR_REG_SARADC_BASE + 0x0014)\r
-/* SARADC_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define SARADC_SAR2_READER_STATUS  0xFFFFFFFF\r
-#define SARADC_SAR2_READER_STATUS_M  ((SARADC_SAR2_READER_STATUS_V)<<(SARADC_SAR2_READER_STATUS_S))\r
-#define SARADC_SAR2_READER_STATUS_V  0xFFFFFFFF\r
-#define SARADC_SAR2_READER_STATUS_S  0\r
-\r
-#define SARADC_ULP_CP_SLEEP_CYC0_REG          (DR_REG_SARADC_BASE + 0x0018)\r
-/* SARADC_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */\r
-/*description: sleep cycles for ULP-coprocessor timer*/\r
-#define SARADC_SLEEP_CYCLES_S0  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S0_M  ((SARADC_SLEEP_CYCLES_S0_V)<<(SARADC_SLEEP_CYCLES_S0_S))\r
-#define SARADC_SLEEP_CYCLES_S0_V  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S0_S  0\r
-\r
-#define SARADC_ULP_CP_SLEEP_CYC1_REG          (DR_REG_SARADC_BASE + 0x001c)\r
-/* SARADC_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */\r
-/*description: */\r
-#define SARADC_SLEEP_CYCLES_S1  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S1_M  ((SARADC_SLEEP_CYCLES_S1_V)<<(SARADC_SLEEP_CYCLES_S1_S))\r
-#define SARADC_SLEEP_CYCLES_S1_V  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S1_S  0\r
-\r
-#define SARADC_ULP_CP_SLEEP_CYC2_REG          (DR_REG_SARADC_BASE + 0x0020)\r
-/* SARADC_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */\r
-/*description: */\r
-#define SARADC_SLEEP_CYCLES_S2  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S2_M  ((SARADC_SLEEP_CYCLES_S2_V)<<(SARADC_SLEEP_CYCLES_S2_S))\r
-#define SARADC_SLEEP_CYCLES_S2_V  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S2_S  0\r
-\r
-#define SARADC_ULP_CP_SLEEP_CYC3_REG          (DR_REG_SARADC_BASE + 0x0024)\r
-/* SARADC_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */\r
-/*description: */\r
-#define SARADC_SLEEP_CYCLES_S3  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S3_M  ((SARADC_SLEEP_CYCLES_S3_V)<<(SARADC_SLEEP_CYCLES_S3_S))\r
-#define SARADC_SLEEP_CYCLES_S3_V  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S3_S  0\r
-\r
-#define SARADC_ULP_CP_SLEEP_CYC4_REG          (DR_REG_SARADC_BASE + 0x0028)\r
-/* SARADC_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */\r
-/*description: */\r
-#define SARADC_SLEEP_CYCLES_S4  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S4_M  ((SARADC_SLEEP_CYCLES_S4_V)<<(SARADC_SLEEP_CYCLES_S4_S))\r
-#define SARADC_SLEEP_CYCLES_S4_V  0xFFFFFFFF\r
-#define SARADC_SLEEP_CYCLES_S4_S  0\r
-\r
-#define SARADC_SAR_START_FORCE_REG          (DR_REG_SARADC_BASE + 0x002c)\r
-/* SARADC_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: N/A*/\r
-#define SARADC_SAR2_PWDET_EN  (BIT(24))\r
-#define SARADC_SAR2_PWDET_EN_M  (BIT(24))\r
-#define SARADC_SAR2_PWDET_EN_V  0x1\r
-#define SARADC_SAR2_PWDET_EN_S  24\r
-/* SARADC_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: stop SAR ADC1 conversion*/\r
-#define SARADC_SAR1_STOP  (BIT(23))\r
-#define SARADC_SAR1_STOP_M  (BIT(23))\r
-#define SARADC_SAR1_STOP_V  0x1\r
-#define SARADC_SAR1_STOP_S  23\r
-/* SARADC_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: stop SAR ADC2 conversion*/\r
-#define SARADC_SAR2_STOP  (BIT(22))\r
-#define SARADC_SAR2_STOP_M  (BIT(22))\r
-#define SARADC_SAR2_STOP_V  0x1\r
-#define SARADC_SAR2_STOP_S  22\r
-/* SARADC_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */\r
-/*description: initialized PC for ULP-coprocessor*/\r
-#define SARADC_PC_INIT  0x000007FF\r
-#define SARADC_PC_INIT_M  ((SARADC_PC_INIT_V)<<(SARADC_PC_INIT_S))\r
-#define SARADC_PC_INIT_V  0x7FF\r
-#define SARADC_PC_INIT_S  11\r
-/* SARADC_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_SARCLK_EN  (BIT(10))\r
-#define SARADC_SARCLK_EN_M  (BIT(10))\r
-#define SARADC_SARCLK_EN_V  0x1\r
-#define SARADC_SARCLK_EN_S  10\r
-/* SARADC_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: Write 1 to start ULP-coprocessor  only active when reg_ulp_cp_force_start_top\r
- = 1*/\r
-#define SARADC_ULP_CP_START_TOP  (BIT(9))\r
-#define SARADC_ULP_CP_START_TOP_M  (BIT(9))\r
-#define SARADC_ULP_CP_START_TOP_V  0x1\r
-#define SARADC_ULP_CP_START_TOP_S  9\r
-/* SARADC_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: 1: ULP-coprocessor is started by SW  0: ULP-coprocessor is started by timer*/\r
-#define SARADC_ULP_CP_FORCE_START_TOP  (BIT(8))\r
-#define SARADC_ULP_CP_FORCE_START_TOP_M  (BIT(8))\r
-#define SARADC_ULP_CP_FORCE_START_TOP_V  0x1\r
-#define SARADC_ULP_CP_FORCE_START_TOP_S  8\r
-/* SARADC_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */\r
-/*description: SAR2_PWDET_CCT  PA power detector capacitance tuning.*/\r
-#define SARADC_SAR2_PWDET_CCT  0x00000007\r
-#define SARADC_SAR2_PWDET_CCT_M  ((SARADC_SAR2_PWDET_CCT_V)<<(SARADC_SAR2_PWDET_CCT_S))\r
-#define SARADC_SAR2_PWDET_CCT_V  0x7\r
-#define SARADC_SAR2_PWDET_CCT_S  5\r
-/* SARADC_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: SAR2_EN_TEST  only active when reg_sar2_dig_force = 0*/\r
-#define SARADC_SAR2_EN_TEST  (BIT(4))\r
-#define SARADC_SAR2_EN_TEST_M  (BIT(4))\r
-#define SARADC_SAR2_EN_TEST_V  0x1\r
-#define SARADC_SAR2_EN_TEST_S  4\r
-/* SARADC_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */\r
-/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/\r
-#define SARADC_SAR2_BIT_WIDTH  0x00000003\r
-#define SARADC_SAR2_BIT_WIDTH_M  ((SARADC_SAR2_BIT_WIDTH_V)<<(SARADC_SAR2_BIT_WIDTH_S))\r
-#define SARADC_SAR2_BIT_WIDTH_V  0x3\r
-#define SARADC_SAR2_BIT_WIDTH_S  2\r
-/* SARADC_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */\r
-/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/\r
-#define SARADC_SAR1_BIT_WIDTH  0x00000003\r
-#define SARADC_SAR1_BIT_WIDTH_M  ((SARADC_SAR1_BIT_WIDTH_V)<<(SARADC_SAR1_BIT_WIDTH_S))\r
-#define SARADC_SAR1_BIT_WIDTH_V  0x3\r
-#define SARADC_SAR1_BIT_WIDTH_S  0\r
-\r
-#define SARADC_SAR_MEM_WR_CTRL_REG          (DR_REG_SARADC_BASE + 0x0030)\r
-/* SARADC_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */\r
-/*description: */\r
-#define SARADC_RTC_MEM_WR_OFFST_CLR  (BIT(22))\r
-#define SARADC_RTC_MEM_WR_OFFST_CLR_M  (BIT(22))\r
-#define SARADC_RTC_MEM_WR_OFFST_CLR_V  0x1\r
-#define SARADC_RTC_MEM_WR_OFFST_CLR_S  22\r
-/* SARADC_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */\r
-/*description: */\r
-#define SARADC_MEM_WR_ADDR_SIZE  0x000007FF\r
-#define SARADC_MEM_WR_ADDR_SIZE_M  ((SARADC_MEM_WR_ADDR_SIZE_V)<<(SARADC_MEM_WR_ADDR_SIZE_S))\r
-#define SARADC_MEM_WR_ADDR_SIZE_V  0x7FF\r
-#define SARADC_MEM_WR_ADDR_SIZE_S  11\r
-/* SARADC_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */\r
-/*description: */\r
-#define SARADC_MEM_WR_ADDR_INIT  0x000007FF\r
-#define SARADC_MEM_WR_ADDR_INIT_M  ((SARADC_MEM_WR_ADDR_INIT_V)<<(SARADC_MEM_WR_ADDR_INIT_S))\r
-#define SARADC_MEM_WR_ADDR_INIT_V  0x7FF\r
-#define SARADC_MEM_WR_ADDR_INIT_S  0\r
-\r
-#define SARADC_SAR_ATTEN1_REG          (DR_REG_SARADC_BASE + 0x0034)\r
-/* SARADC_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */\r
-/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/\r
-#define SARADC_SAR1_ATTEN  0xFFFFFFFF\r
-#define SARADC_SAR1_ATTEN_M  ((SARADC_SAR1_ATTEN_V)<<(SARADC_SAR1_ATTEN_S))\r
-#define SARADC_SAR1_ATTEN_V  0xFFFFFFFF\r
-#define SARADC_SAR1_ATTEN_S  0\r
-\r
-#define SARADC_SAR_ATTEN2_REG          (DR_REG_SARADC_BASE + 0x0038)\r
-/* SARADC_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */\r
-/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/\r
-#define SARADC_SAR2_ATTEN  0xFFFFFFFF\r
-#define SARADC_SAR2_ATTEN_M  ((SARADC_SAR2_ATTEN_V)<<(SARADC_SAR2_ATTEN_S))\r
-#define SARADC_SAR2_ATTEN_V  0xFFFFFFFF\r
-#define SARADC_SAR2_ATTEN_S  0\r
-\r
-#define SARADC_SAR_SLAVE_ADDR1_REG          (DR_REG_SARADC_BASE + 0x003c)\r
-/* SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */\r
-/*description: */\r
-#define SARADC_MEAS_STATUS  0x000000FF\r
-#define SARADC_MEAS_STATUS_M  ((SARADC_MEAS_STATUS_V)<<(SARADC_MEAS_STATUS_S))\r
-#define SARADC_MEAS_STATUS_V  0xFF\r
-#define SARADC_MEAS_STATUS_S  22\r
-/* SARADC_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR0  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR0_M  ((SARADC_I2C_SLAVE_ADDR0_V)<<(SARADC_I2C_SLAVE_ADDR0_S))\r
-#define SARADC_I2C_SLAVE_ADDR0_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR0_S  11\r
-/* SARADC_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR1  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR1_M  ((SARADC_I2C_SLAVE_ADDR1_V)<<(SARADC_I2C_SLAVE_ADDR1_S))\r
-#define SARADC_I2C_SLAVE_ADDR1_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR1_S  0\r
-\r
-#define SARADC_SAR_SLAVE_ADDR2_REG          (DR_REG_SARADC_BASE + 0x0040)\r
-/* SARADC_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR2  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR2_M  ((SARADC_I2C_SLAVE_ADDR2_V)<<(SARADC_I2C_SLAVE_ADDR2_S))\r
-#define SARADC_I2C_SLAVE_ADDR2_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR2_S  11\r
-/* SARADC_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR3  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR3_M  ((SARADC_I2C_SLAVE_ADDR3_V)<<(SARADC_I2C_SLAVE_ADDR3_S))\r
-#define SARADC_I2C_SLAVE_ADDR3_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR3_S  0\r
-\r
-#define SARADC_SAR_SLAVE_ADDR3_REG          (DR_REG_SARADC_BASE + 0x0044)\r
-/* SARADC_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */\r
-/*description: indicate temperature sensor out ready*/\r
-#define SARADC_TSENS_RDY_OUT  (BIT(30))\r
-#define SARADC_TSENS_RDY_OUT_M  (BIT(30))\r
-#define SARADC_TSENS_RDY_OUT_V  0x1\r
-#define SARADC_TSENS_RDY_OUT_S  30\r
-/* SARADC_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */\r
-/*description: temperature sensor data out*/\r
-#define SARADC_TSENS_OUT  0x000000FF\r
-#define SARADC_TSENS_OUT_M  ((SARADC_TSENS_OUT_V)<<(SARADC_TSENS_OUT_S))\r
-#define SARADC_TSENS_OUT_V  0xFF\r
-#define SARADC_TSENS_OUT_S  22\r
-/* SARADC_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR4  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR4_M  ((SARADC_I2C_SLAVE_ADDR4_V)<<(SARADC_I2C_SLAVE_ADDR4_S))\r
-#define SARADC_I2C_SLAVE_ADDR4_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR4_S  11\r
-/* SARADC_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR5  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR5_M  ((SARADC_I2C_SLAVE_ADDR5_V)<<(SARADC_I2C_SLAVE_ADDR5_S))\r
-#define SARADC_I2C_SLAVE_ADDR5_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR5_S  0\r
-\r
-#define SARADC_SAR_SLAVE_ADDR4_REG          (DR_REG_SARADC_BASE + 0x0048)\r
-/* SARADC_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */\r
-/*description: indicate I2C done*/\r
-#define SARADC_I2C_DONE  (BIT(30))\r
-#define SARADC_I2C_DONE_M  (BIT(30))\r
-#define SARADC_I2C_DONE_V  0x1\r
-#define SARADC_I2C_DONE_S  30\r
-/* SARADC_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */\r
-/*description: I2C read data*/\r
-#define SARADC_I2C_RDATA  0x000000FF\r
-#define SARADC_I2C_RDATA_M  ((SARADC_I2C_RDATA_V)<<(SARADC_I2C_RDATA_S))\r
-#define SARADC_I2C_RDATA_V  0xFF\r
-#define SARADC_I2C_RDATA_S  22\r
-/* SARADC_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR6  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR6_M  ((SARADC_I2C_SLAVE_ADDR6_V)<<(SARADC_I2C_SLAVE_ADDR6_S))\r
-#define SARADC_I2C_SLAVE_ADDR6_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR6_S  11\r
-/* SARADC_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */\r
-/*description: */\r
-#define SARADC_I2C_SLAVE_ADDR7  0x000007FF\r
-#define SARADC_I2C_SLAVE_ADDR7_M  ((SARADC_I2C_SLAVE_ADDR7_V)<<(SARADC_I2C_SLAVE_ADDR7_S))\r
-#define SARADC_I2C_SLAVE_ADDR7_V  0x7FF\r
-#define SARADC_I2C_SLAVE_ADDR7_S  0\r
-\r
-#define SARADC_SAR_TSENS_CTRL_REG          (DR_REG_SARADC_BASE + 0x004c)\r
-/* SARADC_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: temperature sensor dump out  only active when reg_tsens_power_up_force = 1*/\r
-#define SARADC_TSENS_DUMP_OUT  (BIT(26))\r
-#define SARADC_TSENS_DUMP_OUT_M  (BIT(26))\r
-#define SARADC_TSENS_DUMP_OUT_V  0x1\r
-#define SARADC_TSENS_DUMP_OUT_S  26\r
-/* SARADC_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: 1: dump out & power up controlled by SW  0: by FSM*/\r
-#define SARADC_TSENS_POWER_UP_FORCE  (BIT(25))\r
-#define SARADC_TSENS_POWER_UP_FORCE_M  (BIT(25))\r
-#define SARADC_TSENS_POWER_UP_FORCE_V  0x1\r
-#define SARADC_TSENS_POWER_UP_FORCE_S  25\r
-/* SARADC_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: temperature sensor power up*/\r
-#define SARADC_TSENS_POWER_UP  (BIT(24))\r
-#define SARADC_TSENS_POWER_UP_M  (BIT(24))\r
-#define SARADC_TSENS_POWER_UP_V  0x1\r
-#define SARADC_TSENS_POWER_UP_S  24\r
-/* SARADC_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */\r
-/*description: temperature sensor clock divider*/\r
-#define SARADC_TSENS_CLK_DIV  0x000000FF\r
-#define SARADC_TSENS_CLK_DIV_M  ((SARADC_TSENS_CLK_DIV_V)<<(SARADC_TSENS_CLK_DIV_S))\r
-#define SARADC_TSENS_CLK_DIV_V  0xFF\r
-#define SARADC_TSENS_CLK_DIV_S  16\r
-/* SARADC_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */\r
-/*description: invert temperature sensor data*/\r
-#define SARADC_TSENS_IN_INV  (BIT(15))\r
-#define SARADC_TSENS_IN_INV_M  (BIT(15))\r
-#define SARADC_TSENS_IN_INV_V  0x1\r
-#define SARADC_TSENS_IN_INV_S  15\r
-/* SARADC_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */\r
-/*description: */\r
-#define SARADC_TSENS_CLK_GATED  (BIT(14))\r
-#define SARADC_TSENS_CLK_GATED_M  (BIT(14))\r
-#define SARADC_TSENS_CLK_GATED_V  0x1\r
-#define SARADC_TSENS_CLK_GATED_S  14\r
-/* SARADC_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */\r
-/*description: */\r
-#define SARADC_TSENS_CLK_INV  (BIT(13))\r
-#define SARADC_TSENS_CLK_INV_M  (BIT(13))\r
-#define SARADC_TSENS_CLK_INV_V  0x1\r
-#define SARADC_TSENS_CLK_INV_S  13\r
-/* SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_TSENS_XPD_FORCE  (BIT(12))\r
-#define SARADC_TSENS_XPD_FORCE_M  (BIT(12))\r
-#define SARADC_TSENS_XPD_FORCE_V  0x1\r
-#define SARADC_TSENS_XPD_FORCE_S  12\r
-/* SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */\r
-/*description: */\r
-#define SARADC_TSENS_XPD_WAIT  0x00000FFF\r
-#define SARADC_TSENS_XPD_WAIT_M  ((SARADC_TSENS_XPD_WAIT_V)<<(SARADC_TSENS_XPD_WAIT_S))\r
-#define SARADC_TSENS_XPD_WAIT_V  0xFFF\r
-#define SARADC_TSENS_XPD_WAIT_S  0\r
-\r
-#define SARADC_SAR_I2C_CTRL_REG          (DR_REG_SARADC_BASE + 0x0050)\r
-/* SARADC_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: 1: I2C started by SW  0: I2C started by FSM*/\r
-#define SARADC_SAR_I2C_START_FORCE  (BIT(29))\r
-#define SARADC_SAR_I2C_START_FORCE_M  (BIT(29))\r
-#define SARADC_SAR_I2C_START_FORCE_V  0x1\r
-#define SARADC_SAR_I2C_START_FORCE_S  29\r
-/* SARADC_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: start I2C  only active when reg_sar_i2c_start_force = 1*/\r
-#define SARADC_SAR_I2C_START  (BIT(28))\r
-#define SARADC_SAR_I2C_START_M  (BIT(28))\r
-#define SARADC_SAR_I2C_START_V  0x1\r
-#define SARADC_SAR_I2C_START_S  28\r
-/* SARADC_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */\r
-/*description: I2C control data  only active when reg_sar_i2c_start_force = 1*/\r
-#define SARADC_SAR_I2C_CTRL  0x0FFFFFFF\r
-#define SARADC_SAR_I2C_CTRL_M  ((SARADC_SAR_I2C_CTRL_V)<<(SARADC_SAR_I2C_CTRL_S))\r
-#define SARADC_SAR_I2C_CTRL_V  0xFFFFFFF\r
-#define SARADC_SAR_I2C_CTRL_S  0\r
-\r
-#define SARADC_SAR_MEAS_START1_REG          (DR_REG_SARADC_BASE + 0x0054)\r
-/* SARADC_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW  0: SAR ADC1\r
- pad enable bitmap is controlled by ULP-coprocessor*/\r
-#define SARADC_SAR1_EN_PAD_FORCE  (BIT(31))\r
-#define SARADC_SAR1_EN_PAD_FORCE_M  (BIT(31))\r
-#define SARADC_SAR1_EN_PAD_FORCE_V  0x1\r
-#define SARADC_SAR1_EN_PAD_FORCE_S  31\r
-/* SARADC_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */\r
-/*description: SAR ADC1 pad enable bitmap  only active when reg_sar1_en_pad_force = 1*/\r
-#define SARADC_SAR1_EN_PAD  0x00000FFF\r
-#define SARADC_SAR1_EN_PAD_M  ((SARADC_SAR1_EN_PAD_V)<<(SARADC_SAR1_EN_PAD_S))\r
-#define SARADC_SAR1_EN_PAD_V  0xFFF\r
-#define SARADC_SAR1_EN_PAD_S  19\r
-/* SARADC_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: 1: SAR ADC1 controller (in RTC) is started by SW  0: SAR ADC1\r
- controller is started by ULP-coprocessor*/\r
-#define SARADC_MEAS1_START_FORCE  (BIT(18))\r
-#define SARADC_MEAS1_START_FORCE_M  (BIT(18))\r
-#define SARADC_MEAS1_START_FORCE_V  0x1\r
-#define SARADC_MEAS1_START_FORCE_S  18\r
-/* SARADC_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: SAR ADC1 controller (in RTC) starts conversion  only active when\r
- reg_meas1_start_force = 1*/\r
-#define SARADC_MEAS1_START_SAR  (BIT(17))\r
-#define SARADC_MEAS1_START_SAR_M  (BIT(17))\r
-#define SARADC_MEAS1_START_SAR_V  0x1\r
-#define SARADC_MEAS1_START_SAR_S  17\r
-/* SARADC_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: SAR ADC1 conversion done indication*/\r
-#define SARADC_MEAS1_DONE_SAR  (BIT(16))\r
-#define SARADC_MEAS1_DONE_SAR_M  (BIT(16))\r
-#define SARADC_MEAS1_DONE_SAR_V  0x1\r
-#define SARADC_MEAS1_DONE_SAR_S  16\r
-/* SARADC_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */\r
-/*description: SAR ADC1 data*/\r
-#define SARADC_MEAS1_DATA_SAR  0x0000FFFF\r
-#define SARADC_MEAS1_DATA_SAR_M  ((SARADC_MEAS1_DATA_SAR_V)<<(SARADC_MEAS1_DATA_SAR_S))\r
-#define SARADC_MEAS1_DATA_SAR_V  0xFFFF\r
-#define SARADC_MEAS1_DATA_SAR_S  0\r
-\r
-#define SARADC_SAR_TOUCH_CTRL1_REG          (DR_REG_SARADC_BASE + 0x0058)\r
-/* SARADC_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: 1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled\r
- by FSM in ULP-coprocessor*/\r
-#define SARADC_HALL_PHASE_FORCE  (BIT(27))\r
-#define SARADC_HALL_PHASE_FORCE_M  (BIT(27))\r
-#define SARADC_HALL_PHASE_FORCE_V  0x1\r
-#define SARADC_HALL_PHASE_FORCE_S  27\r
-/* SARADC_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */\r
-/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by\r
- FSM in ULP-coprocessor*/\r
-#define SARADC_XPD_HALL_FORCE  (BIT(26))\r
-#define SARADC_XPD_HALL_FORCE_M  (BIT(26))\r
-#define SARADC_XPD_HALL_FORCE_V  0x1\r
-#define SARADC_XPD_HALL_FORCE_S  26\r
-/* SARADC_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
-/*description: 1: wakeup interrupt is generated if SET1 is "touched"  0:\r
- wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/\r
-#define SARADC_TOUCH_OUT_1EN  (BIT(25))\r
-#define SARADC_TOUCH_OUT_1EN_M  (BIT(25))\r
-#define SARADC_TOUCH_OUT_1EN_V  0x1\r
-#define SARADC_TOUCH_OUT_1EN_S  25\r
-/* SARADC_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: 1: when the counter is greater then the threshold  the touch\r
- pad is considered as "touched"  0: when the counter is less than the threshold  the touch pad is considered as "touched"*/\r
-#define SARADC_TOUCH_OUT_SEL  (BIT(24))\r
-#define SARADC_TOUCH_OUT_SEL_M  (BIT(24))\r
-#define SARADC_TOUCH_OUT_SEL_V  0x1\r
-#define SARADC_TOUCH_OUT_SEL_S  24\r
-/* SARADC_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */\r
-/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/\r
-#define SARADC_TOUCH_XPD_WAIT  0x000000FF\r
-#define SARADC_TOUCH_XPD_WAIT_M  ((SARADC_TOUCH_XPD_WAIT_V)<<(SARADC_TOUCH_XPD_WAIT_S))\r
-#define SARADC_TOUCH_XPD_WAIT_V  0xFF\r
-#define SARADC_TOUCH_XPD_WAIT_S  16\r
-/* SARADC_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */\r
-/*description: the meas length (in 8MHz)*/\r
-#define SARADC_TOUCH_MEAS_DELAY  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_DELAY_M  ((SARADC_TOUCH_MEAS_DELAY_V)<<(SARADC_TOUCH_MEAS_DELAY_S))\r
-#define SARADC_TOUCH_MEAS_DELAY_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_DELAY_S  0\r
-\r
-#define SARADC_SAR_TOUCH_THRES1_REG          (DR_REG_SARADC_BASE + 0x005c)\r
-/* SARADC_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 0*/\r
-#define SARADC_TOUCH_OUT_TH0  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH0_M  ((SARADC_TOUCH_OUT_TH0_V)<<(SARADC_TOUCH_OUT_TH0_S))\r
-#define SARADC_TOUCH_OUT_TH0_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH0_S  16\r
-/* SARADC_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 1*/\r
-#define SARADC_TOUCH_OUT_TH1  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH1_M  ((SARADC_TOUCH_OUT_TH1_V)<<(SARADC_TOUCH_OUT_TH1_S))\r
-#define SARADC_TOUCH_OUT_TH1_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH1_S  0\r
-\r
-#define SARADC_SAR_TOUCH_THRES2_REG          (DR_REG_SARADC_BASE + 0x0060)\r
-/* SARADC_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 2*/\r
-#define SARADC_TOUCH_OUT_TH2  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH2_M  ((SARADC_TOUCH_OUT_TH2_V)<<(SARADC_TOUCH_OUT_TH2_S))\r
-#define SARADC_TOUCH_OUT_TH2_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH2_S  16\r
-/* SARADC_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 3*/\r
-#define SARADC_TOUCH_OUT_TH3  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH3_M  ((SARADC_TOUCH_OUT_TH3_V)<<(SARADC_TOUCH_OUT_TH3_S))\r
-#define SARADC_TOUCH_OUT_TH3_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH3_S  0\r
-\r
-#define SARADC_SAR_TOUCH_THRES3_REG          (DR_REG_SARADC_BASE + 0x0064)\r
-/* SARADC_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 4*/\r
-#define SARADC_TOUCH_OUT_TH4  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH4_M  ((SARADC_TOUCH_OUT_TH4_V)<<(SARADC_TOUCH_OUT_TH4_S))\r
-#define SARADC_TOUCH_OUT_TH4_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH4_S  16\r
-/* SARADC_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 5*/\r
-#define SARADC_TOUCH_OUT_TH5  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH5_M  ((SARADC_TOUCH_OUT_TH5_V)<<(SARADC_TOUCH_OUT_TH5_S))\r
-#define SARADC_TOUCH_OUT_TH5_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH5_S  0\r
-\r
-#define SARADC_SAR_TOUCH_THRES4_REG          (DR_REG_SARADC_BASE + 0x0068)\r
-/* SARADC_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 6*/\r
-#define SARADC_TOUCH_OUT_TH6  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH6_M  ((SARADC_TOUCH_OUT_TH6_V)<<(SARADC_TOUCH_OUT_TH6_S))\r
-#define SARADC_TOUCH_OUT_TH6_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH6_S  16\r
-/* SARADC_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 7*/\r
-#define SARADC_TOUCH_OUT_TH7  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH7_M  ((SARADC_TOUCH_OUT_TH7_V)<<(SARADC_TOUCH_OUT_TH7_S))\r
-#define SARADC_TOUCH_OUT_TH7_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH7_S  0\r
-\r
-#define SARADC_SAR_TOUCH_THRES5_REG          (DR_REG_SARADC_BASE + 0x006c)\r
-/* SARADC_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 8*/\r
-#define SARADC_TOUCH_OUT_TH8  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH8_M  ((SARADC_TOUCH_OUT_TH8_V)<<(SARADC_TOUCH_OUT_TH8_S))\r
-#define SARADC_TOUCH_OUT_TH8_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH8_S  16\r
-/* SARADC_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the threshold for touch pad 9*/\r
-#define SARADC_TOUCH_OUT_TH9  0x0000FFFF\r
-#define SARADC_TOUCH_OUT_TH9_M  ((SARADC_TOUCH_OUT_TH9_V)<<(SARADC_TOUCH_OUT_TH9_S))\r
-#define SARADC_TOUCH_OUT_TH9_V  0xFFFF\r
-#define SARADC_TOUCH_OUT_TH9_S  0\r
-\r
-#define SARADC_SAR_TOUCH_OUT1_REG          (DR_REG_SARADC_BASE + 0x0070)\r
-/* SARADC_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 0*/\r
-#define SARADC_TOUCH_MEAS_OUT0  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT0_M  ((SARADC_TOUCH_MEAS_OUT0_V)<<(SARADC_TOUCH_MEAS_OUT0_S))\r
-#define SARADC_TOUCH_MEAS_OUT0_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT0_S  16\r
-/* SARADC_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 1*/\r
-#define SARADC_TOUCH_MEAS_OUT1  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT1_M  ((SARADC_TOUCH_MEAS_OUT1_V)<<(SARADC_TOUCH_MEAS_OUT1_S))\r
-#define SARADC_TOUCH_MEAS_OUT1_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT1_S  0\r
-\r
-#define SARADC_SAR_TOUCH_OUT2_REG          (DR_REG_SARADC_BASE + 0x0074)\r
-/* SARADC_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 2*/\r
-#define SARADC_TOUCH_MEAS_OUT2  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT2_M  ((SARADC_TOUCH_MEAS_OUT2_V)<<(SARADC_TOUCH_MEAS_OUT2_S))\r
-#define SARADC_TOUCH_MEAS_OUT2_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT2_S  16\r
-/* SARADC_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 3*/\r
-#define SARADC_TOUCH_MEAS_OUT3  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT3_M  ((SARADC_TOUCH_MEAS_OUT3_V)<<(SARADC_TOUCH_MEAS_OUT3_S))\r
-#define SARADC_TOUCH_MEAS_OUT3_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT3_S  0\r
-\r
-#define SARADC_SAR_TOUCH_OUT3_REG          (DR_REG_SARADC_BASE + 0x0078)\r
-/* SARADC_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 4*/\r
-#define SARADC_TOUCH_MEAS_OUT4  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT4_M  ((SARADC_TOUCH_MEAS_OUT4_V)<<(SARADC_TOUCH_MEAS_OUT4_S))\r
-#define SARADC_TOUCH_MEAS_OUT4_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT4_S  16\r
-/* SARADC_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 5*/\r
-#define SARADC_TOUCH_MEAS_OUT5  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT5_M  ((SARADC_TOUCH_MEAS_OUT5_V)<<(SARADC_TOUCH_MEAS_OUT5_S))\r
-#define SARADC_TOUCH_MEAS_OUT5_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT5_S  0\r
-\r
-#define SARADC_SAR_TOUCH_OUT4_REG          (DR_REG_SARADC_BASE + 0x007c)\r
-/* SARADC_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 6*/\r
-#define SARADC_TOUCH_MEAS_OUT6  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT6_M  ((SARADC_TOUCH_MEAS_OUT6_V)<<(SARADC_TOUCH_MEAS_OUT6_S))\r
-#define SARADC_TOUCH_MEAS_OUT6_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT6_S  16\r
-/* SARADC_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 7*/\r
-#define SARADC_TOUCH_MEAS_OUT7  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT7_M  ((SARADC_TOUCH_MEAS_OUT7_V)<<(SARADC_TOUCH_MEAS_OUT7_S))\r
-#define SARADC_TOUCH_MEAS_OUT7_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT7_S  0\r
-\r
-#define SARADC_SAR_TOUCH_OUT5_REG          (DR_REG_SARADC_BASE + 0x0080)\r
-/* SARADC_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 8*/\r
-#define SARADC_TOUCH_MEAS_OUT8  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT8_M  ((SARADC_TOUCH_MEAS_OUT8_V)<<(SARADC_TOUCH_MEAS_OUT8_S))\r
-#define SARADC_TOUCH_MEAS_OUT8_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT8_S  16\r
-/* SARADC_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */\r
-/*description: the counter for touch pad 9*/\r
-#define SARADC_TOUCH_MEAS_OUT9  0x0000FFFF\r
-#define SARADC_TOUCH_MEAS_OUT9_M  ((SARADC_TOUCH_MEAS_OUT9_V)<<(SARADC_TOUCH_MEAS_OUT9_S))\r
-#define SARADC_TOUCH_MEAS_OUT9_V  0xFFFF\r
-#define SARADC_TOUCH_MEAS_OUT9_S  0\r
-\r
-#define SARADC_SAR_TOUCH_CTRL2_REG          (DR_REG_SARADC_BASE + 0x0084)\r
-/* SARADC_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */\r
-/*description: to clear reg_touch_meas_en*/\r
-#define SARADC_TOUCH_MEAS_EN_CLR  (BIT(30))\r
-#define SARADC_TOUCH_MEAS_EN_CLR_M  (BIT(30))\r
-#define SARADC_TOUCH_MEAS_EN_CLR_V  0x1\r
-#define SARADC_TOUCH_MEAS_EN_CLR_S  30\r
-/* SARADC_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */\r
-/*description: sleep cycles for timer*/\r
-#define SARADC_TOUCH_SLEEP_CYCLES  0x0000FFFF\r
-#define SARADC_TOUCH_SLEEP_CYCLES_M  ((SARADC_TOUCH_SLEEP_CYCLES_V)<<(SARADC_TOUCH_SLEEP_CYCLES_S))\r
-#define SARADC_TOUCH_SLEEP_CYCLES_V  0xFFFF\r
-#define SARADC_TOUCH_SLEEP_CYCLES_S  14\r
-/* SARADC_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */\r
-/*description: 1: to start touch fsm by SW  0: to start touch fsm by timer*/\r
-#define SARADC_TOUCH_START_FORCE  (BIT(13))\r
-#define SARADC_TOUCH_START_FORCE_M  (BIT(13))\r
-#define SARADC_TOUCH_START_FORCE_V  0x1\r
-#define SARADC_TOUCH_START_FORCE_S  13\r
-/* SARADC_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */\r
-/*description: 1: start touch fsm  valid when reg_touch_start_force is set*/\r
-#define SARADC_TOUCH_START_EN  (BIT(12))\r
-#define SARADC_TOUCH_START_EN_M  (BIT(12))\r
-#define SARADC_TOUCH_START_EN_V  0x1\r
-#define SARADC_TOUCH_START_EN_S  12\r
-/* SARADC_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */\r
-/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm  0: TOUCH_START\r
- & TOUCH_XPD is controlled by registers*/\r
-#define SARADC_TOUCH_START_FSM_EN  (BIT(11))\r
-#define SARADC_TOUCH_START_FSM_EN_M  (BIT(11))\r
-#define SARADC_TOUCH_START_FSM_EN_V  0x1\r
-#define SARADC_TOUCH_START_FSM_EN_S  11\r
-/* SARADC_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */\r
-/*description: fsm set 1 to indicate touch touch meas is done*/\r
-#define SARADC_TOUCH_MEAS_DONE  (BIT(10))\r
-#define SARADC_TOUCH_MEAS_DONE_M  (BIT(10))\r
-#define SARADC_TOUCH_MEAS_DONE_V  0x1\r
-#define SARADC_TOUCH_MEAS_DONE_S  10\r
-/* SARADC_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */\r
-/*description: 10-bit register to indicate which pads are "touched"*/\r
-#define SARADC_TOUCH_MEAS_EN  0x000003FF\r
-#define SARADC_TOUCH_MEAS_EN_M  ((SARADC_TOUCH_MEAS_EN_V)<<(SARADC_TOUCH_MEAS_EN_S))\r
-#define SARADC_TOUCH_MEAS_EN_V  0x3FF\r
-#define SARADC_TOUCH_MEAS_EN_S  0\r
-\r
-#define SARADC_SAR_TOUCH_ENABLE_REG          (DR_REG_SARADC_BASE + 0x008c)\r
-/* SARADC_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */\r
-/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is\r
- "touched" only if at least one of touch pad in SET1 is "touched".*/\r
-#define SARADC_TOUCH_PAD_OUTEN1  0x000003FF\r
-#define SARADC_TOUCH_PAD_OUTEN1_M  ((SARADC_TOUCH_PAD_OUTEN1_V)<<(SARADC_TOUCH_PAD_OUTEN1_S))\r
-#define SARADC_TOUCH_PAD_OUTEN1_V  0x3FF\r
-#define SARADC_TOUCH_PAD_OUTEN1_S  20\r
-/* SARADC_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */\r
-/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is\r
- "touched" only if at least one of touch pad in SET2 is "touched".*/\r
-#define SARADC_TOUCH_PAD_OUTEN2  0x000003FF\r
-#define SARADC_TOUCH_PAD_OUTEN2_M  ((SARADC_TOUCH_PAD_OUTEN2_V)<<(SARADC_TOUCH_PAD_OUTEN2_S))\r
-#define SARADC_TOUCH_PAD_OUTEN2_V  0x3FF\r
-#define SARADC_TOUCH_PAD_OUTEN2_S  10\r
-/* SARADC_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */\r
-/*description: Bitmap defining the working set during the measurement.*/\r
-#define SARADC_TOUCH_PAD_WORKEN  0x000003FF\r
-#define SARADC_TOUCH_PAD_WORKEN_M  ((SARADC_TOUCH_PAD_WORKEN_V)<<(SARADC_TOUCH_PAD_WORKEN_S))\r
-#define SARADC_TOUCH_PAD_WORKEN_V  0x3FF\r
-#define SARADC_TOUCH_PAD_WORKEN_S  0\r
-\r
-#define SARADC_SAR_READ_CTRL2_REG          (DR_REG_SARADC_BASE + 0x0090)\r
-/* SARADC_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */\r
-/*description: Invert SAR ADC2 data*/\r
-#define SARADC_SAR2_DATA_INV  (BIT(29))\r
-#define SARADC_SAR2_DATA_INV_M  (BIT(29))\r
-#define SARADC_SAR2_DATA_INV_V  0x1\r
-#define SARADC_SAR2_DATA_INV_S  29\r
-/* SARADC_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */\r
-/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL  0: SAR\r
- ADC2 controlled by RTC ADC2 CTRL*/\r
-#define SARADC_SAR2_DIG_FORCE  (BIT(28))\r
-#define SARADC_SAR2_DIG_FORCE_M  (BIT(28))\r
-#define SARADC_SAR2_DIG_FORCE_V  0x1\r
-#define SARADC_SAR2_DIG_FORCE_S  28\r
-/* SARADC_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_SAR2_PWDET_FORCE  (BIT(27))\r
-#define SARADC_SAR2_PWDET_FORCE_M  (BIT(27))\r
-#define SARADC_SAR2_PWDET_FORCE_V  0x1\r
-#define SARADC_SAR2_PWDET_FORCE_S  27\r
-/* SARADC_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */\r
-/*description: */\r
-#define SARADC_SAR2_SAMPLE_NUM  0x000000FF\r
-#define SARADC_SAR2_SAMPLE_NUM_M  ((SARADC_SAR2_SAMPLE_NUM_V)<<(SARADC_SAR2_SAMPLE_NUM_S))\r
-#define SARADC_SAR2_SAMPLE_NUM_V  0xFF\r
-#define SARADC_SAR2_SAMPLE_NUM_S  19\r
-/* SARADC_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */\r
-/*description: */\r
-#define SARADC_SAR2_CLK_GATED  (BIT(18))\r
-#define SARADC_SAR2_CLK_GATED_M  (BIT(18))\r
-#define SARADC_SAR2_CLK_GATED_V  0x1\r
-#define SARADC_SAR2_CLK_GATED_S  18\r
-/* SARADC_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */\r
-/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width\r
-  11: for 12-bit width*/\r
-#define SARADC_SAR2_SAMPLE_BIT  0x00000003\r
-#define SARADC_SAR2_SAMPLE_BIT_M  ((SARADC_SAR2_SAMPLE_BIT_V)<<(SARADC_SAR2_SAMPLE_BIT_S))\r
-#define SARADC_SAR2_SAMPLE_BIT_V  0x3\r
-#define SARADC_SAR2_SAMPLE_BIT_S  16\r
-/* SARADC_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */\r
-/*description: sample cycles for SAR ADC2*/\r
-#define SARADC_SAR2_SAMPLE_CYCLE  0x000000FF\r
-#define SARADC_SAR2_SAMPLE_CYCLE_M  ((SARADC_SAR2_SAMPLE_CYCLE_V)<<(SARADC_SAR2_SAMPLE_CYCLE_S))\r
-#define SARADC_SAR2_SAMPLE_CYCLE_V  0xFF\r
-#define SARADC_SAR2_SAMPLE_CYCLE_S  8\r
-/* SARADC_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */\r
-/*description: clock divider*/\r
-#define SARADC_SAR2_CLK_DIV  0x000000FF\r
-#define SARADC_SAR2_CLK_DIV_M  ((SARADC_SAR2_CLK_DIV_V)<<(SARADC_SAR2_CLK_DIV_S))\r
-#define SARADC_SAR2_CLK_DIV_V  0xFF\r
-#define SARADC_SAR2_CLK_DIV_S  0\r
-\r
-#define SARADC_SAR_MEAS_START2_REG          (DR_REG_SARADC_BASE + 0x0094)\r
-/* SARADC_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */\r
-/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW  0: SAR ADC2\r
- pad enable bitmap is controlled by ULP-coprocessor*/\r
-#define SARADC_SAR2_EN_PAD_FORCE  (BIT(31))\r
-#define SARADC_SAR2_EN_PAD_FORCE_M  (BIT(31))\r
-#define SARADC_SAR2_EN_PAD_FORCE_V  0x1\r
-#define SARADC_SAR2_EN_PAD_FORCE_S  31\r
-/* SARADC_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */\r
-/*description: SAR ADC2 pad enable bitmap  only active when reg_sar2_en_pad_force = 1*/\r
-#define SARADC_SAR2_EN_PAD  0x00000FFF\r
-#define SARADC_SAR2_EN_PAD_M  ((SARADC_SAR2_EN_PAD_V)<<(SARADC_SAR2_EN_PAD_S))\r
-#define SARADC_SAR2_EN_PAD_V  0xFFF\r
-#define SARADC_SAR2_EN_PAD_S  19\r
-/* SARADC_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */\r
-/*description: 1: SAR ADC2 controller (in RTC) is started by SW  0: SAR ADC2\r
- controller is started by ULP-coprocessor*/\r
-#define SARADC_MEAS2_START_FORCE  (BIT(18))\r
-#define SARADC_MEAS2_START_FORCE_M  (BIT(18))\r
-#define SARADC_MEAS2_START_FORCE_V  0x1\r
-#define SARADC_MEAS2_START_FORCE_S  18\r
-/* SARADC_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */\r
-/*description: SAR ADC2 controller (in RTC) starts conversion  only active when\r
- reg_meas2_start_force = 1*/\r
-#define SARADC_MEAS2_START_SAR  (BIT(17))\r
-#define SARADC_MEAS2_START_SAR_M  (BIT(17))\r
-#define SARADC_MEAS2_START_SAR_V  0x1\r
-#define SARADC_MEAS2_START_SAR_S  17\r
-/* SARADC_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: SAR ADC2 conversion done indication*/\r
-#define SARADC_MEAS2_DONE_SAR  (BIT(16))\r
-#define SARADC_MEAS2_DONE_SAR_M  (BIT(16))\r
-#define SARADC_MEAS2_DONE_SAR_V  0x1\r
-#define SARADC_MEAS2_DONE_SAR_S  16\r
-/* SARADC_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */\r
-/*description: SAR ADC2 data*/\r
-#define SARADC_MEAS2_DATA_SAR  0x0000FFFF\r
-#define SARADC_MEAS2_DATA_SAR_M  ((SARADC_MEAS2_DATA_SAR_V)<<(SARADC_MEAS2_DATA_SAR_S))\r
-#define SARADC_MEAS2_DATA_SAR_V  0xFFFF\r
-#define SARADC_MEAS2_DATA_SAR_S  0\r
-\r
-#define SARADC_SAR_DAC_CTRL1_REG          (DR_REG_SARADC_BASE + 0x0098)\r
-/* SARADC_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */\r
-/*description: 1: invert PDAC_CLK*/\r
-#define SARADC_DAC_CLK_INV  (BIT(25))\r
-#define SARADC_DAC_CLK_INV_M  (BIT(25))\r
-#define SARADC_DAC_CLK_INV_V  0x1\r
-#define SARADC_DAC_CLK_INV_S  25\r
-/* SARADC_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */\r
-/*description: 1: force PDAC_CLK to high*/\r
-#define SARADC_DAC_CLK_FORCE_HIGH  (BIT(24))\r
-#define SARADC_DAC_CLK_FORCE_HIGH_M  (BIT(24))\r
-#define SARADC_DAC_CLK_FORCE_HIGH_V  0x1\r
-#define SARADC_DAC_CLK_FORCE_HIGH_S  24\r
-/* SARADC_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */\r
-/*description: 1: force PDAC_CLK to low*/\r
-#define SARADC_DAC_CLK_FORCE_LOW  (BIT(23))\r
-#define SARADC_DAC_CLK_FORCE_LOW_M  (BIT(23))\r
-#define SARADC_DAC_CLK_FORCE_LOW_V  0x1\r
-#define SARADC_DAC_CLK_FORCE_LOW_S  23\r
-/* SARADC_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */\r
-/*description: 1: DAC1 & DAC2 use DMA  0: DAC1 & DAC2 do not use DMA*/\r
-#define SARADC_DAC_DIG_FORCE  (BIT(22))\r
-#define SARADC_DAC_DIG_FORCE_M  (BIT(22))\r
-#define SARADC_DAC_DIG_FORCE_V  0x1\r
-#define SARADC_DAC_DIG_FORCE_S  22\r
-/* SARADC_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */\r
-/*description: */\r
-#define SARADC_DEBUG_BIT_SEL  0x0000001F\r
-#define SARADC_DEBUG_BIT_SEL_M  ((SARADC_DEBUG_BIT_SEL_V)<<(SARADC_DEBUG_BIT_SEL_S))\r
-#define SARADC_DEBUG_BIT_SEL_V  0x1F\r
-#define SARADC_DEBUG_BIT_SEL_S  17\r
-/* SARADC_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */\r
-/*description: 1: enable CW generator  0: disable CW generator*/\r
-#define SARADC_SW_TONE_EN  (BIT(16))\r
-#define SARADC_SW_TONE_EN_M  (BIT(16))\r
-#define SARADC_SW_TONE_EN_V  0x1\r
-#define SARADC_SW_TONE_EN_S  16\r
-/* SARADC_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */\r
-/*description: frequency step for CW generator  can be used to adjust the frequency*/\r
-#define SARADC_SW_FSTEP  0x0000FFFF\r
-#define SARADC_SW_FSTEP_M  ((SARADC_SW_FSTEP_V)<<(SARADC_SW_FSTEP_S))\r
-#define SARADC_SW_FSTEP_V  0xFFFF\r
-#define SARADC_SW_FSTEP_S  0\r
-\r
-#define SARADC_SAR_DAC_CTRL2_REG          (DR_REG_SARADC_BASE + 0x009c)\r
-/* SARADC_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */\r
-/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]  0: to\r
- select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/\r
-#define SARADC_DAC_CW_EN2  (BIT(25))\r
-#define SARADC_DAC_CW_EN2_M  (BIT(25))\r
-#define SARADC_DAC_CW_EN2_V  0x1\r
-#define SARADC_DAC_CW_EN2_S  25\r
-/* SARADC_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */\r
-/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]  0: to\r
- select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/\r
-#define SARADC_DAC_CW_EN1  (BIT(24))\r
-#define SARADC_DAC_CW_EN1_M  (BIT(24))\r
-#define SARADC_DAC_CW_EN1_V  0x1\r
-#define SARADC_DAC_CW_EN1_S  24\r
-/* SARADC_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */\r
-/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB\r
-  11: invert all bits except MSB*/\r
-#define SARADC_DAC_INV2  0x00000003\r
-#define SARADC_DAC_INV2_M  ((SARADC_DAC_INV2_V)<<(SARADC_DAC_INV2_S))\r
-#define SARADC_DAC_INV2_V  0x3\r
-#define SARADC_DAC_INV2_S  22\r
-/* SARADC_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */\r
-/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB\r
-  11: invert all bits except MSB*/\r
-#define SARADC_DAC_INV1  0x00000003\r
-#define SARADC_DAC_INV1_M  ((SARADC_DAC_INV1_V)<<(SARADC_DAC_INV1_S))\r
-#define SARADC_DAC_INV1_V  0x3\r
-#define SARADC_DAC_INV1_S  20\r
-/* SARADC_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */\r
-/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/\r
-#define SARADC_DAC_SCALE2  0x00000003\r
-#define SARADC_DAC_SCALE2_M  ((SARADC_DAC_SCALE2_V)<<(SARADC_DAC_SCALE2_S))\r
-#define SARADC_DAC_SCALE2_V  0x3\r
-#define SARADC_DAC_SCALE2_S  18\r
-/* SARADC_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */\r
-/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/\r
-#define SARADC_DAC_SCALE1  0x00000003\r
-#define SARADC_DAC_SCALE1_M  ((SARADC_DAC_SCALE1_V)<<(SARADC_DAC_SCALE1_S))\r
-#define SARADC_DAC_SCALE1_V  0x3\r
-#define SARADC_DAC_SCALE1_S  16\r
-/* SARADC_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */\r
-/*description: DC offset for DAC2 CW generator*/\r
-#define SARADC_DAC_DC2  0x000000FF\r
-#define SARADC_DAC_DC2_M  ((SARADC_DAC_DC2_V)<<(SARADC_DAC_DC2_S))\r
-#define SARADC_DAC_DC2_V  0xFF\r
-#define SARADC_DAC_DC2_S  8\r
-/* SARADC_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */\r
-/*description: DC offset for DAC1 CW generator*/\r
-#define SARADC_DAC_DC1  0x000000FF\r
-#define SARADC_DAC_DC1_M  ((SARADC_DAC_DC1_V)<<(SARADC_DAC_DC1_S))\r
-#define SARADC_DAC_DC1_V  0xFF\r
-#define SARADC_DAC_DC1_S  0\r
-\r
-#define SARADC_SAR_MEAS_CTRL2_REG          (DR_REG_SARADC_BASE + 0x0a0)\r
-/* SARADC_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */\r
-/*description: */\r
-#define SARADC_AMP_SHORT_REF_GND_FORCE  0x00000003\r
-#define SARADC_AMP_SHORT_REF_GND_FORCE_M  ((SARADC_AMP_SHORT_REF_GND_FORCE_V)<<(SARADC_AMP_SHORT_REF_GND_FORCE_S))\r
-#define SARADC_AMP_SHORT_REF_GND_FORCE_V  0x3\r
-#define SARADC_AMP_SHORT_REF_GND_FORCE_S  17\r
-/* SARADC_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */\r
-/*description: */\r
-#define SARADC_AMP_SHORT_REF_FORCE  0x00000003\r
-#define SARADC_AMP_SHORT_REF_FORCE_M  ((SARADC_AMP_SHORT_REF_FORCE_V)<<(SARADC_AMP_SHORT_REF_FORCE_S))\r
-#define SARADC_AMP_SHORT_REF_FORCE_V  0x3\r
-#define SARADC_AMP_SHORT_REF_FORCE_S  15\r
-/* SARADC_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */\r
-/*description: */\r
-#define SARADC_AMP_RST_FB_FORCE  0x00000003\r
-#define SARADC_AMP_RST_FB_FORCE_M  ((SARADC_AMP_RST_FB_FORCE_V)<<(SARADC_AMP_RST_FB_FORCE_S))\r
-#define SARADC_AMP_RST_FB_FORCE_V  0x3\r
-#define SARADC_AMP_RST_FB_FORCE_S  13\r
-/* SARADC_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */\r
-/*description: */\r
-#define SARADC_SAR2_RSTB_FORCE  0x00000003\r
-#define SARADC_SAR2_RSTB_FORCE_M  ((SARADC_SAR2_RSTB_FORCE_V)<<(SARADC_SAR2_RSTB_FORCE_S))\r
-#define SARADC_SAR2_RSTB_FORCE_V  0x3\r
-#define SARADC_SAR2_RSTB_FORCE_S  11\r
-/* SARADC_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_SAR_RSTB_FSM_IDLE  (BIT(10))\r
-#define SARADC_SAR_RSTB_FSM_IDLE_M  (BIT(10))\r
-#define SARADC_SAR_RSTB_FSM_IDLE_V  0x1\r
-#define SARADC_SAR_RSTB_FSM_IDLE_S  10\r
-/* SARADC_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_XPD_SAR_FSM_IDLE  (BIT(9))\r
-#define SARADC_XPD_SAR_FSM_IDLE_M  (BIT(9))\r
-#define SARADC_XPD_SAR_FSM_IDLE_V  0x1\r
-#define SARADC_XPD_SAR_FSM_IDLE_S  9\r
-/* SARADC_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE  (BIT(8))\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_M  (BIT(8))\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_V  0x1\r
-#define SARADC_AMP_SHORT_REF_GND_FSM_IDLE_S  8\r
-/* SARADC_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_AMP_SHORT_REF_FSM_IDLE  (BIT(7))\r
-#define SARADC_AMP_SHORT_REF_FSM_IDLE_M  (BIT(7))\r
-#define SARADC_AMP_SHORT_REF_FSM_IDLE_V  0x1\r
-#define SARADC_AMP_SHORT_REF_FSM_IDLE_S  7\r
-/* SARADC_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_AMP_RST_FB_FSM_IDLE  (BIT(6))\r
-#define SARADC_AMP_RST_FB_FSM_IDLE_M  (BIT(6))\r
-#define SARADC_AMP_RST_FB_FSM_IDLE_V  0x1\r
-#define SARADC_AMP_RST_FB_FSM_IDLE_S  6\r
-/* SARADC_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_XPD_SAR_AMP_FSM_IDLE  (BIT(5))\r
-#define SARADC_XPD_SAR_AMP_FSM_IDLE_M  (BIT(5))\r
-#define SARADC_XPD_SAR_AMP_FSM_IDLE_V  0x1\r
-#define SARADC_XPD_SAR_AMP_FSM_IDLE_S  5\r
-/* SARADC_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */\r
-/*description: */\r
-#define SARADC_SAR1_DAC_XPD_FSM_IDLE  (BIT(4))\r
-#define SARADC_SAR1_DAC_XPD_FSM_IDLE_M  (BIT(4))\r
-#define SARADC_SAR1_DAC_XPD_FSM_IDLE_V  0x1\r
-#define SARADC_SAR1_DAC_XPD_FSM_IDLE_S  4\r
-/* SARADC_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */\r
-/*description: */\r
-#define SARADC_SAR1_DAC_XPD_FSM  0x0000000F\r
-#define SARADC_SAR1_DAC_XPD_FSM_M  ((SARADC_SAR1_DAC_XPD_FSM_V)<<(SARADC_SAR1_DAC_XPD_FSM_S))\r
-#define SARADC_SAR1_DAC_XPD_FSM_V  0xF\r
-#define SARADC_SAR1_DAC_XPD_FSM_S  0\r
-\r
-#define SARADC_SAR_NOUSE_REG          (DR_REG_SARADC_BASE + 0x00F8)\r
-/* SARADC_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */\r
-/*description: */\r
-#define SARADC_SAR_NOUSE  0xFFFFFFFF\r
-#define SARADC_SAR_NOUSE_M  ((SARADC_SAR_NOUSE_V)<<(SARADC_SAR_NOUSE_S))\r
-#define SARADC_SAR_NOUSE_V  0xFFFFFFFF\r
-#define SARADC_SAR_NOUSE_S  0\r
-\r
-#define SARADC_SARDATE_REG          (DR_REG_SARADC_BASE + 0x00FC)\r
-/* SARADC_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */\r
-/*description: */\r
-#define SARADC_SAR_DATE  0x0FFFFFFF\r
-#define SARADC_SAR_DATE_M  ((SARADC_SAR_DATE_V)<<(SARADC_SAR_DATE_S))\r
-#define SARADC_SAR_DATE_V  0xFFFFFFF\r
-#define SARADC_SAR_DATE_S  0\r
-\r
-\r
-\r
-\r
-#endif /*_SOC_SARADC_REG_H_ */\r
-\r
-\r

diff --git a/components/esp32/include/soc/sens_reg.h b/components/esp32/include/soc/sens_reg.h
new file mode 100644 (file)
index 0000000..0a032d2
--- /dev/null
+++ b/components/esp32/include/soc/sens_reg.h
@@ -0,0 +1,1047 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENS_REG_H_
+#define _SOC_SENS_REG_H_
+
+
+#include "soc.h"
+#define SENS_SAR_READ_CTRL_REG          (DR_REG_SENS_BASE + 0x0000)
+/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Invert SAR ADC1 data*/
+#define SENS_SAR1_DATA_INV  (BIT(28))
+#define SENS_SAR1_DATA_INV_M  (BIT(28))
+#define SENS_SAR1_DATA_INV_V  0x1
+#define SENS_SAR1_DATA_INV_S  28
+/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL  0: SAR ADC1 controlled by RTC ADC1 CTRL*/
+#define SENS_SAR1_DIG_FORCE  (BIT(27))
+#define SENS_SAR1_DIG_FORCE_M  (BIT(27))
+#define SENS_SAR1_DIG_FORCE_V  0x1
+#define SENS_SAR1_DIG_FORCE_S  27
+/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: */
+#define SENS_SAR1_SAMPLE_NUM  0x000000FF
+#define SENS_SAR1_SAMPLE_NUM_M  ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S))
+#define SENS_SAR1_SAMPLE_NUM_V  0xFF
+#define SENS_SAR1_SAMPLE_NUM_S  19
+/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SENS_SAR1_CLK_GATED  (BIT(18))
+#define SENS_SAR1_CLK_GATED_M  (BIT(18))
+#define SENS_SAR1_CLK_GATED_V  0x1
+#define SENS_SAR1_CLK_GATED_S  18
+/* SENS_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */
+/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width
+  11: for 12-bit width*/
+#define SENS_SAR1_SAMPLE_BIT  0x00000003
+#define SENS_SAR1_SAMPLE_BIT_M  ((SENS_SAR1_SAMPLE_BIT_V)<<(SENS_SAR1_SAMPLE_BIT_S))
+#define SENS_SAR1_SAMPLE_BIT_V  0x3
+#define SENS_SAR1_SAMPLE_BIT_S  16
+/* SENS_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */
+/*description: sample cycles for SAR ADC1*/
+#define SENS_SAR1_SAMPLE_CYCLE  0x000000FF
+#define SENS_SAR1_SAMPLE_CYCLE_M  ((SENS_SAR1_SAMPLE_CYCLE_V)<<(SENS_SAR1_SAMPLE_CYCLE_S))
+#define SENS_SAR1_SAMPLE_CYCLE_V  0xFF
+#define SENS_SAR1_SAMPLE_CYCLE_S  8
+/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: clock divider*/
+#define SENS_SAR1_CLK_DIV  0x000000FF
+#define SENS_SAR1_CLK_DIV_M  ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S))
+#define SENS_SAR1_CLK_DIV_V  0xFF
+#define SENS_SAR1_CLK_DIV_S  0
+
+#define SENS_SAR_READ_STATUS1_REG          (DR_REG_SENS_BASE + 0x0004)
+/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR1_READER_STATUS  0xFFFFFFFF
+#define SENS_SAR1_READER_STATUS_M  ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S))
+#define SENS_SAR1_READER_STATUS_V  0xFFFFFFFF
+#define SENS_SAR1_READER_STATUS_S  0
+
+#define SENS_SAR_MEAS_WAIT1_REG          (DR_REG_SENS_BASE + 0x0008)
+/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT2  0x0000FFFF
+#define SENS_SAR_AMP_WAIT2_M  ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S))
+#define SENS_SAR_AMP_WAIT2_V  0xFFFF
+#define SENS_SAR_AMP_WAIT2_S  16
+/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT1  0x0000FFFF
+#define SENS_SAR_AMP_WAIT1_M  ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S))
+#define SENS_SAR_AMP_WAIT1_V  0xFFFF
+#define SENS_SAR_AMP_WAIT1_S  0
+
+#define SENS_SAR_MEAS_WAIT2_REG          (DR_REG_SENS_BASE + 0x000c)
+/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */
+/*description: */
+#define SENS_SAR2_RSTB_WAIT  0x000000FF
+#define SENS_SAR2_RSTB_WAIT_M  ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S))
+#define SENS_SAR2_RSTB_WAIT_V  0xFF
+#define SENS_SAR2_RSTB_WAIT_S  20
+/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: */
+#define SENS_FORCE_XPD_SAR  0x00000003
+#define SENS_FORCE_XPD_SAR_M  ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
+#define SENS_FORCE_XPD_SAR_V  0x3
+#define SENS_FORCE_XPD_SAR_S  18
+/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: */
+#define SENS_FORCE_XPD_AMP  0x00000003
+#define SENS_FORCE_XPD_AMP_M  ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S))
+#define SENS_FORCE_XPD_AMP_V  0x3
+#define SENS_FORCE_XPD_AMP_S  16
+/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT3  0x0000FFFF
+#define SENS_SAR_AMP_WAIT3_M  ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S))
+#define SENS_SAR_AMP_WAIT3_V  0xFFFF
+#define SENS_SAR_AMP_WAIT3_S  0
+
+#define SENS_SAR_MEAS_CTRL_REG          (DR_REG_SENS_BASE + 0x0010)
+/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */
+/*description: */
+#define SENS_SAR2_XPD_WAIT  0x000000FF
+#define SENS_SAR2_XPD_WAIT_M  ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S))
+#define SENS_SAR2_XPD_WAIT_V  0xFF
+#define SENS_SAR2_XPD_WAIT_S  24
+/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */
+/*description: */
+#define SENS_SAR_RSTB_FSM  0x0000000F
+#define SENS_SAR_RSTB_FSM_M  ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S))
+#define SENS_SAR_RSTB_FSM_V  0xF
+#define SENS_SAR_RSTB_FSM_S  20
+/* SENS_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */
+/*description: */
+#define SENS_XPD_SAR_FSM  0x0000000F
+#define SENS_XPD_SAR_FSM_M  ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S))
+#define SENS_XPD_SAR_FSM_V  0xF
+#define SENS_XPD_SAR_FSM_S  16
+/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FSM  0x0000000F
+#define SENS_AMP_SHORT_REF_GND_FSM_M  ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S))
+#define SENS_AMP_SHORT_REF_GND_FSM_V  0xF
+#define SENS_AMP_SHORT_REF_GND_FSM_S  12
+/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FSM  0x0000000F
+#define SENS_AMP_SHORT_REF_FSM_M  ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S))
+#define SENS_AMP_SHORT_REF_FSM_V  0xF
+#define SENS_AMP_SHORT_REF_FSM_S  8
+/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FSM  0x0000000F
+#define SENS_AMP_RST_FB_FSM_M  ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S))
+#define SENS_AMP_RST_FB_FSM_V  0xF
+#define SENS_AMP_RST_FB_FSM_S  4
+/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */
+/*description: */
+#define SENS_XPD_SAR_AMP_FSM  0x0000000F
+#define SENS_XPD_SAR_AMP_FSM_M  ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S))
+#define SENS_XPD_SAR_AMP_FSM_V  0xF
+#define SENS_XPD_SAR_AMP_FSM_S  0
+
+#define SENS_SAR_READ_STATUS2_REG          (DR_REG_SENS_BASE + 0x0014)
+/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR2_READER_STATUS  0xFFFFFFFF
+#define SENS_SAR2_READER_STATUS_M  ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S))
+#define SENS_SAR2_READER_STATUS_V  0xFFFFFFFF
+#define SENS_SAR2_READER_STATUS_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC0_REG          (DR_REG_SENS_BASE + 0x0018)
+/* SENS_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer*/
+#define SENS_SLEEP_CYCLES_S0  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S0_M  ((SENS_SLEEP_CYCLES_S0_V)<<(SENS_SLEEP_CYCLES_S0_S))
+#define SENS_SLEEP_CYCLES_S0_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S0_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC1_REG          (DR_REG_SENS_BASE + 0x001c)
+/* SENS_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S1  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S1_M  ((SENS_SLEEP_CYCLES_S1_V)<<(SENS_SLEEP_CYCLES_S1_S))
+#define SENS_SLEEP_CYCLES_S1_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S1_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC2_REG          (DR_REG_SENS_BASE + 0x0020)
+/* SENS_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S2  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S2_M  ((SENS_SLEEP_CYCLES_S2_V)<<(SENS_SLEEP_CYCLES_S2_S))
+#define SENS_SLEEP_CYCLES_S2_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S2_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC3_REG          (DR_REG_SENS_BASE + 0x0024)
+/* SENS_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S3  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S3_M  ((SENS_SLEEP_CYCLES_S3_V)<<(SENS_SLEEP_CYCLES_S3_S))
+#define SENS_SLEEP_CYCLES_S3_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S3_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC4_REG          (DR_REG_SENS_BASE + 0x0028)
+/* SENS_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S4  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S4_M  ((SENS_SLEEP_CYCLES_S4_V)<<(SENS_SLEEP_CYCLES_S4_S))
+#define SENS_SLEEP_CYCLES_S4_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S4_S  0
+
+#define SENS_SAR_START_FORCE_REG          (DR_REG_SENS_BASE + 0x002c)
+/* SENS_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: N/A*/
+#define SENS_SAR2_PWDET_EN  (BIT(24))
+#define SENS_SAR2_PWDET_EN_M  (BIT(24))
+#define SENS_SAR2_PWDET_EN_V  0x1
+#define SENS_SAR2_PWDET_EN_S  24
+/* SENS_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: stop SAR ADC1 conversion*/
+#define SENS_SAR1_STOP  (BIT(23))
+#define SENS_SAR1_STOP_M  (BIT(23))
+#define SENS_SAR1_STOP_V  0x1
+#define SENS_SAR1_STOP_S  23
+/* SENS_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: stop SAR ADC2 conversion*/
+#define SENS_SAR2_STOP  (BIT(22))
+#define SENS_SAR2_STOP_M  (BIT(22))
+#define SENS_SAR2_STOP_V  0x1
+#define SENS_SAR2_STOP_S  22
+/* SENS_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */
+/*description: initialized PC for ULP-coprocessor*/
+#define SENS_PC_INIT  0x000007FF
+#define SENS_PC_INIT_M  ((SENS_PC_INIT_V)<<(SENS_PC_INIT_S))
+#define SENS_PC_INIT_V  0x7FF
+#define SENS_PC_INIT_S  11
+/* SENS_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SARCLK_EN  (BIT(10))
+#define SENS_SARCLK_EN_M  (BIT(10))
+#define SENS_SARCLK_EN_V  0x1
+#define SENS_SARCLK_EN_S  10
+/* SENS_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Write 1 to start ULP-coprocessor  only active when reg_ulp_cp_force_start_top
+ = 1*/
+#define SENS_ULP_CP_START_TOP  (BIT(9))
+#define SENS_ULP_CP_START_TOP_M  (BIT(9))
+#define SENS_ULP_CP_START_TOP_V  0x1
+#define SENS_ULP_CP_START_TOP_S  9
+/* SENS_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: ULP-coprocessor is started by SW  0: ULP-coprocessor is started by timer*/
+#define SENS_ULP_CP_FORCE_START_TOP  (BIT(8))
+#define SENS_ULP_CP_FORCE_START_TOP_M  (BIT(8))
+#define SENS_ULP_CP_FORCE_START_TOP_V  0x1
+#define SENS_ULP_CP_FORCE_START_TOP_S  8
+/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
+/*description: SAR2_PWDET_CCT  PA power detector capacitance tuning.*/
+#define SENS_SAR2_PWDET_CCT  0x00000007
+#define SENS_SAR2_PWDET_CCT_M  ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S))
+#define SENS_SAR2_PWDET_CCT_V  0x7
+#define SENS_SAR2_PWDET_CCT_S  5
+/* SENS_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: SAR2_EN_TEST  only active when reg_sar2_dig_force = 0*/
+#define SENS_SAR2_EN_TEST  (BIT(4))
+#define SENS_SAR2_EN_TEST_M  (BIT(4))
+#define SENS_SAR2_EN_TEST_V  0x1
+#define SENS_SAR2_EN_TEST_S  4
+/* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
+#define SENS_SAR2_BIT_WIDTH  0x00000003
+#define SENS_SAR2_BIT_WIDTH_M  ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S))
+#define SENS_SAR2_BIT_WIDTH_V  0x3
+#define SENS_SAR2_BIT_WIDTH_S  2
+/* SENS_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
+#define SENS_SAR1_BIT_WIDTH  0x00000003
+#define SENS_SAR1_BIT_WIDTH_M  ((SENS_SAR1_BIT_WIDTH_V)<<(SENS_SAR1_BIT_WIDTH_S))
+#define SENS_SAR1_BIT_WIDTH_V  0x3
+#define SENS_SAR1_BIT_WIDTH_S  0
+
+#define SENS_SAR_MEM_WR_CTRL_REG          (DR_REG_SENS_BASE + 0x0030)
+/* SENS_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: */
+#define SENS_RTC_MEM_WR_OFFST_CLR  (BIT(22))
+#define SENS_RTC_MEM_WR_OFFST_CLR_M  (BIT(22))
+#define SENS_RTC_MEM_WR_OFFST_CLR_V  0x1
+#define SENS_RTC_MEM_WR_OFFST_CLR_S  22
+/* SENS_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */
+/*description: */
+#define SENS_MEM_WR_ADDR_SIZE  0x000007FF
+#define SENS_MEM_WR_ADDR_SIZE_M  ((SENS_MEM_WR_ADDR_SIZE_V)<<(SENS_MEM_WR_ADDR_SIZE_S))
+#define SENS_MEM_WR_ADDR_SIZE_V  0x7FF
+#define SENS_MEM_WR_ADDR_SIZE_S  11
+/* SENS_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */
+/*description: */
+#define SENS_MEM_WR_ADDR_INIT  0x000007FF
+#define SENS_MEM_WR_ADDR_INIT_M  ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S))
+#define SENS_MEM_WR_ADDR_INIT_V  0x7FF
+#define SENS_MEM_WR_ADDR_INIT_S  0
+
+#define SENS_SAR_ATTEN1_REG          (DR_REG_SENS_BASE + 0x0034)
+/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
+#define SENS_SAR1_ATTEN  0xFFFFFFFF
+#define SENS_SAR1_ATTEN_M  ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S))
+#define SENS_SAR1_ATTEN_V  0xFFFFFFFF
+#define SENS_SAR1_ATTEN_S  0
+
+#define SENS_SAR_ATTEN2_REG          (DR_REG_SENS_BASE + 0x0038)
+/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
+#define SENS_SAR2_ATTEN  0xFFFFFFFF
+#define SENS_SAR2_ATTEN_M  ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S))
+#define SENS_SAR2_ATTEN_V  0xFFFFFFFF
+#define SENS_SAR2_ATTEN_S  0
+
+#define SENS_SAR_SLAVE_ADDR1_REG          (DR_REG_SENS_BASE + 0x003c)
+/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: */
+#define SENS_MEAS_STATUS  0x000000FF
+#define SENS_MEAS_STATUS_M  ((SENS_MEAS_STATUS_V)<<(SENS_MEAS_STATUS_S))
+#define SENS_MEAS_STATUS_V  0xFF
+#define SENS_MEAS_STATUS_S  22
+/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR0  0x000007FF
+#define SENS_I2C_SLAVE_ADDR0_M  ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S))
+#define SENS_I2C_SLAVE_ADDR0_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR0_S  11
+/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR1  0x000007FF
+#define SENS_I2C_SLAVE_ADDR1_M  ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S))
+#define SENS_I2C_SLAVE_ADDR1_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR1_S  0
+
+#define SENS_SAR_SLAVE_ADDR2_REG          (DR_REG_SENS_BASE + 0x0040)
+/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR2  0x000007FF
+#define SENS_I2C_SLAVE_ADDR2_M  ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S))
+#define SENS_I2C_SLAVE_ADDR2_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR2_S  11
+/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR3  0x000007FF
+#define SENS_I2C_SLAVE_ADDR3_M  ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S))
+#define SENS_I2C_SLAVE_ADDR3_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR3_S  0
+
+#define SENS_SAR_SLAVE_ADDR3_REG          (DR_REG_SENS_BASE + 0x0044)
+/* SENS_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */
+/*description: indicate temperature sensor out ready*/
+#define SENS_TSENS_RDY_OUT  (BIT(30))
+#define SENS_TSENS_RDY_OUT_M  (BIT(30))
+#define SENS_TSENS_RDY_OUT_V  0x1
+#define SENS_TSENS_RDY_OUT_S  30
+/* SENS_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: temperature sensor data out*/
+#define SENS_TSENS_OUT  0x000000FF
+#define SENS_TSENS_OUT_M  ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S))
+#define SENS_TSENS_OUT_V  0xFF
+#define SENS_TSENS_OUT_S  22
+/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR4  0x000007FF
+#define SENS_I2C_SLAVE_ADDR4_M  ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S))
+#define SENS_I2C_SLAVE_ADDR4_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR4_S  11
+/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR5  0x000007FF
+#define SENS_I2C_SLAVE_ADDR5_M  ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S))
+#define SENS_I2C_SLAVE_ADDR5_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR5_S  0
+
+#define SENS_SAR_SLAVE_ADDR4_REG          (DR_REG_SENS_BASE + 0x0048)
+/* SENS_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */
+/*description: indicate I2C done*/
+#define SENS_I2C_DONE  (BIT(30))
+#define SENS_I2C_DONE_M  (BIT(30))
+#define SENS_I2C_DONE_V  0x1
+#define SENS_I2C_DONE_S  30
+/* SENS_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: I2C read data*/
+#define SENS_I2C_RDATA  0x000000FF
+#define SENS_I2C_RDATA_M  ((SENS_I2C_RDATA_V)<<(SENS_I2C_RDATA_S))
+#define SENS_I2C_RDATA_V  0xFF
+#define SENS_I2C_RDATA_S  22
+/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR6  0x000007FF
+#define SENS_I2C_SLAVE_ADDR6_M  ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S))
+#define SENS_I2C_SLAVE_ADDR6_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR6_S  11
+/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR7  0x000007FF
+#define SENS_I2C_SLAVE_ADDR7_M  ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S))
+#define SENS_I2C_SLAVE_ADDR7_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR7_S  0
+
+#define SENS_SAR_TSENS_CTRL_REG          (DR_REG_SENS_BASE + 0x004c)
+/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: temperature sensor dump out  only active when reg_tsens_power_up_force = 1*/
+#define SENS_TSENS_DUMP_OUT  (BIT(26))
+#define SENS_TSENS_DUMP_OUT_M  (BIT(26))
+#define SENS_TSENS_DUMP_OUT_V  0x1
+#define SENS_TSENS_DUMP_OUT_S  26
+/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: dump out & power up controlled by SW  0: by FSM*/
+#define SENS_TSENS_POWER_UP_FORCE  (BIT(25))
+#define SENS_TSENS_POWER_UP_FORCE_M  (BIT(25))
+#define SENS_TSENS_POWER_UP_FORCE_V  0x1
+#define SENS_TSENS_POWER_UP_FORCE_S  25
+/* SENS_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: temperature sensor power up*/
+#define SENS_TSENS_POWER_UP  (BIT(24))
+#define SENS_TSENS_POWER_UP_M  (BIT(24))
+#define SENS_TSENS_POWER_UP_V  0x1
+#define SENS_TSENS_POWER_UP_S  24
+/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */
+/*description: temperature sensor clock divider*/
+#define SENS_TSENS_CLK_DIV  0x000000FF
+#define SENS_TSENS_CLK_DIV_M  ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S))
+#define SENS_TSENS_CLK_DIV_V  0xFF
+#define SENS_TSENS_CLK_DIV_S  16
+/* SENS_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: invert temperature sensor data*/
+#define SENS_TSENS_IN_INV  (BIT(15))
+#define SENS_TSENS_IN_INV_M  (BIT(15))
+#define SENS_TSENS_IN_INV_V  0x1
+#define SENS_TSENS_IN_INV_S  15
+/* SENS_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define SENS_TSENS_CLK_GATED  (BIT(14))
+#define SENS_TSENS_CLK_GATED_M  (BIT(14))
+#define SENS_TSENS_CLK_GATED_V  0x1
+#define SENS_TSENS_CLK_GATED_S  14
+/* SENS_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define SENS_TSENS_CLK_INV  (BIT(13))
+#define SENS_TSENS_CLK_INV_M  (BIT(13))
+#define SENS_TSENS_CLK_INV_V  0x1
+#define SENS_TSENS_CLK_INV_S  13
+/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SENS_TSENS_XPD_FORCE  (BIT(12))
+#define SENS_TSENS_XPD_FORCE_M  (BIT(12))
+#define SENS_TSENS_XPD_FORCE_V  0x1
+#define SENS_TSENS_XPD_FORCE_S  12
+/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
+/*description: */
+#define SENS_TSENS_XPD_WAIT  0x00000FFF
+#define SENS_TSENS_XPD_WAIT_M  ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S))
+#define SENS_TSENS_XPD_WAIT_V  0xFFF
+#define SENS_TSENS_XPD_WAIT_S  0
+
+#define SENS_SAR_I2C_CTRL_REG          (DR_REG_SENS_BASE + 0x0050)
+/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: I2C started by SW  0: I2C started by FSM*/
+#define SENS_SAR_I2C_START_FORCE  (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_M  (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_V  0x1
+#define SENS_SAR_I2C_START_FORCE_S  29
+/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: start I2C  only active when reg_sar_i2c_start_force = 1*/
+#define SENS_SAR_I2C_START  (BIT(28))
+#define SENS_SAR_I2C_START_M  (BIT(28))
+#define SENS_SAR_I2C_START_V  0x1
+#define SENS_SAR_I2C_START_S  28
+/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
+/*description: I2C control data  only active when reg_sar_i2c_start_force = 1*/
+#define SENS_SAR_I2C_CTRL  0x0FFFFFFF
+#define SENS_SAR_I2C_CTRL_M  ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S))
+#define SENS_SAR_I2C_CTRL_V  0xFFFFFFF
+#define SENS_SAR_I2C_CTRL_S  0
+
+#define SENS_SAR_MEAS_START1_REG          (DR_REG_SENS_BASE + 0x0054)
+/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW  0: SAR ADC1
+ pad enable bitmap is controlled by ULP-coprocessor*/
+#define SENS_SAR1_EN_PAD_FORCE  (BIT(31))
+#define SENS_SAR1_EN_PAD_FORCE_M  (BIT(31))
+#define SENS_SAR1_EN_PAD_FORCE_V  0x1
+#define SENS_SAR1_EN_PAD_FORCE_S  31
+/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
+/*description: SAR ADC1 pad enable bitmap  only active when reg_sar1_en_pad_force = 1*/
+#define SENS_SAR1_EN_PAD  0x00000FFF
+#define SENS_SAR1_EN_PAD_M  ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S))
+#define SENS_SAR1_EN_PAD_V  0xFFF
+#define SENS_SAR1_EN_PAD_S  19
+/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SAR ADC1 controller (in RTC) is started by SW  0: SAR ADC1
+ controller is started by ULP-coprocessor*/
+#define SENS_MEAS1_START_FORCE  (BIT(18))
+#define SENS_MEAS1_START_FORCE_M  (BIT(18))
+#define SENS_MEAS1_START_FORCE_V  0x1
+#define SENS_MEAS1_START_FORCE_S  18
+/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: SAR ADC1 controller (in RTC) starts conversion  only active when
+ reg_meas1_start_force = 1*/
+#define SENS_MEAS1_START_SAR  (BIT(17))
+#define SENS_MEAS1_START_SAR_M  (BIT(17))
+#define SENS_MEAS1_START_SAR_V  0x1
+#define SENS_MEAS1_START_SAR_S  17
+/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: SAR ADC1 conversion done indication*/
+#define SENS_MEAS1_DONE_SAR  (BIT(16))
+#define SENS_MEAS1_DONE_SAR_M  (BIT(16))
+#define SENS_MEAS1_DONE_SAR_V  0x1
+#define SENS_MEAS1_DONE_SAR_S  16
+/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: SAR ADC1 data*/
+#define SENS_MEAS1_DATA_SAR  0x0000FFFF
+#define SENS_MEAS1_DATA_SAR_M  ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S))
+#define SENS_MEAS1_DATA_SAR_V  0xFFFF
+#define SENS_MEAS1_DATA_SAR_S  0
+
+#define SENS_SAR_TOUCH_CTRL1_REG          (DR_REG_SENS_BASE + 0x0058)
+/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled
+ by FSM in ULP-coprocessor*/
+#define SENS_HALL_PHASE_FORCE  (BIT(27))
+#define SENS_HALL_PHASE_FORCE_M  (BIT(27))
+#define SENS_HALL_PHASE_FORCE_V  0x1
+#define SENS_HALL_PHASE_FORCE_S  27
+/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by
+ FSM in ULP-coprocessor*/
+#define SENS_XPD_HALL_FORCE  (BIT(26))
+#define SENS_XPD_HALL_FORCE_M  (BIT(26))
+#define SENS_XPD_HALL_FORCE_V  0x1
+#define SENS_XPD_HALL_FORCE_S  26
+/* SENS_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: 1: wakeup interrupt is generated if SET1 is "touched"  0:
+ wakeup interrupt is generated only if SET1 & SET2 is both "touched"*/
+#define SENS_TOUCH_OUT_1EN  (BIT(25))
+#define SENS_TOUCH_OUT_1EN_M  (BIT(25))
+#define SENS_TOUCH_OUT_1EN_V  0x1
+#define SENS_TOUCH_OUT_1EN_S  25
+/* SENS_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: when the counter is greater then the threshold  the touch
+ pad is considered as "touched"  0: when the counter is less than the threshold  the touch pad is considered as "touched"*/
+#define SENS_TOUCH_OUT_SEL  (BIT(24))
+#define SENS_TOUCH_OUT_SEL_M  (BIT(24))
+#define SENS_TOUCH_OUT_SEL_V  0x1
+#define SENS_TOUCH_OUT_SEL_S  24
+/* SENS_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */
+/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
+#define SENS_TOUCH_XPD_WAIT  0x000000FF
+#define SENS_TOUCH_XPD_WAIT_M  ((SENS_TOUCH_XPD_WAIT_V)<<(SENS_TOUCH_XPD_WAIT_S))
+#define SENS_TOUCH_XPD_WAIT_V  0xFF
+#define SENS_TOUCH_XPD_WAIT_S  16
+/* SENS_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: the meas length (in 8MHz)*/
+#define SENS_TOUCH_MEAS_DELAY  0x0000FFFF
+#define SENS_TOUCH_MEAS_DELAY_M  ((SENS_TOUCH_MEAS_DELAY_V)<<(SENS_TOUCH_MEAS_DELAY_S))
+#define SENS_TOUCH_MEAS_DELAY_V  0xFFFF
+#define SENS_TOUCH_MEAS_DELAY_S  0
+
+#define SENS_SAR_TOUCH_THRES1_REG          (DR_REG_SENS_BASE + 0x005c)
+/* SENS_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 0*/
+#define SENS_TOUCH_OUT_TH0  0x0000FFFF
+#define SENS_TOUCH_OUT_TH0_M  ((SENS_TOUCH_OUT_TH0_V)<<(SENS_TOUCH_OUT_TH0_S))
+#define SENS_TOUCH_OUT_TH0_V  0xFFFF
+#define SENS_TOUCH_OUT_TH0_S  16
+/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 1*/
+#define SENS_TOUCH_OUT_TH1  0x0000FFFF
+#define SENS_TOUCH_OUT_TH1_M  ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S))
+#define SENS_TOUCH_OUT_TH1_V  0xFFFF
+#define SENS_TOUCH_OUT_TH1_S  0
+
+#define SENS_SAR_TOUCH_THRES2_REG          (DR_REG_SENS_BASE + 0x0060)
+/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 2*/
+#define SENS_TOUCH_OUT_TH2  0x0000FFFF
+#define SENS_TOUCH_OUT_TH2_M  ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S))
+#define SENS_TOUCH_OUT_TH2_V  0xFFFF
+#define SENS_TOUCH_OUT_TH2_S  16
+/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 3*/
+#define SENS_TOUCH_OUT_TH3  0x0000FFFF
+#define SENS_TOUCH_OUT_TH3_M  ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S))
+#define SENS_TOUCH_OUT_TH3_V  0xFFFF
+#define SENS_TOUCH_OUT_TH3_S  0
+
+#define SENS_SAR_TOUCH_THRES3_REG          (DR_REG_SENS_BASE + 0x0064)
+/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 4*/
+#define SENS_TOUCH_OUT_TH4  0x0000FFFF
+#define SENS_TOUCH_OUT_TH4_M  ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S))
+#define SENS_TOUCH_OUT_TH4_V  0xFFFF
+#define SENS_TOUCH_OUT_TH4_S  16
+/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 5*/
+#define SENS_TOUCH_OUT_TH5  0x0000FFFF
+#define SENS_TOUCH_OUT_TH5_M  ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S))
+#define SENS_TOUCH_OUT_TH5_V  0xFFFF
+#define SENS_TOUCH_OUT_TH5_S  0
+
+#define SENS_SAR_TOUCH_THRES4_REG          (DR_REG_SENS_BASE + 0x0068)
+/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 6*/
+#define SENS_TOUCH_OUT_TH6  0x0000FFFF
+#define SENS_TOUCH_OUT_TH6_M  ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S))
+#define SENS_TOUCH_OUT_TH6_V  0xFFFF
+#define SENS_TOUCH_OUT_TH6_S  16
+/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 7*/
+#define SENS_TOUCH_OUT_TH7  0x0000FFFF
+#define SENS_TOUCH_OUT_TH7_M  ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S))
+#define SENS_TOUCH_OUT_TH7_V  0xFFFF
+#define SENS_TOUCH_OUT_TH7_S  0
+
+#define SENS_SAR_TOUCH_THRES5_REG          (DR_REG_SENS_BASE + 0x006c)
+/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 8*/
+#define SENS_TOUCH_OUT_TH8  0x0000FFFF
+#define SENS_TOUCH_OUT_TH8_M  ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S))
+#define SENS_TOUCH_OUT_TH8_V  0xFFFF
+#define SENS_TOUCH_OUT_TH8_S  16
+/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 9*/
+#define SENS_TOUCH_OUT_TH9  0x0000FFFF
+#define SENS_TOUCH_OUT_TH9_M  ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S))
+#define SENS_TOUCH_OUT_TH9_V  0xFFFF
+#define SENS_TOUCH_OUT_TH9_S  0
+
+#define SENS_SAR_TOUCH_OUT1_REG          (DR_REG_SENS_BASE + 0x0070)
+/* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 0*/
+#define SENS_TOUCH_MEAS_OUT0  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT0_M  ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S))
+#define SENS_TOUCH_MEAS_OUT0_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT0_S  16
+/* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 1*/
+#define SENS_TOUCH_MEAS_OUT1  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT1_M  ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S))
+#define SENS_TOUCH_MEAS_OUT1_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT1_S  0
+
+#define SENS_SAR_TOUCH_OUT2_REG          (DR_REG_SENS_BASE + 0x0074)
+/* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 2*/
+#define SENS_TOUCH_MEAS_OUT2  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT2_M  ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S))
+#define SENS_TOUCH_MEAS_OUT2_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT2_S  16
+/* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 3*/
+#define SENS_TOUCH_MEAS_OUT3  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT3_M  ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S))
+#define SENS_TOUCH_MEAS_OUT3_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT3_S  0
+
+#define SENS_SAR_TOUCH_OUT3_REG          (DR_REG_SENS_BASE + 0x0078)
+/* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 4*/
+#define SENS_TOUCH_MEAS_OUT4  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT4_M  ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S))
+#define SENS_TOUCH_MEAS_OUT4_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT4_S  16
+/* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 5*/
+#define SENS_TOUCH_MEAS_OUT5  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT5_M  ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S))
+#define SENS_TOUCH_MEAS_OUT5_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT5_S  0
+
+#define SENS_SAR_TOUCH_OUT4_REG          (DR_REG_SENS_BASE + 0x007c)
+/* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 6*/
+#define SENS_TOUCH_MEAS_OUT6  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT6_M  ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S))
+#define SENS_TOUCH_MEAS_OUT6_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT6_S  16
+/* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 7*/
+#define SENS_TOUCH_MEAS_OUT7  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT7_M  ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S))
+#define SENS_TOUCH_MEAS_OUT7_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT7_S  0
+
+#define SENS_SAR_TOUCH_OUT5_REG          (DR_REG_SENS_BASE + 0x0080)
+/* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 8*/
+#define SENS_TOUCH_MEAS_OUT8  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT8_M  ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S))
+#define SENS_TOUCH_MEAS_OUT8_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT8_S  16
+/* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 9*/
+#define SENS_TOUCH_MEAS_OUT9  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT9_M  ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S))
+#define SENS_TOUCH_MEAS_OUT9_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT9_S  0
+
+#define SENS_SAR_TOUCH_CTRL2_REG          (DR_REG_SENS_BASE + 0x0084)
+/* SENS_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */
+/*description: to clear reg_touch_meas_en*/
+#define SENS_TOUCH_MEAS_EN_CLR  (BIT(30))
+#define SENS_TOUCH_MEAS_EN_CLR_M  (BIT(30))
+#define SENS_TOUCH_MEAS_EN_CLR_V  0x1
+#define SENS_TOUCH_MEAS_EN_CLR_S  30
+/* SENS_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */
+/*description: sleep cycles for timer*/
+#define SENS_TOUCH_SLEEP_CYCLES  0x0000FFFF
+#define SENS_TOUCH_SLEEP_CYCLES_M  ((SENS_TOUCH_SLEEP_CYCLES_V)<<(SENS_TOUCH_SLEEP_CYCLES_S))
+#define SENS_TOUCH_SLEEP_CYCLES_V  0xFFFF
+#define SENS_TOUCH_SLEEP_CYCLES_S  14
+/* SENS_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */
+/*description: 1: to start touch fsm by SW  0: to start touch fsm by timer*/
+#define SENS_TOUCH_START_FORCE  (BIT(13))
+#define SENS_TOUCH_START_FORCE_M  (BIT(13))
+#define SENS_TOUCH_START_FORCE_V  0x1
+#define SENS_TOUCH_START_FORCE_S  13
+/* SENS_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: 1: start touch fsm  valid when reg_touch_start_force is set*/
+#define SENS_TOUCH_START_EN  (BIT(12))
+#define SENS_TOUCH_START_EN_M  (BIT(12))
+#define SENS_TOUCH_START_EN_V  0x1
+#define SENS_TOUCH_START_EN_S  12
+/* SENS_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm  0: TOUCH_START
+ & TOUCH_XPD is controlled by registers*/
+#define SENS_TOUCH_START_FSM_EN  (BIT(11))
+#define SENS_TOUCH_START_FSM_EN_M  (BIT(11))
+#define SENS_TOUCH_START_FSM_EN_V  0x1
+#define SENS_TOUCH_START_FSM_EN_S  11
+/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */
+/*description: fsm set 1 to indicate touch touch meas is done*/
+#define SENS_TOUCH_MEAS_DONE  (BIT(10))
+#define SENS_TOUCH_MEAS_DONE_M  (BIT(10))
+#define SENS_TOUCH_MEAS_DONE_V  0x1
+#define SENS_TOUCH_MEAS_DONE_S  10
+/* SENS_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: 10-bit register to indicate which pads are "touched"*/
+#define SENS_TOUCH_MEAS_EN  0x000003FF
+#define SENS_TOUCH_MEAS_EN_M  ((SENS_TOUCH_MEAS_EN_V)<<(SENS_TOUCH_MEAS_EN_S))
+#define SENS_TOUCH_MEAS_EN_V  0x3FF
+#define SENS_TOUCH_MEAS_EN_S  0
+
+#define SENS_SAR_TOUCH_ENABLE_REG          (DR_REG_SENS_BASE + 0x008c)
+/* SENS_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */
+/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is
+ "touched" only if at least one of touch pad in SET1 is "touched".*/
+#define SENS_TOUCH_PAD_OUTEN1  0x000003FF
+#define SENS_TOUCH_PAD_OUTEN1_M  ((SENS_TOUCH_PAD_OUTEN1_V)<<(SENS_TOUCH_PAD_OUTEN1_S))
+#define SENS_TOUCH_PAD_OUTEN1_V  0x3FF
+#define SENS_TOUCH_PAD_OUTEN1_S  20
+/* SENS_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */
+/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is
+ "touched" only if at least one of touch pad in SET2 is "touched".*/
+#define SENS_TOUCH_PAD_OUTEN2  0x000003FF
+#define SENS_TOUCH_PAD_OUTEN2_M  ((SENS_TOUCH_PAD_OUTEN2_V)<<(SENS_TOUCH_PAD_OUTEN2_S))
+#define SENS_TOUCH_PAD_OUTEN2_V  0x3FF
+#define SENS_TOUCH_PAD_OUTEN2_S  10
+/* SENS_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
+/*description: Bitmap defining the working set during the measurement.*/
+#define SENS_TOUCH_PAD_WORKEN  0x000003FF
+#define SENS_TOUCH_PAD_WORKEN_M  ((SENS_TOUCH_PAD_WORKEN_V)<<(SENS_TOUCH_PAD_WORKEN_S))
+#define SENS_TOUCH_PAD_WORKEN_V  0x3FF
+#define SENS_TOUCH_PAD_WORKEN_S  0
+
+#define SENS_SAR_READ_CTRL2_REG          (DR_REG_SENS_BASE + 0x0090)
+/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Invert SAR ADC2 data*/
+#define SENS_SAR2_DATA_INV  (BIT(29))
+#define SENS_SAR2_DATA_INV_M  (BIT(29))
+#define SENS_SAR2_DATA_INV_V  0x1
+#define SENS_SAR2_DATA_INV_S  29
+/* SENS_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL  0: SAR
+ ADC2 controlled by RTC ADC2 CTRL*/
+#define SENS_SAR2_DIG_FORCE  (BIT(28))
+#define SENS_SAR2_DIG_FORCE_M  (BIT(28))
+#define SENS_SAR2_DIG_FORCE_V  0x1
+#define SENS_SAR2_DIG_FORCE_S  28
+/* SENS_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR2_PWDET_FORCE  (BIT(27))
+#define SENS_SAR2_PWDET_FORCE_M  (BIT(27))
+#define SENS_SAR2_PWDET_FORCE_V  0x1
+#define SENS_SAR2_PWDET_FORCE_S  27
+/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: */
+#define SENS_SAR2_SAMPLE_NUM  0x000000FF
+#define SENS_SAR2_SAMPLE_NUM_M  ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S))
+#define SENS_SAR2_SAMPLE_NUM_V  0xFF
+#define SENS_SAR2_SAMPLE_NUM_S  19
+/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SENS_SAR2_CLK_GATED  (BIT(18))
+#define SENS_SAR2_CLK_GATED_M  (BIT(18))
+#define SENS_SAR2_CLK_GATED_V  0x1
+#define SENS_SAR2_CLK_GATED_S  18
+/* SENS_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */
+/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width
+  11: for 12-bit width*/
+#define SENS_SAR2_SAMPLE_BIT  0x00000003
+#define SENS_SAR2_SAMPLE_BIT_M  ((SENS_SAR2_SAMPLE_BIT_V)<<(SENS_SAR2_SAMPLE_BIT_S))
+#define SENS_SAR2_SAMPLE_BIT_V  0x3
+#define SENS_SAR2_SAMPLE_BIT_S  16
+/* SENS_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */
+/*description: sample cycles for SAR ADC2*/
+#define SENS_SAR2_SAMPLE_CYCLE  0x000000FF
+#define SENS_SAR2_SAMPLE_CYCLE_M  ((SENS_SAR2_SAMPLE_CYCLE_V)<<(SENS_SAR2_SAMPLE_CYCLE_S))
+#define SENS_SAR2_SAMPLE_CYCLE_V  0xFF
+#define SENS_SAR2_SAMPLE_CYCLE_S  8
+/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: clock divider*/
+#define SENS_SAR2_CLK_DIV  0x000000FF
+#define SENS_SAR2_CLK_DIV_M  ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S))
+#define SENS_SAR2_CLK_DIV_V  0xFF
+#define SENS_SAR2_CLK_DIV_S  0
+
+#define SENS_SAR_MEAS_START2_REG          (DR_REG_SENS_BASE + 0x0094)
+/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW  0: SAR ADC2
+ pad enable bitmap is controlled by ULP-coprocessor*/
+#define SENS_SAR2_EN_PAD_FORCE  (BIT(31))
+#define SENS_SAR2_EN_PAD_FORCE_M  (BIT(31))
+#define SENS_SAR2_EN_PAD_FORCE_V  0x1
+#define SENS_SAR2_EN_PAD_FORCE_S  31
+/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
+/*description: SAR ADC2 pad enable bitmap  only active when reg_sar2_en_pad_force = 1*/
+#define SENS_SAR2_EN_PAD  0x00000FFF
+#define SENS_SAR2_EN_PAD_M  ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S))
+#define SENS_SAR2_EN_PAD_V  0xFFF
+#define SENS_SAR2_EN_PAD_S  19
+/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 controller (in RTC) is started by SW  0: SAR ADC2
+ controller is started by ULP-coprocessor*/
+#define SENS_MEAS2_START_FORCE  (BIT(18))
+#define SENS_MEAS2_START_FORCE_M  (BIT(18))
+#define SENS_MEAS2_START_FORCE_V  0x1
+#define SENS_MEAS2_START_FORCE_S  18
+/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: SAR ADC2 controller (in RTC) starts conversion  only active when
+ reg_meas2_start_force = 1*/
+#define SENS_MEAS2_START_SAR  (BIT(17))
+#define SENS_MEAS2_START_SAR_M  (BIT(17))
+#define SENS_MEAS2_START_SAR_V  0x1
+#define SENS_MEAS2_START_SAR_S  17
+/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: SAR ADC2 conversion done indication*/
+#define SENS_MEAS2_DONE_SAR  (BIT(16))
+#define SENS_MEAS2_DONE_SAR_M  (BIT(16))
+#define SENS_MEAS2_DONE_SAR_V  0x1
+#define SENS_MEAS2_DONE_SAR_S  16
+/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: SAR ADC2 data*/
+#define SENS_MEAS2_DATA_SAR  0x0000FFFF
+#define SENS_MEAS2_DATA_SAR_M  ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S))
+#define SENS_MEAS2_DATA_SAR_V  0xFFFF
+#define SENS_MEAS2_DATA_SAR_S  0
+
+#define SENS_SAR_DAC_CTRL1_REG          (DR_REG_SENS_BASE + 0x0098)
+/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: invert PDAC_CLK*/
+#define SENS_DAC_CLK_INV  (BIT(25))
+#define SENS_DAC_CLK_INV_M  (BIT(25))
+#define SENS_DAC_CLK_INV_V  0x1
+#define SENS_DAC_CLK_INV_S  25
+/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: force PDAC_CLK to high*/
+#define SENS_DAC_CLK_FORCE_HIGH  (BIT(24))
+#define SENS_DAC_CLK_FORCE_HIGH_M  (BIT(24))
+#define SENS_DAC_CLK_FORCE_HIGH_V  0x1
+#define SENS_DAC_CLK_FORCE_HIGH_S  24
+/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: force PDAC_CLK to low*/
+#define SENS_DAC_CLK_FORCE_LOW  (BIT(23))
+#define SENS_DAC_CLK_FORCE_LOW_M  (BIT(23))
+#define SENS_DAC_CLK_FORCE_LOW_V  0x1
+#define SENS_DAC_CLK_FORCE_LOW_S  23
+/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: DAC1 & DAC2 use DMA  0: DAC1 & DAC2 do not use DMA*/
+#define SENS_DAC_DIG_FORCE  (BIT(22))
+#define SENS_DAC_DIG_FORCE_M  (BIT(22))
+#define SENS_DAC_DIG_FORCE_V  0x1
+#define SENS_DAC_DIG_FORCE_S  22
+/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: */
+#define SENS_DEBUG_BIT_SEL  0x0000001F
+#define SENS_DEBUG_BIT_SEL_M  ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S))
+#define SENS_DEBUG_BIT_SEL_V  0x1F
+#define SENS_DEBUG_BIT_SEL_S  17
+/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: enable CW generator  0: disable CW generator*/
+#define SENS_SW_TONE_EN  (BIT(16))
+#define SENS_SW_TONE_EN_M  (BIT(16))
+#define SENS_SW_TONE_EN_V  0x1
+#define SENS_SW_TONE_EN_S  16
+/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: frequency step for CW generator  can be used to adjust the frequency*/
+#define SENS_SW_FSTEP  0x0000FFFF
+#define SENS_SW_FSTEP_M  ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S))
+#define SENS_SW_FSTEP_V  0xFFFF
+#define SENS_SW_FSTEP_S  0
+
+#define SENS_SAR_DAC_CTRL2_REG          (DR_REG_SENS_BASE + 0x009c)
+/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]  0: to
+ select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/
+#define SENS_DAC_CW_EN2  (BIT(25))
+#define SENS_DAC_CW_EN2_M  (BIT(25))
+#define SENS_DAC_CW_EN2_V  0x1
+#define SENS_DAC_CW_EN2_S  25
+/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]  0: to
+ select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/
+#define SENS_DAC_CW_EN1  (BIT(24))
+#define SENS_DAC_CW_EN1_M  (BIT(24))
+#define SENS_DAC_CW_EN1_V  0x1
+#define SENS_DAC_CW_EN1_S  24
+/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB
+  11: invert all bits except MSB*/
+#define SENS_DAC_INV2  0x00000003
+#define SENS_DAC_INV2_M  ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S))
+#define SENS_DAC_INV2_V  0x3
+#define SENS_DAC_INV2_S  22
+/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */
+/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB
+  11: invert all bits except MSB*/
+#define SENS_DAC_INV1  0x00000003
+#define SENS_DAC_INV1_M  ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S))
+#define SENS_DAC_INV1_V  0x3
+#define SENS_DAC_INV1_S  20
+/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
+#define SENS_DAC_SCALE2  0x00000003
+#define SENS_DAC_SCALE2_M  ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S))
+#define SENS_DAC_SCALE2_V  0x3
+#define SENS_DAC_SCALE2_S  18
+/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
+#define SENS_DAC_SCALE1  0x00000003
+#define SENS_DAC_SCALE1_M  ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S))
+#define SENS_DAC_SCALE1_V  0x3
+#define SENS_DAC_SCALE1_S  16
+/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: DC offset for DAC2 CW generator*/
+#define SENS_DAC_DC2  0x000000FF
+#define SENS_DAC_DC2_M  ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S))
+#define SENS_DAC_DC2_V  0xFF
+#define SENS_DAC_DC2_S  8
+/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: DC offset for DAC1 CW generator*/
+#define SENS_DAC_DC1  0x000000FF
+#define SENS_DAC_DC1_M  ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S))
+#define SENS_DAC_DC1_V  0xFF
+#define SENS_DAC_DC1_S  0
+
+#define SENS_SAR_MEAS_CTRL2_REG          (DR_REG_SENS_BASE + 0x0a0)
+/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FORCE  0x00000003
+#define SENS_AMP_SHORT_REF_GND_FORCE_M  ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S))
+#define SENS_AMP_SHORT_REF_GND_FORCE_V  0x3
+#define SENS_AMP_SHORT_REF_GND_FORCE_S  17
+/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FORCE  0x00000003
+#define SENS_AMP_SHORT_REF_FORCE_M  ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S))
+#define SENS_AMP_SHORT_REF_FORCE_V  0x3
+#define SENS_AMP_SHORT_REF_FORCE_S  15
+/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FORCE  0x00000003
+#define SENS_AMP_RST_FB_FORCE_M  ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S))
+#define SENS_AMP_RST_FB_FORCE_V  0x3
+#define SENS_AMP_RST_FB_FORCE_S  13
+/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */
+/*description: */
+#define SENS_SAR2_RSTB_FORCE  0x00000003
+#define SENS_SAR2_RSTB_FORCE_M  ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S))
+#define SENS_SAR2_RSTB_FORCE_V  0x3
+#define SENS_SAR2_RSTB_FORCE_S  11
+/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR_RSTB_FSM_IDLE  (BIT(10))
+#define SENS_SAR_RSTB_FSM_IDLE_M  (BIT(10))
+#define SENS_SAR_RSTB_FSM_IDLE_V  0x1
+#define SENS_SAR_RSTB_FSM_IDLE_S  10
+/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_XPD_SAR_FSM_IDLE  (BIT(9))
+#define SENS_XPD_SAR_FSM_IDLE_M  (BIT(9))
+#define SENS_XPD_SAR_FSM_IDLE_V  0x1
+#define SENS_XPD_SAR_FSM_IDLE_S  9
+/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE  (BIT(8))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M  (BIT(8))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V  0x1
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S  8
+/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FSM_IDLE  (BIT(7))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_M  (BIT(7))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_V  0x1
+#define SENS_AMP_SHORT_REF_FSM_IDLE_S  7
+/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FSM_IDLE  (BIT(6))
+#define SENS_AMP_RST_FB_FSM_IDLE_M  (BIT(6))
+#define SENS_AMP_RST_FB_FSM_IDLE_V  0x1
+#define SENS_AMP_RST_FB_FSM_IDLE_S  6
+/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_XPD_SAR_AMP_FSM_IDLE  (BIT(5))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_M  (BIT(5))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_V  0x1
+#define SENS_XPD_SAR_AMP_FSM_IDLE_S  5
+/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR1_DAC_XPD_FSM_IDLE  (BIT(4))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_M  (BIT(4))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_V  0x1
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_S  4
+/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_SAR1_DAC_XPD_FSM  0x0000000F
+#define SENS_SAR1_DAC_XPD_FSM_M  ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S))
+#define SENS_SAR1_DAC_XPD_FSM_V  0xF
+#define SENS_SAR1_DAC_XPD_FSM_S  0
+
+#define SENS_SAR_NOUSE_REG          (DR_REG_SENS_BASE + 0x00F8)
+/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR_NOUSE  0xFFFFFFFF
+#define SENS_SAR_NOUSE_M  ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S))
+#define SENS_SAR_NOUSE_V  0xFFFFFFFF
+#define SENS_SAR_NOUSE_S  0
+
+#define SENS_SARDATE_REG          (DR_REG_SENS_BASE + 0x00FC)
+/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1605180 ; */
+/*description: */
+#define SENS_SAR_DATE  0x0FFFFFFF
+#define SENS_SAR_DATE_M  ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S))
+#define SENS_SAR_DATE_V  0xFFFFFFF
+#define SENS_SAR_DATE_S  0
+
+
+
+
+#endif /*_SOC_SENS_REG_H_ */
+
+

diff --git a/components/esp32/include/soc/soc.h b/components/esp32/include/soc/soc.h
index 04551f61fedb86e3a7e53604e706fcf054de7e6e..3991152f2137affc89bca92bd4a9b33393a67cfd 100755 (executable)
--- a/components/esp32/include/soc/soc.h
+++ b/components/esp32/include/soc/soc.h
@@ -153,7 +153,7 @@
 #define DR_REG_FRC_TIMER_BASE                   0x3ff47000
 #define DR_REG_RTCCNTL_BASE                     0x3ff48000
 #define DR_REG_RTCIO_BASE                       0x3ff48400
-#define DR_REG_SARADC_BASE                      0x3ff48800
+#define DR_REG_SENS_BASE                      0x3ff48800
 #define DR_REG_IO_MUX_BASE                      0x3ff49000
 #define DR_REG_RTCMEM0_BASE                     0x3ff61000
 #define DR_REG_RTCMEM1_BASE                     0x3ff62000

diff --git a/components/ulp/ulp.c b/components/ulp/ulp.c
index 5583055e60c118c68cad4562310b63a84657d9e7..228e3ff16d7173c84d6f52ba422a23a2aa5a22b5 100644 (file)
--- a/components/ulp/ulp.c
+++ b/components/ulp/ulp.c
@@ -23,7 +23,7 @@
 
 #include "soc/soc.h"
 #include "soc/rtc_cntl_reg.h"
-#include "soc/saradc_reg.h"
+#include "soc/sens_reg.h"
 
 #include "sdkconfig.h"
 
@@ -263,8 +263,8 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog
 
 esp_err_t ulp_run(uint32_t entry_point)
 {
-    SET_PERI_REG_MASK(SARADC_SAR_START_FORCE_REG, SARADC_ULP_CP_FORCE_START_TOP_M);
-    SET_PERI_REG_BITS(SARADC_SAR_START_FORCE_REG, SARADC_PC_INIT_V, entry_point, SARADC_PC_INIT_S);
-    SET_PERI_REG_MASK(SARADC_SAR_START_FORCE_REG, SARADC_ULP_CP_START_TOP_M);
+    SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP_M);
+    SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_PC_INIT_V, entry_point, SENS_PC_INIT_S);
+    SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP_M);
     return ESP_OK;
 }