[AArch64][SVE2] Asm: support SVE2 store instructions

Summary:
Patch adds support for the following instructions:
    * STNT1B, STNT1H, STNT1S, STNT1D

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Reviewed By: chill

Differential Revision: https://reviews.llvm.org/D62599

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362213 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index e89dc905415612411c17c2314e74d4fe21bd6a02..a7d31cc0c6b205a35dfe51a04214c9626c049646 100644 (file)
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1357,6 +1357,16 @@ let Predicates = [HasSVE2] in {
   defm SRSHR_ZPmI  : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
   defm URSHR_ZPmI  : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
   defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
+
+  // Non-temporal contiguous stores (vector + register)
+  defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
+  defm STNT1H_ZZR_S : sve2_mem_cstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
+  defm STNT1W_ZZR_S : sve2_mem_cstnt_vs<0b101, "stnt1w", Z_s, ZPR32>;
+
+  defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
+  defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
+  defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
+  defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
 }
 
 let Predicates = [HasSVE2AES] in {

diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index f22995489690f542ba0af5884d88831dcb5a4005..afe845a52e56580ed21ea6c18cbb81ac868a5eb9 100644 (file)
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -3827,6 +3827,43 @@ multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
+class sve2_mem_cstnt_vs_base<bits<3> opc, dag iops, string asm,
+                             RegisterOperand VecList>
+: I<(outs VecList:$Zt), iops,
+  asm, "\t$Zt, $Pg, [$Zn, $Rm]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Rm;
+  bits<5> Zn;
+  bits<5> Zt;
+  let Inst{31-25} = 0b1110010;
+  let Inst{24-22} = opc;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Rm;
+  let Inst{15-13} = 0b001;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zt;
+
+  let mayStore = 1;
+}
+
+multiclass sve2_mem_cstnt_vs<bits<3> opc, string asm,
+                             RegisterOperand listty, ZPRRegOp zprty> {
+  def _REAL : sve2_mem_cstnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
+                                     asm, listty>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
+                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
+                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
+                 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
+                 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
+}
+
 class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
                      RegisterOperand VecList, RegisterOperand zprext>
 : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),

diff --git a/test/MC/AArch64/SVE/stnt1b-diagnostics.s b/test/MC/AArch64/SVE/stnt1b-diagnostics.s
index 4b7806e5b0e817c6684e8532a11c0fc054a8eac8..0d0488d810e8e22122f04e4fb0ed90aebe1f0be5 100644 (file)
--- a/test/MC/AArch64/SVE/stnt1b-diagnostics.s
+++ b/test/MC/AArch64/SVE/stnt1b-diagnostics.s
@@ -23,12 +23,12 @@ stnt1b z0.h, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.s, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: stnt1b z0.s, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 stnt1b z0.d, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: stnt1b z0.d, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

diff --git a/test/MC/AArch64/SVE2/stnt1b-diagnostics.s b/test/MC/AArch64/SVE2/stnt1b-diagnostics.s
new file mode 100644 (file)
index 0000000..dbf30a6
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1b-diagnostics.s
@@ -0,0 +1,82 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Invalid result type.
+
+stnt1b { z0.b }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b { z0.b }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b { z0.h }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b { z0.h }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid base vector.
+
+stnt1b { z0.s }, p0, [z0.b]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.b]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b { z0.d }, p0, [z0.h]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.h]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid offset type.
+
+stnt1b { z0.d }, p0, [z0.d, z1.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+stnt1b { z27.d }, p8, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+stnt1b { }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: stnt1b { }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b { z0.d, z1.d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b { z0.d, z1.d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b { v0.2d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b { v0.2d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+stnt1b  { z0.d }, p0, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1b  { z0.d }, p0, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+stnt1b  { z0.s }, p0, [z0.s, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1b  { z0.s }, p0, [z0.s, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE2/stnt1b.s b/test/MC/AArch64/SVE2/stnt1b.s
new file mode 100644 (file)
index 0000000..cab8a6b
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1b.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+stnt1b z0.s, p0, [z1.s]
+// CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
+// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
+
+stnt1b z31.s, p7, [z31.s, xzr]
+// CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
+// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
+
+stnt1b z31.s, p7, [z31.s, x0]
+// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
+
+stnt1b z0.d, p0, [z1.d]
+// CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
+
+stnt1b z31.d, p7, [z31.d, xzr]
+// CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
+
+stnt1b z31.d, p7, [z31.d, x0]
+// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>
+
+stnt1b { z0.s }, p0, [z1.s]
+// CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
+// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
+
+stnt1b { z31.s }, p7, [z31.s, xzr]
+// CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
+// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
+
+stnt1b { z31.s }, p7, [z31.s, x0]
+// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
+
+stnt1b { z0.d }, p0, [z1.d]
+// CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
+
+stnt1b { z31.d }, p7, [z31.d, xzr]
+// CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
+
+stnt1b { z31.d }, p7, [z31.d, x0]
+// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>

diff --git a/test/MC/AArch64/SVE2/stnt1d-diagnostics.s b/test/MC/AArch64/SVE2/stnt1d-diagnostics.s
new file mode 100644 (file)
index 0000000..c5be826
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1d-diagnostics.s
@@ -0,0 +1,82 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Invalid result type.
+
+stnt1d { z0.b }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d { z0.b }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1d { z0.h }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d { z0.h }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1d { z0.s }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d { z0.s }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid base vector.
+
+stnt1d { z0.d }, p0, [z0.b]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.b]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid offset type.
+
+stnt1d { z0.d }, p0, [z0.d, z1.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+stnt1d { z27.d }, p8, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+stnt1d { }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: stnt1d { }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1d { z0.d, z1.d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d { z0.d, z1.d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1d { v0.2d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d { v0.2d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+stnt1d  { z0.d }, p0, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1d  { z0.d }, p0, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+stnt1d  { z0.d }, p0, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1d  { z0.d }, p0, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE2/stnt1d.s b/test/MC/AArch64/SVE2/stnt1d.s
new file mode 100644 (file)
index 0000000..462b8bc
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1d.s
@@ -0,0 +1,44 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+stnt1d z0.d, p0, [z1.d]
+// CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
+
+stnt1d z31.d, p7, [z31.d, xzr]
+// CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
+
+stnt1d z31.d, p7, [z31.d, x0]
+// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>
+
+stnt1d { z0.d }, p0, [z1.d]
+// CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
+
+stnt1d { z31.d }, p7, [z31.d, xzr]
+// CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
+
+stnt1d { z31.d }, p7, [z31.d, x0]
+// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>

diff --git a/test/MC/AArch64/SVE2/stnt1h-diagnostics.s b/test/MC/AArch64/SVE2/stnt1h-diagnostics.s
new file mode 100644 (file)
index 0000000..db60d05
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1h-diagnostics.s
@@ -0,0 +1,82 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Invalid result type.
+
+stnt1h { z0.b }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1h { z0.b }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1h { z0.h }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1h { z0.h }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid base vector.
+
+stnt1h { z0.s }, p0, [z0.b]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.b]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1h { z0.d }, p0, [z0.h]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.h]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid offset type.
+
+stnt1h { z0.d }, p0, [z0.d, z1.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+stnt1h { z27.d }, p8, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+stnt1h { }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: stnt1h { }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1h { z0.d, z1.d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1h { z0.d, z1.d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1h { v0.2d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1h { v0.2d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+stnt1h  { z0.d }, p0, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1h  { z0.d }, p0, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+stnt1h  { z0.s }, p0, [z0.s, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1h  { z0.s }, p0, [z0.s, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE2/stnt1h.s b/test/MC/AArch64/SVE2/stnt1h.s
new file mode 100644 (file)
index 0000000..07c9c32
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1h.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+stnt1h z0.s, p0, [z1.s]
+// CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
+// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 df e4 <unknown>
+
+stnt1h z31.s, p7, [z31.s, xzr]
+// CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
+// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f df e4 <unknown>
+
+stnt1h z31.s, p7, [z31.s, x0]
+// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
+// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
+
+stnt1h z0.d, p0, [z1.d]
+// CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
+
+stnt1h z31.d, p7, [z31.d, xzr]
+// CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
+
+stnt1h z31.d, p7, [z31.d, x0]
+// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>
+
+stnt1h { z0.s }, p0, [z1.s]
+// CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
+// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 df e4 <unknown>
+
+stnt1h { z31.s }, p7, [z31.s, xzr]
+// CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
+// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f df e4 <unknown>
+
+stnt1h { z31.s }, p7, [z31.s, x0]
+// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
+// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
+
+stnt1h { z0.d }, p0, [z1.d]
+// CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
+
+stnt1h { z31.d }, p7, [z31.d, xzr]
+// CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
+
+stnt1h { z31.d }, p7, [z31.d, x0]
+// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>

diff --git a/test/MC/AArch64/SVE2/stnt1w-diagnostics.s b/test/MC/AArch64/SVE2/stnt1w-diagnostics.s
new file mode 100644 (file)
index 0000000..c552e36
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1w-diagnostics.s
@@ -0,0 +1,82 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Invalid result type.
+
+stnt1w { z0.b }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1w { z0.b }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1w { z0.h }, p0, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1w { z0.h }, p0, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid base vector.
+
+stnt1w { z0.s }, p0, [z0.b]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.b]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1w { z0.d }, p0, [z0.h]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.h]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid offset type.
+
+stnt1w { z0.d }, p0, [z0.d, z1.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// restricted predicate has range [0, 7].
+
+stnt1w { z27.d }, p8, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector list.
+
+stnt1w { }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
+// CHECK-NEXT: stnt1w { }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1w { z0.d, z1.d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1w { z0.d, z1.d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1w { v0.2d }, p0, [z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1w { v0.2d }, p0, [z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+stnt1w  { z0.d }, p0, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1w  { z0.d }, p0, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+movprfx z0, z7
+stnt1w  { z0.s }, p0, [z0.s, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: stnt1w  { z0.s }, p0, [z0.s, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE2/stnt1w.s b/test/MC/AArch64/SVE2/stnt1w.s
new file mode 100644 (file)
index 0000000..90d4c8e
--- /dev/null
+++ b/test/MC/AArch64/SVE2/stnt1w.s
@@ -0,0 +1,80 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+stnt1w z0.s, p0, [z1.s]
+// CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
+// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
+
+stnt1w z31.s, p7, [z31.s, xzr]
+// CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
+// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
+
+stnt1w z31.s, p7, [z31.s, x0]
+// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
+
+stnt1w z0.d, p0, [z1.d]
+// CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
+
+stnt1w z31.d, p7, [z31.d, xzr]
+// CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
+
+stnt1w z31.d, p7, [z31.d, x0]
+// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>
+
+stnt1w { z0.s }, p0, [z1.s]
+// CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
+// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
+
+stnt1w { z31.s }, p7, [z31.s, xzr]
+// CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
+// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
+
+stnt1w { z31.s }, p7, [z31.s, x0]
+// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
+
+stnt1w { z0.d }, p0, [z1.d]
+// CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
+// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
+
+stnt1w { z31.d }, p7, [z31.d, xzr]
+// CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
+
+stnt1w { z31.d }, p7, [z31.d, x0]
+// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
+// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>