AMDGPU: Move si_mask_branch register operand to be a use

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274818 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index 77f67b492f424efcef536151af64bfdc8380ba47..e1e6f2eb3a39a9a557e9adbe015602fd5f4449f3 100644 (file)
--- a/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -113,7 +113,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
         SmallVector<char, 16> BBStr;
         raw_svector_ostream Str(BBStr);
 
-        const MachineBasicBlock *MBB = MI->getOperand(1).getMBB();
+        const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
         const MCSymbolRefExpr *Expr
           = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
         Expr->print(Str, MAI);

diff --git a/lib/Target/AMDGPU/SIInstructions.td b/lib/Target/AMDGPU/SIInstructions.td
index 9eff2e056a8f6c1c9a6ae20320e794cd2aeb2d1f..46b3e50b78b8dfd57faed4d575b4af2376c3ac9b 100644 (file)
--- a/lib/Target/AMDGPU/SIInstructions.td
+++ b/lib/Target/AMDGPU/SIInstructions.td
@@ -1929,7 +1929,7 @@ let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1 in {
 // Dummy terminator instruction to use after control flow instructions
 // replaced with exec mask operations.
 def SI_MASK_BRANCH : InstSI <
-  (outs SReg_64:$dst), (ins brtarget:$target)> {
+  (outs), (ins brtarget:$target, SReg_64:$dst)> {
   let isBranch = 1;
   let isTerminator = 1;
   let isBarrier = 1;

diff --git a/lib/Target/AMDGPU/SILowerControlFlow.cpp b/lib/Target/AMDGPU/SILowerControlFlow.cpp
index 7ef8904e69375a758f0c16b1de35b5c0657f0f8f..81dfd91999831f73263fe54eb5e38fc0f7798149 100644 (file)
--- a/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -237,8 +237,9 @@ void SILowerControlFlow::If(MachineInstr &MI) {
   Skip(MI, MI.getOperand(2));
 
   // Insert a pseudo terminator to help keep the verifier happy.
-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Reg)
-    .addOperand(MI.getOperand(2));
+  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
+    .addOperand(MI.getOperand(2))
+    .addReg(Reg);
 
   MI.eraseFromParent();
 }
@@ -269,8 +270,9 @@ void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) {
   Skip(MI, MI.getOperand(2));
 
   // Insert a pseudo terminator to help keep the verifier happy.
-  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH), Dst)
-    .addOperand(MI.getOperand(2));
+  BuildMI(MBB, &MI, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
+    .addOperand(MI.getOperand(2))
+    .addReg(Dst);
 
   MI.eraseFromParent();
 }