class TargetSchedModel;
class TargetSubtargetInfo;
-template<class T> class SmallVectorImpl;
+template <class T> class SmallVectorImpl;
//---------------------------------------------------------------------------
///
TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
: CallFrameSetupOpcode(CFSetupOpcode),
- CallFrameDestroyOpcode(CFDestroyOpcode),
- CatchRetOpcode(CatchRetOpcode),
+ CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
ReturnOpcode(ReturnOpcode) {}
TargetInstrInfo(const TargetInstrInfo &) = delete;
TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
/// Given a machine instruction descriptor, returns the register
/// class constraint for OpNum, or NULL.
- const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
- unsigned OpNum,
+ const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
const TargetRegisterInfo *TRI,
const MachineFunction &MF) const;
/// the fixed result pair is equal to or equivalent to the source pair of
/// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
/// the pairs (x,y) and (y,x) are equivalent.
- static bool fixCommutedOpIndices(unsigned &ResultIdx1,
- unsigned &ResultIdx2,
+ static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
unsigned CommutableOpIdx1,
unsigned CommutableOpIdx2);
/// Returns true if the argument is a frame pseudo instruction.
bool isFrameInstr(const MachineInstr &I) const {
return I.getOpcode() == getCallFrameSetupOpcode() ||
- I.getOpcode() == getCallFrameDestroyOpcode();
+ I.getOpcode() == getCallFrameDestroyOpcode();
}
/// Returns true if the argument is a frame setup pseudo instruction.
/// prior to the pair.
int64_t getFrameTotalSize(const MachineInstr &I) const {
if (isFrameSetup(I)) {
- assert(I.getOperand(1).getImm() >= 0 && "Frame size must not be negative");
+ assert(I.getOperand(1).getImm() >= 0 &&
+ "Frame size must not be negative");
return getFrameSize(I) + I.getOperand(1).getImm();
}
return getFrameSize(I);
/// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
/// expected the pre-extension value is available as a subreg of the result
/// register. This also returns the sub-register index in SubIdx.
- virtual bool isCoalescableExtInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SubIdx) const {
+ virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
+ unsigned &DstReg, unsigned &SubIdx) const {
return false;
}
/// MachineSink determines on its own whether the instruction is safe to sink;
/// this gives the target a hook to override the default behavior with regards
/// to which instructions should be sunk.
- virtual bool shouldSink(const MachineInstr &MI) const {
- return true;
- }
+ virtual bool shouldSink(const MachineInstr &MI) const { return true; }
/// Re-issue the specified 'original' instruction at the
/// specific location targeting a new destination register.
/// \note The generic implementation does not provide any support for
/// MI.isExtractSubregLike(). In other words, one has to override
/// getExtractSubregLikeInputs for target specific instructions.
- bool
- getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
- RegSubRegPairAndIdx &InputReg) const;
+ bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
+ RegSubRegPairAndIdx &InputReg) const;
/// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
/// and \p DefIdx.
/// \note The generic implementation does not provide any support for
/// MI.isInsertSubregLike(). In other words, one has to override
/// getInsertSubregLikeInputs for target specific instructions.
- bool
- getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
- RegSubRegPair &BaseReg,
- RegSubRegPairAndIdx &InsertedReg) const;
+ bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
+ RegSubRegPair &BaseReg,
+ RegSubRegPairAndIdx &InsertedReg) const;
/// Return true if two machine instructions would produce identical values.
/// By default, this is only true when the two instructions
MachineBasicBlock *DestBB,
const DebugLoc &DL,
int *BytesAdded = nullptr) const {
- return insertBranch(MBB, DestBB, nullptr,
- ArrayRef<MachineOperand>(), DL, BytesAdded);
+ return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
+ BytesAdded);
}
/// Analyze the loop code, return true if it cannot be understoo. Upon
/// finished. Return the value/register of the the new loop count. We need
/// this function when peeling off one or more iterations of a loop. This
/// function assumes the nth iteration is peeled first.
- virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
- MachineInstr *IndVar, MachineInstr &Cmp,
+ virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
+ MachineInstr &Cmp,
SmallVectorImpl<MachineOperand> &Cond,
SmallVectorImpl<MachineInstr *> &PrevInsts,
unsigned Iter, unsigned MaxIter) const {
/// of the specified basic block, where the probability of the instructions
/// being executed is given by Probability, and Confidence is a measure
/// of our confidence that it will be properly predicted.
- virtual
- bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
- unsigned ExtraPredCycles,
- BranchProbability Probability) const {
+ virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
+ unsigned ExtraPredCycles,
+ BranchProbability Probability) const {
return false;
}
/// predicates, where the probability of the true path being taken is given
/// by Probability, and Confidence is a measure of our confidence that it
/// will be properly predicted.
- virtual bool
- isProfitableToIfCvt(MachineBasicBlock &TMBB,
- unsigned NumTCycles, unsigned ExtraTCycles,
- MachineBasicBlock &FMBB,
- unsigned NumFCycles, unsigned ExtraFCycles,
- BranchProbability Probability) const {
+ virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
+ unsigned ExtraTCycles,
+ MachineBasicBlock &FMBB, unsigned NumFCycles,
+ unsigned ExtraFCycles,
+ BranchProbability Probability) const {
return false;
}
/// The probability of the instructions being executed is given by
/// Probability, and Confidence is a measure of our confidence that it
/// will be properly predicted.
- virtual bool
- isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
- BranchProbability Probability) const {
+ virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
+ unsigned NumCycles,
+ BranchProbability Probability) const {
return false;
}
/// @param TrueCycles Latency from TrueReg to select output.
/// @param FalseCycles Latency from FalseReg to select output.
virtual bool canInsertSelect(const MachineBasicBlock &MBB,
- ArrayRef<MachineOperand> Cond,
- unsigned TrueReg, unsigned FalseReg,
- int &CondCycles,
+ ArrayRef<MachineOperand> Cond, unsigned TrueReg,
+ unsigned FalseReg, int &CondCycles,
int &TrueCycles, int &FalseCycles) const {
return false;
}
/// Set special operand attributes for new instructions after reassociation.
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
MachineInstr &NewMI1,
- MachineInstr &NewMI2) const {
- }
+ MachineInstr &NewMI2) const {}
/// Return true when a target supports MachineCombiner.
virtual bool useMachineCombiner() const { return false; }
/// \pre MI.isExtractSubregLike().
///
/// \see TargetInstrInfo::getExtractSubregInputs.
- virtual bool getExtractSubregLikeInputs(
- const MachineInstr &MI, unsigned DefIdx,
- RegSubRegPairAndIdx &InputReg) const {
+ virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
+ unsigned DefIdx,
+ RegSubRegPairAndIdx &InputReg) const {
return false;
}
}
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
- SmallVectorImpl<SDNode*> &NewNodes) const {
+ SmallVectorImpl<SDNode *> &NewNodes) const {
return false;
}
/// possible. If LoadRegIndex is non-null, it is filled in with the operand
/// index of the operand which will hold the register holding the loaded
/// value.
- virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
- bool UnfoldLoad, bool UnfoldStore,
- unsigned *LoadRegIndex = nullptr) const {
+ virtual unsigned
+ getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
+ unsigned *LoadRegIndex = nullptr) const {
return 0;
}
/// pointers are the same and the only differences between the two addresses
/// are the offset. It also returns the offsets by reference.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
- int64_t &Offset1, int64_t &Offset2) const {
+ int64_t &Offset1,
+ int64_t &Offset2) const {
return false;
}
/// Reverses the branch condition of the specified condition list,
/// returning false on success and true if it cannot be reversed.
- virtual
- bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
+ virtual bool
+ reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
return true;
}
virtual void getNoop(MCInst &NopInst) const;
/// Return true for post-incremented instructions.
- virtual bool isPostIncrement(const MachineInstr &MI) const {
- return false;
- }
+ virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
/// Returns true if the instruction is already predicated.
- virtual bool isPredicated(const MachineInstr &MI) const {
- return false;
- }
+ virtual bool isPredicated(const MachineInstr &MI) const { return false; }
/// Returns true if the instruction is a
/// terminator instruction that has not been predicated.
}
/// Returns true if the tail call can be made conditional on BranchCond.
- virtual bool
- canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
- const MachineInstr &TailCall) const {
+ virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
+ const MachineInstr &TailCall) const {
return false;
}
/// Returns true if the first specified predicate
/// subsumes the second, e.g. GE subsumes GT.
- virtual
- bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
- ArrayRef<MachineOperand> Pred2) const {
+ virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
+ ArrayRef<MachineOperand> Pred2) const {
return false;
}
/// Allocate and return a hazard recognizer to use for this target when
/// scheduling the machine instructions before register allocation.
- virtual ScheduleHazardRecognizer*
+ virtual ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
const ScheduleDAG *DAG) const;
/// Allocate and return a hazard recognizer to use for this target when
/// scheduling the machine instructions before register allocation.
- virtual ScheduleHazardRecognizer*
- CreateTargetMIHazardRecognizer(const InstrItineraryData*,
+ virtual ScheduleHazardRecognizer *
+ CreateTargetMIHazardRecognizer(const InstrItineraryData *,
const ScheduleDAG *DAG) const;
/// Allocate and return a hazard recognizer to use for this target when
/// scheduling the machine instructions after register allocation.
- virtual ScheduleHazardRecognizer*
- CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
+ virtual ScheduleHazardRecognizer *
+ CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
const ScheduleDAG *DAG) const;
/// Allocate and return a hazard recognizer to use for by non-scheduling
/// passes.
- virtual ScheduleHazardRecognizer*
+ virtual ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
return nullptr;
}
/// \brief Return the value to use for the MachineCSE's LookAheadLimit,
/// which is a heuristic used for CSE'ing phys reg defs.
- virtual unsigned getMachineCSELookAheadLimit () const {
+ virtual unsigned getMachineCSELookAheadLimit() const {
// The default lookahead is small to prevent unprofitable quadratic
// behavior.
return 5;
return false;
}
- /// \brief Return how many instructions would be saved by outlining a
- /// sequence containing \p SequenceSize instructions that appears
- /// \p Occurrences times in a module.
- virtual unsigned getOutliningBenefit(size_t SequenceSize, size_t Occurrences,
- bool CanBeTailCall) const {
+ /// \brief Returns the number of instructions that will be taken to call a
+ /// function defined by the sequence on the closed interval [ \p StartIt, \p
+ /// EndIt].
+ virtual size_t
+ getOutliningCallOverhead(MachineBasicBlock::iterator &StartIt,
+ MachineBasicBlock::iterator &EndIt) const {
+ llvm_unreachable(
+ "Target didn't implement TargetInstrInfo::getOutliningCallOverhead!");
+ }
+
+ /// \brief Returns the number of instructions that will be taken to construct
+ /// an outlined function frame for a function defined on the closed interval
+ /// [ \p StartIt, \p EndIt].
+ virtual size_t
+ getOutliningFrameOverhead(MachineBasicBlock::iterator &StartIt,
+ MachineBasicBlock::iterator &EndIt) const {
llvm_unreachable(
- "Target didn't implement TargetInstrInfo::getOutliningBenefit!");
+ "Target didn't implement TargetInstrInfo::getOutliningCallOverhead!");
}
/// Represents how an instruction should be mapped by the outliner.
/// \p Illegal instructions are those which cannot be outlined.
/// \p Invisible instructions are instructions which can be outlined, but
/// shouldn't actually impact the outlining result.
- enum MachineOutlinerInstrType {Legal, Illegal, Invisible};
+ enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
/// Returns how or if \p MI should be outlined.
virtual MachineOutlinerInstrType getOutliningType(MachineInstr &MI) const {
};
/// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
-template<>
-struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
+template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
using RegInfo = DenseMapInfo<unsigned>;
static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
- RegInfo::getEmptyKey());
+ RegInfo::getEmptyKey());
}
static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
- RegInfo::getTombstoneKey());
+ RegInfo::getTombstoneKey());
}
/// \brief Reuse getHashValue implementation from
/// std::pair<unsigned, unsigned>.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
- std::pair<unsigned, unsigned> PairVal =
- std::make_pair(Val.Reg, Val.SubReg);
+ std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
}
#define GET_INSTRINFO_CTOR_DTOR
#include "AArch64GenInstrInfo.inc"
-static cl::opt<unsigned>
-TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
- cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"));
+static cl::opt<unsigned> TBZDisplacementBits(
+ "aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
+ cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"));
-static cl::opt<unsigned>
-CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
- cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"));
+static cl::opt<unsigned> CBZDisplacementBits(
+ "aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
+ cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"));
static cl::opt<unsigned>
-BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
- cl::desc("Restrict range of Bcc instructions (DEBUG)"));
+ BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
+ cl::desc("Restrict range of Bcc instructions (DEBUG)"));
AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
: AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
return isIntN(Bits, BrOffset / 4);
}
-MachineBasicBlock *AArch64InstrInfo::getBranchDestBlock(
- const MachineInstr &MI) const {
+MachineBasicBlock *
+AArch64InstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
default:
llvm_unreachable("unexpected opcode!");
}
}
-unsigned AArch64InstrInfo::insertBranch(MachineBasicBlock &MBB,
- MachineBasicBlock *TBB,
- MachineBasicBlock *FBB,
- ArrayRef<MachineOperand> Cond,
- const DebugLoc &DL,
- int *BytesAdded) const {
+unsigned AArch64InstrInfo::insertBranch(
+ MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
+ ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
// Shouldn't be a fall through.
assert(TBB && "insertBranch must not be told to insert a fallthrough");
return Opc;
}
-bool AArch64InstrInfo::canInsertSelect(
- const MachineBasicBlock &MBB, ArrayRef<MachineOperand> Cond,
- unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
- int &FalseCycles) const {
+bool AArch64InstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
+ ArrayRef<MachineOperand> Cond,
+ unsigned TrueReg, unsigned FalseReg,
+ int &CondCycles, int &TrueCycles,
+ int &FalseCycles) const {
// Check register classes.
const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
const TargetRegisterClass *RC =
MRI.constrainRegClass(FalseReg, RC);
// Insert the csel.
- BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
- CC);
+ BuildMI(MBB, I, DL, get(Opc), DstReg)
+ .addReg(TrueReg)
+ .addReg(FalseReg)
+ .addImm(CC);
}
/// Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.
}
}
-enum AccessKind {
- AK_Write = 0x01,
- AK_Read = 0x10,
- AK_All = 0x11
-};
+enum AccessKind { AK_Write = 0x01, AK_Read = 0x10, AK_All = 0x11 };
/// True when condition flags are accessed (either by writing or reading)
/// on the instruction trace starting at From and ending at To.
for (--To; To != From; --To) {
const MachineInstr &Instr = *To;
- if ( ((AccessToCheck & AK_Write) && Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
- ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
+ if (((AccessToCheck & AK_Write) &&
+ Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
+ ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
return true;
}
return false;
}
/// Try to optimize a compare instruction. A compare instruction is an
-/// instruction which produces AArch64::NZCV. It can be truly compare instruction
+/// instruction which produces AArch64::NZCV. It can be truly compare
+/// instruction
/// when there are no uses of its destination register.
///
/// The following steps are tried in order:
/// 1. Convert CmpInstr into an unconditional version.
/// 2. Remove CmpInstr if above there is an instruction producing a needed
-/// condition code or an instruction which can be converted into such an instruction.
+/// condition code or an instruction which can be converted into such an
+/// instruction.
/// Only comparison with zero is supported.
bool AArch64InstrInfo::optimizeCompareInstr(
MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
case AArch64::SUBSXri:
return Instr.getOpcode();
- case AArch64::ADDWrr: return AArch64::ADDSWrr;
- case AArch64::ADDWri: return AArch64::ADDSWri;
- case AArch64::ADDXrr: return AArch64::ADDSXrr;
- case AArch64::ADDXri: return AArch64::ADDSXri;
- case AArch64::ADCWr: return AArch64::ADCSWr;
- case AArch64::ADCXr: return AArch64::ADCSXr;
- case AArch64::SUBWrr: return AArch64::SUBSWrr;
- case AArch64::SUBWri: return AArch64::SUBSWri;
- case AArch64::SUBXrr: return AArch64::SUBSXrr;
- case AArch64::SUBXri: return AArch64::SUBSXri;
- case AArch64::SBCWr: return AArch64::SBCSWr;
- case AArch64::SBCXr: return AArch64::SBCSXr;
- case AArch64::ANDWri: return AArch64::ANDSWri;
- case AArch64::ANDXri: return AArch64::ANDSXri;
+ case AArch64::ADDWrr:
+ return AArch64::ADDSWrr;
+ case AArch64::ADDWri:
+ return AArch64::ADDSWri;
+ case AArch64::ADDXrr:
+ return AArch64::ADDSXrr;
+ case AArch64::ADDXri:
+ return AArch64::ADDSXri;
+ case AArch64::ADCWr:
+ return AArch64::ADCSWr;
+ case AArch64::ADCXr:
+ return AArch64::ADCSXr;
+ case AArch64::SUBWrr:
+ return AArch64::SUBSWrr;
+ case AArch64::SUBWri:
+ return AArch64::SUBSWri;
+ case AArch64::SUBXrr:
+ return AArch64::SUBSXrr;
+ case AArch64::SUBXri:
+ return AArch64::SUBSXri;
+ case AArch64::SBCWr:
+ return AArch64::SBCSWr;
+ case AArch64::SBCXr:
+ return AArch64::SBCSXr;
+ case AArch64::ANDWri:
+ return AArch64::ANDSWri;
+ case AArch64::ANDXri:
+ return AArch64::ANDSXri;
}
}
UsedNZCV() = default;
- UsedNZCV& operator |=(const UsedNZCV& UsedFlags) {
+ UsedNZCV &operator|=(const UsedNZCV &UsedFlags) {
this->N |= UsedFlags.N;
this->Z |= UsedFlags.Z;
this->C |= UsedFlags.C;
/// codes or we don't optimize CmpInstr in the presence of such instructions.
static AArch64CC::CondCode findCondCodeUsedByInstr(const MachineInstr &Instr) {
switch (Instr.getOpcode()) {
- default:
- return AArch64CC::Invalid;
+ default:
+ return AArch64CC::Invalid;
- case AArch64::Bcc: {
- int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
- assert(Idx >= 2);
-
return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 2).getImm());
- }
+ case AArch64::Bcc: {
+ int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
+ assert(Idx >= 2);
+ return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 2).getImm());
+ }
- case AArch64::CSINVWr:
- case AArch64::CSINVXr:
- case AArch64::CSINCWr:
- case AArch64::CSINCXr:
- case AArch64::CSELWr:
- case AArch64::CSELXr:
- case AArch64::CSNEGWr:
- case AArch64::CSNEGXr:
- case AArch64::FCSELSrrr:
- case AArch64::FCSELDrrr: {
- int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
- assert(Idx >= 1);
-
return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 1).getImm());
- }
+ case AArch64::CSINVWr:
+ case AArch64::CSINVXr:
+ case AArch64::CSINCWr:
+ case AArch64::CSINCXr:
+ case AArch64::CSELWr:
+ case AArch64::CSELXr:
+ case AArch64::CSNEGWr:
+ case AArch64::CSNEGXr:
+ case AArch64::FCSELSrrr:
+ case AArch64::FCSELDrrr: {
+ int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
+ assert(Idx >= 1);
+ return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 1).getImm());
+ }
}
}
assert(CC != AArch64CC::Invalid);
UsedNZCV UsedFlags;
switch (CC) {
- default:
- break;
+ default:
+ break;
- case AArch64CC::EQ: // Z set
- case AArch64CC::NE: // Z clear
- UsedFlags.Z = true;
- break;
+ case AArch64CC::EQ: // Z set
+ case AArch64CC::NE: // Z clear
+ UsedFlags.Z = true;
+ break;
- case AArch64CC::HI: // Z clear and C set
- case AArch64CC::LS: // Z set or C clear
- UsedFlags.Z = true;
- LLVM_FALLTHROUGH;
- case AArch64CC::HS: // C set
- case AArch64CC::LO: // C clear
- UsedFlags.C = true;
- break;
+ case AArch64CC::HI: // Z clear and C set
+ case AArch64CC::LS: // Z set or C clear
+ UsedFlags.Z = true;
+ LLVM_FALLTHROUGH;
+ case AArch64CC::HS: // C set
+ case AArch64CC::LO: // C clear
+ UsedFlags.C = true;
+ break;
- case AArch64CC::MI: // N set
- case AArch64CC::PL: // N clear
- UsedFlags.N = true;
- break;
+ case AArch64CC::MI: // N set
+ case AArch64CC::PL: // N clear
+ UsedFlags.N = true;
+ break;
- case AArch64CC::VS: // V set
- case AArch64CC::VC: // V clear
- UsedFlags.V = true;
- break;
+ case AArch64CC::VS: // V set
+ case AArch64CC::VC: // V clear
+ UsedFlags.V = true;
+ break;
- case AArch64CC::GT: // Z clear, N and V the same
- case AArch64CC::LE: // Z set, N and V differ
- UsedFlags.Z = true;
- LLVM_FALLTHROUGH;
- case AArch64CC::GE: // N and V the same
- case AArch64CC::LT: // N and V differ
- UsedFlags.N = true;
- UsedFlags.V = true;
- break;
+ case AArch64CC::GT: // Z clear, N and V the same
+ case AArch64CC::LE: // Z set, N and V differ
+ UsedFlags.Z = true;
+ LLVM_FALLTHROUGH;
+ case AArch64CC::GE: // N and V the same
+ case AArch64CC::LT: // N and V differ
+ UsedFlags.N = true;
+ UsedFlags.V = true;
+ break;
}
return UsedFlags;
}
/// nor uses of flags between MI and CmpInstr.
/// - and C/V flags are not used after CmpInstr
static bool canInstrSubstituteCmpInstr(MachineInstr *MI, MachineInstr *CmpInstr,
- const TargetRegisterInfo *TRI) {
+ const TargetRegisterInfo *TRI) {
assert(MI);
assert(sForm(*MI) != AArch64::INSTRUCTION_LIST_END);
assert(CmpInstr);
return false;
UsedNZCV NZCVUsedAfterCmp;
- for (auto I = std::next(CmpInstr->getIterator()), E = CmpInstr->getParent()->instr_end();
+ for (auto I = std::next(CmpInstr->getIterator()),
+ E = CmpInstr->getParent()->instr_end();
I != E; ++I) {
const MachineInstr &Instr = *I;
if (Instr.readsRegister(AArch64::NZCV, TRI)) {
if (Instr.modifiesRegister(AArch64::NZCV, TRI))
break;
}
-
+
return !NZCVUsedAfterCmp.C && !NZCVUsedAfterCmp.V;
}
.addMemOperand(*MI.memoperands_begin());
} else if (TM.getCodeModel() == CodeModel::Large) {
BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
- .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC).addImm(0);
+ .addGlobalAddress(GV, 0, AArch64II::MO_G0 | MO_NC)
+ .addImm(0);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
- .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC).addImm(16);
+ .addGlobalAddress(GV, 0, AArch64II::MO_G1 | MO_NC)
+ .addImm(16);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
- .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC).addImm(32);
+ .addGlobalAddress(GV, 0, AArch64II::MO_G2 | MO_NC)
+ .addImm(32);
BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
.addReg(Reg, RegState::Kill)
- .addGlobalAddress(GV, 0, AArch64II::MO_G3).addImm(48);
+ .addGlobalAddress(GV, 0, AArch64II::MO_G3)
+ .addImm(48);
BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
.addReg(Reg, RegState::Kill)
.addImm(0)
} else
return false;
- // Get the scaling factor for the instruction and set the width for the
+ // Get the scaling factor for the instruction and set the width for the
// instruction.
unsigned Scale = 0;
int64_t Dummy1, Dummy2;
return true;
}
-MachineOperand&
+MachineOperand &
AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const {
assert(LdSt.mayLoadOrStore() && "Expected a memory operation.");
- MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands()-1);
+ MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands() - 1);
assert(OfsOp.isImm() && "Offset operand wasn't immediate.");
return OfsOp;
}
unsigned &Width, int64_t &MinOffset,
int64_t &MaxOffset) const {
switch (Opcode) {
- // Not a memory operation or something we want to handle.
+ // Not a memory operation or something we want to handle.
default:
Scale = Width = 0;
MinOffset = MaxOffset = 0;
return ((DestReg - SrcReg) & 0x1f) < NumRegs;
}
-void AArch64InstrInfo::copyPhysRegTuple(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL,
- unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode,
- ArrayRef<unsigned> Indices) const {
- assert(Subtarget.hasNEON() &&
- "Unexpected register copy without NEON");
+void AArch64InstrInfo::copyPhysRegTuple(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator I,
+ const DebugLoc &DL, unsigned DestReg,
+ unsigned SrcReg, bool KillSrc,
+ unsigned Opcode,
+ ArrayRef<unsigned> Indices) const {
+ assert(Subtarget.hasNEON() && "Unexpected register copy without NEON");
const TargetRegisterInfo *TRI = &getRegisterInfo();
uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
}
} else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroing()) {
- BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg).addImm(0).addImm(
- AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
+ BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
+ .addImm(0)
+ .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
} else {
if (Subtarget.hasZeroCycleRegMove()) {
// Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
.addImm(0)
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
} else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroing()) {
- BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg).addImm(0).addImm(
- AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
+ BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
+ .addImm(0)
+ .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
} else {
// Otherwise, expand to ORR XZR.
BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
// Copy a DDDD register quad by copying the individual sub-registers.
if (AArch64::DDDDRegClass.contains(DestReg) &&
AArch64::DDDDRegClass.contains(SrcReg)) {
- static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
- AArch64::dsub2, AArch64::dsub3 };
+ static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1,
+ AArch64::dsub2, AArch64::dsub3};
copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
Indices);
return;
// Copy a DDD register triple by copying the individual sub-registers.
if (AArch64::DDDRegClass.contains(DestReg) &&
AArch64::DDDRegClass.contains(SrcReg)) {
- static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1,
- AArch64::dsub2 };
+ static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1,
+ AArch64::dsub2};
copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
Indices);
return;
// Copy a DD register pair by copying the individual sub-registers.
if (AArch64::DDRegClass.contains(DestReg) &&
AArch64::DDRegClass.contains(SrcReg)) {
- static const unsigned Indices[] = { AArch64::dsub0, AArch64::dsub1 };
+ static const unsigned Indices[] = {AArch64::dsub0, AArch64::dsub1};
copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8,
Indices);
return;
// Copy a QQQQ register quad by copying the individual sub-registers.
if (AArch64::QQQQRegClass.contains(DestReg) &&
AArch64::QQQQRegClass.contains(SrcReg)) {
- static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
- AArch64::qsub2, AArch64::qsub3 };
+ static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
+ AArch64::qsub2, AArch64::qsub3};
copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
Indices);
return;
// Copy a QQQ register triple by copying the individual sub-registers.
if (AArch64::QQQRegClass.contains(DestReg) &&
AArch64::QQQRegClass.contains(SrcReg)) {
- static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1,
- AArch64::qsub2 };
+ static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1,
+ AArch64::qsub2};
copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
Indices);
return;
// Copy a QQ register pair by copying the individual sub-registers.
if (AArch64::QQRegClass.contains(DestReg) &&
AArch64::QQRegClass.contains(SrcReg)) {
- static const unsigned Indices[] = { AArch64::qsub0, AArch64::qsub1 };
+ static const unsigned Indices[] = {AArch64::qsub0, AArch64::qsub1};
copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8,
Indices);
return;
if (AArch64::FPR128RegClass.contains(DestReg) &&
AArch64::FPR128RegClass.contains(SrcReg)) {
- if(Subtarget.hasNEON()) {
+ if (Subtarget.hasNEON()) {
BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
.addReg(SrcReg)
.addReg(SrcReg, getKillRegState(KillSrc));
} else {
BuildMI(MBB, I, DL, get(AArch64::STRQpre))
- .addReg(AArch64::SP, RegState::Define)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addReg(AArch64::SP)
- .addImm(-16);
+ .addReg(AArch64::SP, RegState::Define)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(AArch64::SP)
+ .addImm(-16);
BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
- .addReg(AArch64::SP, RegState::Define)
- .addReg(DestReg, RegState::Define)
- .addReg(AArch64::SP)
- .addImm(16);
+ .addReg(AArch64::SP, RegState::Define)
+ .addReg(DestReg, RegState::Define)
+ .addReg(AArch64::SP)
+ .addImm(16);
}
return;
}
if (AArch64::FPR64RegClass.contains(DestReg) &&
AArch64::FPR64RegClass.contains(SrcReg)) {
- if(Subtarget.hasNEON()) {
+ if (Subtarget.hasNEON()) {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
&AArch64::FPR128RegClass);
SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
if (AArch64::FPR32RegClass.contains(DestReg) &&
AArch64::FPR32RegClass.contains(SrcReg)) {
- if(Subtarget.hasNEON()) {
+ if (Subtarget.hasNEON()) {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
&AArch64::FPR128RegClass);
SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
if (AArch64::FPR16RegClass.contains(DestReg) &&
AArch64::FPR16RegClass.contains(SrcReg)) {
- if(Subtarget.hasNEON()) {
+ if (Subtarget.hasNEON()) {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
&AArch64::FPR128RegClass);
SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
if (AArch64::FPR8RegClass.contains(DestReg) &&
AArch64::FPR8RegClass.contains(SrcReg)) {
- if(Subtarget.hasNEON()) {
+ if (Subtarget.hasNEON()) {
DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
&AArch64::FPR128RegClass);
SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
if (DestReg == AArch64::NZCV) {
assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
BuildMI(MBB, I, DL, get(AArch64::MSR))
- .addImm(AArch64SysReg::NZCV)
- .addReg(SrcReg, getKillRegState(KillSrc))
- .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
+ .addImm(AArch64SysReg::NZCV)
+ .addReg(SrcReg, getKillRegState(KillSrc))
+ .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
return;
}
if (SrcReg == AArch64::NZCV) {
assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
- .addImm(AArch64SysReg::NZCV)
- .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
+ .addImm(AArch64SysReg::NZCV)
+ .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
return;
}
if (AArch64::FPR128RegClass.hasSubClassEq(RC))
Opc = AArch64::STRQui;
else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register store without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Twov1d;
Offset = false;
}
break;
case 24:
if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register store without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Threev1d;
Offset = false;
}
break;
case 32:
if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register store without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Fourv1d;
Offset = false;
} else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register store without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Twov2d;
Offset = false;
}
break;
case 48:
if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register store without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Threev2d;
Offset = false;
}
break;
case 64:
if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register store without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
Opc = AArch64::ST1Fourv2d;
Offset = false;
}
assert(Opc && "Unknown register class");
const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
- .addReg(SrcReg, getKillRegState(isKill))
- .addFrameIndex(FI);
+ .addReg(SrcReg, getKillRegState(isKill))
+ .addFrameIndex(FI);
if (Offset)
MI.addImm(0);
if (AArch64::FPR128RegClass.hasSubClassEq(RC))
Opc = AArch64::LDRQui;
else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register load without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Twov1d;
Offset = false;
}
break;
case 24:
if (AArch64::DDDRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register load without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Threev1d;
Offset = false;
}
break;
case 32:
if (AArch64::DDDDRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register load without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Fourv1d;
Offset = false;
} else if (AArch64::QQRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register load without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Twov2d;
Offset = false;
}
break;
case 48:
if (AArch64::QQQRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register load without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Threev2d;
Offset = false;
}
break;
case 64:
if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
- assert(Subtarget.hasNEON() &&
- "Unexpected register load without NEON");
+ assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
Opc = AArch64::LD1Fourv2d;
Offset = false;
}
assert(Opc && "Unknown register class");
const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
- .addReg(DestReg, getDefRegState(true))
- .addFrameIndex(FI);
+ .addReg(DestReg, getDefRegState(true))
+ .addFrameIndex(FI);
if (Offset)
MI.addImm(0);
MI.addMemOperand(MMO);
if (DstMO.getSubReg() == 0 && SrcMO.getSubReg() == 0) {
assert(TRI.getRegSizeInBits(*getRegClass(DstReg)) ==
- TRI.getRegSizeInBits(*getRegClass(SrcReg)) &&
+ TRI.getRegSizeInBits(*getRegClass(SrcReg)) &&
"Mismatched register size in non subreg COPY");
if (IsSpill)
storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
}
// AArch64 supports MachineCombiner.
-bool AArch64InstrInfo::useMachineCombiner() const {
-
- return true;
-}
+bool AArch64InstrInfo::useMachineCombiner() const { return true; }
// True when Opc sets flag
static bool isCombineInstrSettingFlag(unsigned Opc) {
// 1. Other data types (integer, vectors)
// 2. Other math / logic operations (xor, or)
// 3. Other forms of the same operation (intrinsics and other variants)
-bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
+bool AArch64InstrInfo::isAssociativeAndCommutative(
+ const MachineInstr &Inst) const {
switch (Inst.getOpcode()) {
case AArch64::FADDDrr:
case AArch64::FADDSrr:
/// Return true when a code sequence can improve throughput. It
/// should be called only for instructions in loops.
/// \param Pattern - combiner pattern
-bool
-AArch64InstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
+bool AArch64InstrInfo::isThroughputPattern(
+ MachineCombinerPattern Pattern) const {
switch (Pattern) {
default:
break;
static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
const TargetInstrInfo *TII, MachineInstr &Root,
SmallVectorImpl<MachineInstr *> &InsInstrs,
- unsigned IdxMulOpd, unsigned MaddOpc,
- unsigned VR, const TargetRegisterClass *RC) {
+ unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR,
+ const TargetRegisterClass *RC) {
assert(IdxMulOpd == 1 || IdxMulOpd == 2);
MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
if (TargetRegisterInfo::isVirtualRegister(VR))
MRI.constrainRegClass(VR, RC);
- MachineInstrBuilder MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc),
- ResultReg)
- .addReg(SrcReg0, getKillRegState(Src0IsKill))
- .addReg(SrcReg1, getKillRegState(Src1IsKill))
- .addReg(VR);
+ MachineInstrBuilder MIB =
+ BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
+ .addReg(SrcReg0, getKillRegState(Src0IsKill))
+ .addReg(SrcReg1, getKillRegState(Src1IsKill))
+ .addReg(VR);
// Insert the MADD
InsInstrs.push_back(MIB);
return MUL;
using namespace AArch64II;
static const std::pair<unsigned, const char *> TargetFlags[] = {
- {MO_PAGE, "aarch64-page"},
- {MO_PAGEOFF, "aarch64-pageoff"},
- {MO_G3, "aarch64-g3"},
- {MO_G2, "aarch64-g2"},
- {MO_G1, "aarch64-g1"},
- {MO_G0, "aarch64-g0"},
+ {MO_PAGE, "aarch64-page"}, {MO_PAGEOFF, "aarch64-pageoff"},
+ {MO_G3, "aarch64-g3"}, {MO_G2, "aarch64-g2"},
+ {MO_G1, "aarch64-g1"}, {MO_G0, "aarch64-g0"},
{MO_HI12, "aarch64-hi12"}};
return makeArrayRef(TargetFlags);
}
using namespace AArch64II;
static const std::pair<unsigned, const char *> TargetFlags[] = {
- {MO_GOT, "aarch64-got"},
- {MO_NC, "aarch64-nc"},
- {MO_TLS, "aarch64-tls"}};
+ {MO_GOT, "aarch64-got"}, {MO_NC, "aarch64-nc"}, {MO_TLS, "aarch64-tls"}};
return makeArrayRef(TargetFlags);
}
return makeArrayRef(TargetFlags);
}
-unsigned AArch64InstrInfo::getOutliningBenefit(size_t SequenceSize,
- size_t Occurrences,
- bool CanBeTailCall) const {
- unsigned NotOutlinedSize = SequenceSize * Occurrences;
- unsigned OutlinedSize;
-
- // Is this candidate something we can outline as a tail call?
- if (CanBeTailCall) {
- // If yes, then we just outline the sequence and replace each of its
- // occurrences with a branch instruction.
- OutlinedSize = SequenceSize + Occurrences;
- } else {
- // If no, then we outline the sequence (SequenceSize), add a return (+1),
- // and replace each occurrence with a save/restore to LR and a call
- // (3 * Occurrences)
- OutlinedSize = (SequenceSize + 1) + (3 * Occurrences);
- }
+size_t AArch64InstrInfo::getOutliningCallOverhead(
+ MachineBasicBlock::iterator &StartIt,
+ MachineBasicBlock::iterator &EndIt) const {
+ // Is this a tail-call?
+ if (EndIt->isTerminator())
+ return 1; // Yes, so we don't need to save/restore LR.
- // Return the number of instructions saved by outlining this sequence.
- return NotOutlinedSize > OutlinedSize ? NotOutlinedSize - OutlinedSize : 0;
+ // No, so save + restore LR.
+ return 3;
+}
+
+size_t AArch64InstrInfo::getOutliningFrameOverhead(
+ MachineBasicBlock::iterator &StartIt,
+ MachineBasicBlock::iterator &EndIt) const {
+
+ // Is this a tail-call?
+ if (EndIt->isTerminator())
+ return 0; // Yes, so we already have a return.
+
+ // No, so we have to add a return to the end.
+ return 1;
}
bool AArch64InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF) const {
// Is this the end of a function?
if (MI.getParent()->succ_empty())
- return MachineOutlinerInstrType::Legal;
+ return MachineOutlinerInstrType::Legal;
// It's not, so don't outline it.
return MachineOutlinerInstrType::Illegal;
// Don't outline anything that uses the link register.
if (MI.modifiesRegister(AArch64::LR, &RI) ||
MI.readsRegister(AArch64::LR, &RI))
- return MachineOutlinerInstrType::Illegal;
+ return MachineOutlinerInstrType::Illegal;
// Does this use the stack?
if (MI.modifiesRegister(AArch64::SP, &RI) ||
// Is it a memory operation?
if (MI.mayLoadOrStore()) {
- unsigned Base; // Filled with the base regiser of MI.
+ unsigned Base; // Filled with the base regiser of MI.
int64_t Offset; // Filled with the offset of MI.
unsigned DummyWidth;
// Does it allow us to offset the base register and is the base SP?
if (!getMemOpBaseRegImmOfsWidth(MI, Base, Offset, DummyWidth, &RI) ||
- Base != AArch64::SP)
+ Base != AArch64::SP)
return MachineOutlinerInstrType::Illegal;
// Find the minimum/maximum offset for this instruction and check if
// This is tricky to test with IR tests, but when the outliner is moved
// to a MIR test, it really ought to be checked.
if (Offset + 16 < MinOffset || Offset + 16 > MaxOffset)
- return MachineOutlinerInstrType::Illegal;
+ return MachineOutlinerInstrType::Illegal;
// It's in range, so we can outline it.
return MachineOutlinerInstrType::Legal;
// We've pushed the return address to the stack, so add 16 to the offset.
// This is safe, since we already checked if it would overflow when we
// checked if this instruction was legal to outline.
- int64_t NewImm = (Offset + 16)/Scale;
+ int64_t NewImm = (Offset + 16) / Scale;
StackOffsetOperand.setImm(NewImm);
}
}
return It;
}
-
projects / llvm / commitdiff