]> granicus.if.org Git - llvm/commitdiff
[SelectionDAG] Const-correct the DemandedMask argument to one of the overloads of...
authorCraig Topper <craig.topper@intel.com>
Thu, 12 Oct 2017 23:46:05 +0000 (23:46 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 12 Oct 2017 23:46:05 +0000 (23:46 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315641 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetLowering.h
lib/CodeGen/SelectionDAG/TargetLowering.cpp

index 0d24c30c8ef0c1c2d36da4e8d4e4712b33c31919..5bc26cc35c5300a7b893882e026069d0f1769337 100644 (file)
@@ -2654,7 +2654,7 @@ public:
                             bool AssumeSingleUse = false) const;
 
   /// Helper wrapper around SimplifyDemandedBits
-  bool SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
+  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                             DAGCombinerInfo &DCI) const;
 
   /// Determine which of the bits specified in Mask are known to be either zero
index 31f8f3b49dcd144a98b9bc1c3b6b14d77b99cc15..7570b06a5de4ec92a8a79932085d34e550c160b2 100644 (file)
@@ -479,7 +479,7 @@ TargetLowering::SimplifyDemandedBits(SDNode *User, unsigned OpIdx,
   return true;
 }
 
-bool TargetLowering::SimplifyDemandedBits(SDValue Op, APInt &DemandedMask,
+bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                                           DAGCombinerInfo &DCI) const {
 
   SelectionDAG &DAG = DCI.DAG;