[Hexagon] Remove registers coalesced in expand-condsets from live intervals

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285846 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 15ffa1c4c66139fdce56582b630172f0fbfcd803..edbd61d5eb40cbebe1a1341eb6b353e18195db1e 100644 (file)
--- a/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -1078,6 +1078,8 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
   LiveInterval &L2 = LIS->getInterval(R2.Reg);
   if (L2.empty())
     return false;
+  if (L1.hasSubRanges() || L2.hasSubRanges())
+    return false;
   bool Overlap = L1.overlaps(L2);
 
   DEBUG(dbgs() << "compatible registers: ("
@@ -1113,6 +1115,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
   }
   while (L2.begin() != L2.end())
     L2.removeSegment(*L2.begin());
+  LIS->removeInterval(R2.Reg);
 
   updateKillFlags(R1.Reg);
   DEBUG(dbgs() << "coalesced: " << L1 << "\n");

diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
new file mode 100644 (file)
index 0000000..983035e
--- /dev/null
+++ b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
@@ -0,0 +1,49 @@
+# RUN: llc -march=hexagon -run-pass expand-condsets -o - 2>&1 %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s
+# REQUIRES: asserts
+
+# Check that coalesced registers are removed from live intervals.
+#
+# Check that vreg3 is coalesced into vreg4, and that after coalescing
+# it is no longer in live intervals.
+
+# CHECK-LABEL: After expand-condsets
+# CHECK: INTERVALS
+# CHECK-NOT: vreg3
+# CHECK: MACHINEINSTRS
+
+
+--- |
+  define void @fred() { ret void }
+
+...
+---
+
+name: fred
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: intregs }
+  - { id: 1, class: intregs }
+  - { id: 2, class: predregs }
+  - { id: 3, class: intregs }
+  - { id: 4, class: intregs }
+liveins:
+  - { reg: '%r0', virtual-reg: '%0' }
+  - { reg: '%r1', virtual-reg: '%1' }
+  - { reg: '%p0', virtual-reg: '%2' }
+
+body: |
+  bb.0:
+    liveins: %r0, %r1, %p0
+        %0 = COPY %r0
+        %0 = COPY %r0  ; Force isSSA = false.
+        %1 = COPY %r1
+        %2 = COPY %p0
+        ; Check that %3 was coalesced into %4.
+        ; CHECK: %4 = A2_abs %1
+        ; CHECK: %4 = A2_tfrt killed %2, killed %0, implicit %4
+        %3 = A2_abs %1
+        %4 = C2_mux %2, %0, %3
+        %r0 = COPY %4
+        J2_jumpr %r31, implicit %r0, implicit-def %pc
+...
+