[ARM] GlobalISel: Support G_ICMP for s8 and s16

Widen to s32 (like all other binary ops).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305683 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index 2892b721902fbca2386dd30e4915940fdb034a02..5873c7fb38729029263f86f2c4bbe28522c0d238 100644 (file)
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -87,6 +87,8 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
   setAction({G_CONSTANT, s32}, Legal);
 
   setAction({G_ICMP, s1}, Legal);
+  for (auto Ty : {s8, s16})
+    setAction({G_ICMP, 1, Ty}, WidenScalar);
   for (auto Ty : {s32, p0})
     setAction({G_ICMP, 1, Ty}, Legal);
 

diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/test/CodeGen/ARM/GlobalISel/arm-isel.ll
index 4d1e1fcc918787e238a7ef1ea4c4475cf137ace1..76fb39ecea013ae12418e97e22595a5e0fa418a8 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-isel.ll
+++ b/test/CodeGen/ARM/GlobalISel/arm-isel.ll
@@ -385,3 +385,18 @@ entry:
   %r = zext i1 %v to i32
   ret i32 %r
 }
+
+define arm_aapcscc i32 @test_cmp_i16_slt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_cmp_i16_slt:
+; CHECK-DAG: sxth r0, r0
+; CHECK-DAG: sxth r1, r1
+; CHECK-DAG: mov [[V:r[0-9]+]], #0
+; CHECK: cmp r0, r1
+; CHECK: movlt [[V]], #1
+; CHECK: and r0, [[V]], #1
+; CHECK: bx lr
+entry:
+  %v = icmp slt i16 %a, %b
+  %r = zext i1 %v to i32
+  ret i32 %r
+}

diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 7a1902e77d3ca4ca1354d33ff7853db4e4ec5faf..2def31eb1592935f4d98e8a7bb07d23bba30cd7d 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -35,7 +35,9 @@
 
   define void @test_constants() { ret void }
 
-  define void @test_icmp_eq_s32() { ret void }
+  define void @test_icmp_s8() { ret void }
+  define void @test_icmp_s16() { ret void }
+  define void @test_icmp_s32() { ret void }
 
   define void @test_fadd_s32() #0 { ret void }
   define void @test_fadd_s64() #0 { ret void }
@@ -693,8 +695,62 @@ body:             |
     BX_RET 14, _, implicit %r0
 ...
 ---
-name:            test_icmp_eq_s32
-# CHECK-LABEL: name: test_icmp_eq_s32
+name:            test_icmp_s8
+# CHECK-LABEL: name: test_icmp_s8
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s8) = COPY %r0
+    %1(s8) = COPY %r1
+    %2(s1) = G_ICMP intpred(ne), %0(s8), %1
+    ; G_ICMP with s8 should widen
+    ; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}(s1) = G_ICMP intpred(ne), {{%[0-9]+}}(s8), {{%[0-9]+}}
+    %3(s32) = G_ZEXT %2(s1)
+    %r0 = COPY %3(s32)
+    BX_RET 14, _, implicit %r0
+...
+---
+name:            test_icmp_s16
+# CHECK-LABEL: name: test_icmp_s16
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0:
+    liveins: %r0, %r1
+
+    %0(s16) = COPY %r0
+    %1(s16) = COPY %r1
+    %2(s1) = G_ICMP intpred(slt), %0(s16), %1
+    ; G_ICMP with s16 should widen
+    ; CHECK: {{%[0-9]+}}(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s32), {{%[0-9]+}}
+    ; CHECK-NOT: {{%[0-9]+}}(s1) = G_ICMP intpred(slt), {{%[0-9]+}}(s16), {{%[0-9]+}}
+    %3(s32) = G_ZEXT %2(s1)
+    %r0 = COPY %3(s32)
+    BX_RET 14, _, implicit %r0
+...
+---
+name:            test_icmp_s32
+# CHECK-LABEL: name: test_icmp_s32
 legalized:       false
 # CHECK: legalized: true
 regBankSelected: false