These options specify 64-bit FP registers and 32-bit FP registers respectively.
When using -mfp32, the FPU has 16x double-precision registers overlapping with
the 32x single-precision registers (each double-precision register overlaps
two single-precision registers).
When using -mfp64, the FPU has 32x double-precision registers overlapping with
the 32x single-precision registers (each double-precision register overlaps
with one single-precision register and has an additional 32-bits).
MSA requires -mfp64.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@192899
91177308-0d34-0410-b5e6-
96231b3b80d8
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group<m_Group>,
HelpText<"Disable MSA ASE (MIPS only)">;
+def mfp64 : Flag<["-"], "mfp64">, Group<m_Group>,
+ HelpText<"Use 64-bit floating point registers (MIPS only)">;
+def mfp32 : Flag<["-"], "mfp32">, Group<m_Group>,
+ HelpText<"Use 32-bit floating point registers (MIPS only)">;
def mnan_EQ : Joined<["-"], "mnan=">, Group<m_Group>;
def mips32 : Flag<["-"], "mips32">,
Alias<march_EQ>, AliasArgs<["mips32"]>,
"dspr2");
AddTargetFeature(Args, Features, options::OPT_mmsa, options::OPT_mno_msa,
"msa");
+ AddTargetFeature(Args, Features, options::OPT_mfp64, options::OPT_mfp32,
+ "fp64");
}
void Clang::AddMIPSTargetArgs(const ArgList &Args,
// RUN: | FileCheck --check-prefix=CHECK-NOMMSA %s
// CHECK-NOMMSA: "-target-feature" "-msa"
//
+// -mfp64
+// RUN: %clang -target mips-linux-gnu -### -c %s \
+// RUN: -mfp32 -mfp64 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-MFP64 %s
+// CHECK-MFP64: "-target-feature" "+fp64"
+//
+// -mfp32
+// RUN: %clang -target mips-linux-gnu -### -c %s \
+// RUN: -mfp64 -mfp32 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-NOMFP64 %s
+// CHECK-NOMFP64: "-target-feature" "-fp64"
+//
// -mxgot
// RUN: %clang -target mips-linux-gnu -### -c %s \
// RUN: -mno-xgot -mxgot 2>&1 \