[Hexagon] Keep all phi nodes when building DFG in addr-mode-opt

The dead phis are needed for finding correct would-be reaching defs
in register propagation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306690 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index 27b40f134b1f41c8ea8f3b958aee01e86e66ca60..a331c978f59d2e0f17f152db1ef9303da45c4fe5 100644 (file)
--- a/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -535,9 +535,9 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
         !MI->getOperand(1).isGlobal())
       continue;
 
-    DEBUG(dbgs() << "[Analyzing A2_tfrsi]: " << *MI << "\n");
-    DEBUG(dbgs() << "\t[InstrNode]: " << Print<NodeAddr<InstrNode *>>(IA, *DFG)
-                 << "\n");
+    DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode()) << "]: "
+                 << *MI << "\n\t[InstrNode]: "
+                 << Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n');
 
     NodeList UNodeList;
     getAllRealUses(SA, UNodeList);
@@ -605,7 +605,9 @@ bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
   const TargetOperandInfo TOI(*HII);
 
   DataFlowGraph G(MF, *HII, TRI, *MDT, MDF, TOI);
-  G.build();
+  // Need to keep dead phis because we can propagate uses of registers into
+  // nodes dominated by those would-be phis.
+  G.build(BuildOptions::KeepDeadPhis);
   DFG = &G;
 
   Liveness L(MRI, *DFG);

diff --git a/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir b/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir
new file mode 100644 (file)
index 0000000..b77a7b1
--- /dev/null
+++ b/test/CodeGen/Hexagon/addrmode-keepdeadphis.mir
@@ -0,0 +1,30 @@
+# RUN: llc -march=hexagon -run-pass amode-opt %s -o - | FileCheck %s
+
+# Check that the addasl is not propagated into the addressing mode.
+# CHECK-NOT: L4_loadri_ur
+
+--- |
+  @g = global i32 zeroinitializer
+  define void @fred() { ret void }
+...
+
+---
+name: fred
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: %p0
+    %r0 = A2_tfrsi @g
+    %r1 = A2_tfrsi 1
+    %r2 = S2_addasl_rrri %r0, %r1, 1
+    J2_jumpt %p0, %bb.2, implicit-def %pc
+
+  bb.1:
+    liveins: %r0, %r2
+    %r1 = A2_tfrsi 2
+
+  bb.2:
+    liveins: %r0, %r2
+    %r3 = L2_loadri_io %r2, 0
+...