libhb: Skylake microarchitecture detection, RB 859

diff --git a/libhb/ports.c b/libhb/ports.c
index e93fdb100416f30f8b07840f7178a108104ec6a9..23be576b9ca988eed9e3bef3b67b9ae33d1825c9 100644 (file)
--- a/libhb/ports.c
+++ b/libhb/ports.c
@@ -269,6 +269,8 @@ const char* hb_get_cpu_platform_name()
             return "Intel microarchitecture Haswell";
         case HB_CPU_PLATFORM_INTEL_BDW:
             return "Intel microarchitecture Broadwell";
+        case HB_CPU_PLATFORM_INTEL_SKL:
+            return "Intel microarchitecture Skylake";
         case HB_CPU_PLATFORM_INTEL_CHT:
             return "Intel microarchitecture Airmont";
 
@@ -354,6 +356,10 @@ static void init_cpu_info()
                     case 0x4C:
                         hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_CHT;
                         break;
+                    case 0x4E:
+                    case 0x5E:
+                        hb_cpu_info.platform = HB_CPU_PLATFORM_INTEL_SKL;
+                        break;
                     default:
                         break;
                 }

diff --git a/libhb/ports.h b/libhb/ports.h
index 5e039809e64cc4c5c3afb72764d0f84709718cb9..d1649304306f918d042fdb1d596567ccd440ad2e 100644 (file)
--- a/libhb/ports.h
+++ b/libhb/ports.h
@@ -39,6 +39,7 @@ enum hb_cpu_platform
     HB_CPU_PLATFORM_INTEL_HSW,
     HB_CPU_PLATFORM_INTEL_BDW,
     HB_CPU_PLATFORM_INTEL_CHT,
+    HB_CPU_PLATFORM_INTEL_SKL,
 };
 int         hb_get_cpu_count();
 int         hb_get_cpu_platform();

diff --git a/libhb/qsv_common.c b/libhb/qsv_common.c
index 60d371f825dcdec31ef15e3ff73998497f274a75..12f4d5e7b1204549c19bd7f2c6a72b721e1a4ceb 100644 (file)
--- a/libhb/qsv_common.c
+++ b/libhb/qsv_common.c
@@ -108,6 +108,8 @@ enum
     QSV_G2, // Ivy Bridge or equivalent
     QSV_G3, // Haswell or equivalent
     QSV_G4, // Broadwell or equivalent
+    QSV_G5, // Skylake or equivalent
+    QSV_FU, // always last (future processors)
 };
 static int qsv_hardware_generation(int cpu_platform)
 {
@@ -124,8 +126,11 @@ static int qsv_hardware_generation(int cpu_platform)
         case HB_CPU_PLATFORM_INTEL_HSW:
             return QSV_G3;
         case HB_CPU_PLATFORM_INTEL_BDW:
-        default:
             return QSV_G4;
+        case HB_CPU_PLATFORM_INTEL_SKL:
+            return QSV_G5;
+        default:
+            return QSV_FU;
     }
 }