[AArch64][SVE] Asm: Predicated integer reductions.

This patch adds support for various integer reduction operations:

  SADDV    signed add reduction to scalar
  UADDV    unsigned add reduction to scalar

  SMAXV    signed maximum reduction to scalar
  SMINV    signed minimum reduction to scalar
  UMAXV    unsigned maximum reduction to scalar
  UMINV    unsigned minimum reduction to scalar

  ANDV     logical AND reduction to scalar
  ORV      logical OR reduction to scalar
  EORV     logical EOR reduction to scalar

The reduction is predicated, e.g.
  smaxv s0, p0, z1.s

performs a signed maximum reduction on active elements in z1,
and stores the (signed max value) result in s0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338126 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 12a669a0d05e9e6a0dffe0baf58bfd9d90f9ad7f..16e6ddda6398ed5dcfe55cbd6ecd48d25d1ad9f9 100644 (file)
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -53,6 +53,17 @@ let Predicates = [HasSVE] in {
   defm MLA_ZPmZZ : sve_int_mlas_vvv_pred<0b0, "mla">;
   defm MLS_ZPmZZ : sve_int_mlas_vvv_pred<0b1, "mls">;
 
+  // SVE predicated integer reductions.
+  defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv">;
+  defm UADDV_VPZ : sve_int_reduce_0_uaddv<0b001, "uaddv">;
+  defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv">;
+  defm UMAXV_VPZ : sve_int_reduce_1<0b001, "umaxv">;
+  defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv">;
+  defm UMINV_VPZ : sve_int_reduce_1<0b011, "uminv">;
+  defm ORV_VPZ   : sve_int_reduce_2<0b000, "orv">;
+  defm EORV_VPZ  : sve_int_reduce_2<0b001, "eorv">;
+  defm ANDV_VPZ  : sve_int_reduce_2<0b010, "andv">;
+
   defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
   defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
   defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;

diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index 92ab1e24d76fc3e10289d2ec5082c390162a287e..17b3f6041279c19c56bb10bfcdadd20b8929a41b 100644 (file)
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -4066,3 +4066,54 @@ class sve_int_bin_cons_misc_0_c<bits<8> opc, string asm, ZPRRegOp zprty>
   let Inst{9-5}   = Zn;
   let Inst{4-0}   = Zd;
 }
+
+//===----------------------------------------------------------------------===//
+// SVE Integer Reduction Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
+                     ZPRRegOp zprty, RegisterClass regtype>
+: I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+  asm, "\t$Vd, $Pg, $Zn",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Vd;
+  bits<5> Zn;
+  let Inst{31-24} = 0b00000100;
+  let Inst{23-22} = sz8_32;
+  let Inst{21}    = 0b0;
+  let Inst{20-19} = fmt;
+  let Inst{18-16} = opc;
+  let Inst{15-13} = 0b001;
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Vd;
+}
+
+multiclass sve_int_reduce_0_saddv<bits<3> opc, string asm> {
+  def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
+  def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
+  def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
+}
+
+multiclass sve_int_reduce_0_uaddv<bits<3> opc, string asm> {
+  def _B : sve_int_reduce<0b00, 0b00, opc, asm, ZPR8, FPR64>;
+  def _H : sve_int_reduce<0b01, 0b00, opc, asm, ZPR16, FPR64>;
+  def _S : sve_int_reduce<0b10, 0b00, opc, asm, ZPR32, FPR64>;
+  def _D : sve_int_reduce<0b11, 0b00, opc, asm, ZPR64, FPR64>;
+}
+
+multiclass sve_int_reduce_1<bits<3> opc, string asm> {
+  def _B : sve_int_reduce<0b00, 0b01, opc, asm, ZPR8, FPR8>;
+  def _H : sve_int_reduce<0b01, 0b01, opc, asm, ZPR16, FPR16>;
+  def _S : sve_int_reduce<0b10, 0b01, opc, asm, ZPR32, FPR32>;
+  def _D : sve_int_reduce<0b11, 0b01, opc, asm, ZPR64, FPR64>;
+}
+
+multiclass sve_int_reduce_2<bits<3> opc, string asm> {
+  def _B : sve_int_reduce<0b00, 0b11, opc, asm, ZPR8, FPR8>;
+  def _H : sve_int_reduce<0b01, 0b11, opc, asm, ZPR16, FPR16>;
+  def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>;
+  def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>;
+}

diff --git a/test/MC/AArch64/SVE/andv-diagnostics.s b/test/MC/AArch64/SVE/andv-diagnostics.s
new file mode 100644 (file)
index 0000000..60a42f8
--- /dev/null
+++ b/test/MC/AArch64/SVE/andv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+andv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: andv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+andv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: andv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+andv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: andv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+andv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: andv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+andv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: andv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/andv.s b/test/MC/AArch64/SVE/andv.s
new file mode 100644 (file)
index 0000000..da0ec1f
--- /dev/null
+++ b/test/MC/AArch64/SVE/andv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+andv b0, p7, z31.b
+// CHECK-INST: andv    b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x1a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 1a 04 <unknown>
+
+andv h0, p7, z31.h
+// CHECK-INST: andv    h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x5a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 5a 04 <unknown>
+
+andv s0, p7, z31.s
+// CHECK-INST: andv    s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x9a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 9a 04 <unknown>
+
+andv d0, p7, z31.d
+// CHECK-INST: andv    d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xda,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f da 04 <unknown>

diff --git a/test/MC/AArch64/SVE/eorv-diagnostics.s b/test/MC/AArch64/SVE/eorv-diagnostics.s
new file mode 100644 (file)
index 0000000..c182615
--- /dev/null
+++ b/test/MC/AArch64/SVE/eorv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+eorv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: eorv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eorv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: eorv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eorv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: eorv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eorv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: eorv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+eorv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: eorv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/eorv.s b/test/MC/AArch64/SVE/eorv.s
new file mode 100644 (file)
index 0000000..3b65447
--- /dev/null
+++ b/test/MC/AArch64/SVE/eorv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+eorv b0, p7, z31.b
+// CHECK-INST: eorv    b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x19,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 19 04 <unknown>
+
+eorv h0, p7, z31.h
+// CHECK-INST: eorv    h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x59,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 59 04 <unknown>
+
+eorv s0, p7, z31.s
+// CHECK-INST: eorv    s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x99,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 99 04 <unknown>
+
+eorv d0, p7, z31.d
+// CHECK-INST: eorv    d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xd9,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f d9 04 <unknown>

diff --git a/test/MC/AArch64/SVE/orv-diagnostics.s b/test/MC/AArch64/SVE/orv-diagnostics.s
new file mode 100644 (file)
index 0000000..8a64ad8
--- /dev/null
+++ b/test/MC/AArch64/SVE/orv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+orv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: orv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: orv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: orv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: orv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+orv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: orv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/orv.s b/test/MC/AArch64/SVE/orv.s
new file mode 100644 (file)
index 0000000..8ae0371
--- /dev/null
+++ b/test/MC/AArch64/SVE/orv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+orv b0, p7, z31.b
+// CHECK-INST: orv     b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x18,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 18 04 <unknown>
+
+orv h0, p7, z31.h
+// CHECK-INST: orv     h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x58,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 58 04 <unknown>
+
+orv s0, p7, z31.s
+// CHECK-INST: orv     s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x98,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 98 04 <unknown>
+
+orv d0, p7, z31.d
+// CHECK-INST: orv     d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xd8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f d8 04 <unknown>

diff --git a/test/MC/AArch64/SVE/saddv-diagnostics.s b/test/MC/AArch64/SVE/saddv-diagnostics.s
new file mode 100644 (file)
index 0000000..e387e07
--- /dev/null
+++ b/test/MC/AArch64/SVE/saddv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+saddv s0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: saddv s0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+saddv s0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: saddv s0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+saddv s0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: saddv s0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+saddv d0, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: saddv d0, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+saddv d0, p8, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: saddv d0, p8, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/saddv.s b/test/MC/AArch64/SVE/saddv.s
new file mode 100644 (file)
index 0000000..28a64d7
--- /dev/null
+++ b/test/MC/AArch64/SVE/saddv.s
@@ -0,0 +1,26 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+saddv d0, p7, z31.b
+// CHECK-INST: saddv   d0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x00,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 00 04 <unknown>
+
+saddv d0, p7, z31.h
+// CHECK-INST: saddv   d0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x40,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 40 04 <unknown>
+
+saddv d0, p7, z31.s
+// CHECK-INST: saddv   d0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x80,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 80 04 <unknown>

diff --git a/test/MC/AArch64/SVE/smaxv-diagnostics.s b/test/MC/AArch64/SVE/smaxv-diagnostics.s
new file mode 100644 (file)
index 0000000..6293602
--- /dev/null
+++ b/test/MC/AArch64/SVE/smaxv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+smaxv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smaxv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smaxv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smaxv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smaxv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: smaxv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smaxv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smaxv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+smaxv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: smaxv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/smaxv.s b/test/MC/AArch64/SVE/smaxv.s
new file mode 100644 (file)
index 0000000..bb0b627
--- /dev/null
+++ b/test/MC/AArch64/SVE/smaxv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+smaxv b0, p7, z31.b
+// CHECK-INST: smaxv   b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x08,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 08 04 <unknown>
+
+smaxv h0, p7, z31.h
+// CHECK-INST: smaxv   h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x48,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 48 04 <unknown>
+
+smaxv s0, p7, z31.s
+// CHECK-INST: smaxv   s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x88,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 88 04 <unknown>
+
+smaxv d0, p7, z31.d
+// CHECK-INST: smaxv   d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c8 04 <unknown>

diff --git a/test/MC/AArch64/SVE/sminv-diagnostics.s b/test/MC/AArch64/SVE/sminv-diagnostics.s
new file mode 100644 (file)
index 0000000..85f5577
--- /dev/null
+++ b/test/MC/AArch64/SVE/sminv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+sminv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sminv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sminv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sminv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sminv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sminv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sminv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sminv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+sminv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: sminv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/sminv.s b/test/MC/AArch64/SVE/sminv.s
new file mode 100644 (file)
index 0000000..6490813
--- /dev/null
+++ b/test/MC/AArch64/SVE/sminv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sminv b0, p7, z31.b
+// CHECK-INST: sminv   b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x0a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 0a 04 <unknown>
+
+sminv h0, p7, z31.h
+// CHECK-INST: sminv   h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x4a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 4a 04 <unknown>
+
+sminv s0, p7, z31.s
+// CHECK-INST: sminv   s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x8a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 8a 04 <unknown>
+
+sminv d0, p7, z31.d
+// CHECK-INST: sminv   d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xca,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f ca 04 <unknown>

diff --git a/test/MC/AArch64/SVE/uaddv-diagnostics.s b/test/MC/AArch64/SVE/uaddv-diagnostics.s
new file mode 100644 (file)
index 0000000..11ec959
--- /dev/null
+++ b/test/MC/AArch64/SVE/uaddv-diagnostics.s
@@ -0,0 +1,29 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+uaddv s0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uaddv s0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uaddv s0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uaddv s0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uaddv s0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uaddv s0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+uaddv d0, p8, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: uaddv d0, p8, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/uaddv.s b/test/MC/AArch64/SVE/uaddv.s
new file mode 100644 (file)
index 0000000..07da5ab
--- /dev/null
+++ b/test/MC/AArch64/SVE/uaddv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uaddv d0, p7, z31.b
+// CHECK-INST: uaddv   d0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x01,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 01 04 <unknown>
+
+uaddv d0, p7, z31.h
+// CHECK-INST: uaddv   d0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x41,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 41 04 <unknown>
+
+uaddv d0, p7, z31.s
+// CHECK-INST: uaddv   d0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x81,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 81 04 <unknown>
+
+uaddv d0, p7, z31.d
+// CHECK-INST: uaddv   d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc1,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c1 04 <unknown>

diff --git a/test/MC/AArch64/SVE/umaxv-diagnostics.s b/test/MC/AArch64/SVE/umaxv-diagnostics.s
new file mode 100644 (file)
index 0000000..cfcabb9
--- /dev/null
+++ b/test/MC/AArch64/SVE/umaxv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+umaxv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umaxv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umaxv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umaxv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umaxv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: umaxv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umaxv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: umaxv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+umaxv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: umaxv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/umaxv.s b/test/MC/AArch64/SVE/umaxv.s
new file mode 100644 (file)
index 0000000..c573e1b
--- /dev/null
+++ b/test/MC/AArch64/SVE/umaxv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+umaxv b0, p7, z31.b
+// CHECK-INST: umaxv   b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x09,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 09 04 <unknown>
+
+umaxv h0, p7, z31.h
+// CHECK-INST: umaxv   h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x49,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 49 04 <unknown>
+
+umaxv s0, p7, z31.s
+// CHECK-INST: umaxv   s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x89,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 89 04 <unknown>
+
+umaxv d0, p7, z31.d
+// CHECK-INST: umaxv   d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xc9,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f c9 04 <unknown>

diff --git a/test/MC/AArch64/SVE/uminv-diagnostics.s b/test/MC/AArch64/SVE/uminv-diagnostics.s
new file mode 100644 (file)
index 0000000..9208dc9
--- /dev/null
+++ b/test/MC/AArch64/SVE/uminv-diagnostics.s
@@ -0,0 +1,34 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid destination or source register.
+
+uminv d0, p7, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uminv d0, p7, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uminv d0, p7, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uminv d0, p7, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uminv d0, p7, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uminv d0, p7, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uminv v0.2d, p7, z31.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uminv v0.2d, p7, z31.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate
+
+uminv h0, p8, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: uminv h0, p8, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
\ No newline at end of file

diff --git a/test/MC/AArch64/SVE/uminv.s b/test/MC/AArch64/SVE/uminv.s
new file mode 100644 (file)
index 0000000..e2512da
--- /dev/null
+++ b/test/MC/AArch64/SVE/uminv.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uminv b0, p7, z31.b
+// CHECK-INST: uminv   b0, p7, z31.b
+// CHECK-ENCODING: [0xe0,0x3f,0x0b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 0b 04 <unknown>
+
+uminv h0, p7, z31.h
+// CHECK-INST: uminv   h0, p7, z31.h
+// CHECK-ENCODING: [0xe0,0x3f,0x4b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 4b 04 <unknown>
+
+uminv s0, p7, z31.s
+// CHECK-INST: uminv   s0, p7, z31.s
+// CHECK-ENCODING: [0xe0,0x3f,0x8b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f 8b 04 <unknown>
+
+uminv d0, p7, z31.d
+// CHECK-INST: uminv   d0, p7, z31.d
+// CHECK-ENCODING: [0xe0,0x3f,0xcb,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 3f cb 04 <unknown>