* x86id.re: Add support for VIA PadLock instructions.

* padlock.asm: New testcase for these instructions.

svn path=/trunk/yasm/; revision=1267

diff --git a/modules/arch/x86/tests/Makefile.inc b/modules/arch/x86/tests/Makefile.inc
index 2758332e05244c733e9209c1f5e18b769174aef1..fd8f11358b7dcda46055b786a2910fca0457a822 100644 (file)
--- a/modules/arch/x86/tests/Makefile.inc
+++ b/modules/arch/x86/tests/Makefile.inc
@@ -112,6 +112,9 @@ EXTRA_DIST += modules/arch/x86/tests/opsize-err.errwarn
 EXTRA_DIST += modules/arch/x86/tests/overflow.asm
 EXTRA_DIST += modules/arch/x86/tests/overflow.errwarn
 EXTRA_DIST += modules/arch/x86/tests/overflow.hex
+EXTRA_DIST += modules/arch/x86/tests/padlock.asm
+EXTRA_DIST += modules/arch/x86/tests/padlock.errwarn
+EXTRA_DIST += modules/arch/x86/tests/padlock.hex
 EXTRA_DIST += modules/arch/x86/tests/pshift.asm
 EXTRA_DIST += modules/arch/x86/tests/pshift.errwarn
 EXTRA_DIST += modules/arch/x86/tests/pshift.hex

diff --git a/modules/arch/x86/tests/padlock.asm b/modules/arch/x86/tests/padlock.asm
new file mode 100644 (file)
index 0000000..24fb755
--- /dev/null
+++ b/modules/arch/x86/tests/padlock.asm
@@ -0,0 +1,16 @@
+;xstore-rng
+xstorerng
+xstore
+;xcrypt-ecb
+xcryptecb
+;xcrypt-cbc
+xcryptcbc
+;xcrypt-ctr
+xcryptctr
+;xcrypt-cfb
+xcryptcfb
+;xcrypt-ofb
+xcryptofb
+montmul
+xsha1
+xsha256

diff --git a/modules/arch/x86/tests/padlock.errwarn b/modules/arch/x86/tests/padlock.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/padlock.hex b/modules/arch/x86/tests/padlock.hex
new file mode 100644 (file)
index 0000000..081730e
--- /dev/null
+++ b/modules/arch/x86/tests/padlock.hex
@@ -0,0 +1,38 @@
+0f 
+a7 
+c0 
+0f 
+a7 
+c0 
+f3 
+0f 
+a7 
+c8 
+f3 
+0f 
+a7 
+d0 
+f3 
+0f 
+a7 
+d8 
+f3 
+0f 
+a7 
+e0 
+f3 
+0f 
+a7 
+e8 
+f3 
+0f 
+a6 
+c0 
+f3 
+0f 
+a6 
+c8 
+f3 
+0f 
+a6 
+d0 

diff --git a/modules/arch/x86/x86arch.h b/modules/arch/x86/x86arch.h
index 3cc57e5bba9e4c3032b246e25353f3c662195eef..3d317abf7ca41e8f9af3d7fcc3aa43a2a235a96c 100644 (file)
--- a/modules/arch/x86/x86arch.h
+++ b/modules/arch/x86/x86arch.h
@@ -56,12 +56,13 @@
 #define CPU_Obs            (1UL<<23)   /* Obsolete instruction */
 #define CPU_Priv    (1UL<<24)  /* Priveleged instruction */
 #define CPU_SVM            (1UL<<25)   /* Secure Virtual Machine instruction */
+#define CPU_PadLock (1UL<<25)  /* VIA PadLock instruction */
 
 /* Technically not CPU capabilities, they do affect what instructions are
  * available.  These are tested against BITS==64.
  */
-#define CPU_64     (1UL<<25)   /* Only available in 64-bit mode */
-#define CPU_Not64   (1UL<<26)  /* Not available (invalid) in 64-bit mode */
+#define CPU_64     (1UL<<26)   /* Only available in 64-bit mode */
+#define CPU_Not64   (1UL<<27)  /* Not available (invalid) in 64-bit mode */
 
 typedef struct yasm_arch_x86 {
     yasm_arch_base arch;       /* base structure */

diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re
index cfbb56550b822ea8beaddc64d1c6a5945fd8fc22..d7f346c1c09d8cdcd80e5784e1e85ce5085478a9 100644 (file)
--- a/modules/arch/x86/x86id.re
+++ b/modules/arch/x86/x86id.re
@@ -274,7 +274,7 @@ typedef struct x86_insn_info {
  */
 #define DEF_INSN_DATA(group, mod, cpu) do { \
     data[0] = (unsigned long)group##_insn; \
-    data[1] = ((mod)<<8) | \
+    data[1] = (((unsigned long)mod)<<8) | \
              ((unsigned char)(sizeof(group##_insn)/sizeof(x86_insn_info))); \
     data[2] = cpu; \
     data[3] |= arch_x86->mode_bits; \
@@ -1931,6 +1931,11 @@ static const x86_insn_info svm_rax_insn[] = {
     { CPU_SVM, MOD_Op2Add, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1,
       {OPT_Areg|OPS_64|OPA_None, 0, 0} }
 };
+/* VIA PadLock instructions */
+static const x86_insn_info padlock_insn[] = {
+    { CPU_Any, MOD_Imm8|MOD_PreAdd|MOD_Op1Add, 0, 0, 0x00, 2, {0x0F, 0x00, 0},
+      0, 0, {0, 0, 0} }
+};
 
 /* Cyrix MMX instructions */
 static const x86_insn_info cyrixmmx_insn[] = {
@@ -2983,6 +2988,8 @@ yasm_x86__parse_cpu(yasm_arch *arch, const char *id, unsigned long line)
        N O P R I V     { arch_x86->cpu_enabled &= ~CPU_Priv; return; }
        S V M           { arch_x86->cpu_enabled |= CPU_SVM; return; }
        N O S V M       { arch_x86->cpu_enabled &= ~CPU_SVM; return; }
+       P A D L O C K   { arch_x86->cpu_enabled |= CPU_PadLock; return; }
+       N O P A D L O C K   { arch_x86->cpu_enabled &= ~CPU_PadLock; return; }
 
        /* catchalls */
        [\001-\377]+    {
@@ -4408,6 +4415,16 @@ yasm_x86__parse_check_insn(yasm_arch *arch, unsigned long data[4],
        V M M C A L L { RET_INSN_NS(threebyte, 0x0F01D9, CPU_Hammer|CPU_64|CPU_SVM); }
        V M R U N { RET_INSN_NS(svm_rax, 0xD8, CPU_Hammer|CPU_64|CPU_SVM); }
        V M S A V E { RET_INSN_NS(svm_rax, 0xDB, CPU_Hammer|CPU_64|CPU_SVM); }
+       /* VIA PadLock instructions */
+       X S T O R E (R N G)? { RET_INSN_NS(padlock, 0xC000A7, CPU_PadLock); }
+       X C R Y P T E C B { RET_INSN_NS(padlock, 0xC8F3A7, CPU_PadLock); }
+       X C R Y P T C B C { RET_INSN_NS(padlock, 0xD0F3A7, CPU_PadLock); }
+       X C R Y P T C T R { RET_INSN_NS(padlock, 0xD8F3A7, CPU_PadLock); }
+       X C R Y P T C F B { RET_INSN_NS(padlock, 0xE0F3A7, CPU_PadLock); }
+       X C R Y P T O F B { RET_INSN_NS(padlock, 0xE8F3A7, CPU_PadLock); }
+       M O N T M U L { RET_INSN_NS(padlock, 0xC0F3A6, CPU_PadLock); }
+       X S H A "1" { RET_INSN_NS(padlock, 0xC8F3A6, CPU_PadLock); }
+       X S H A "256" { RET_INSN_NS(padlock, 0xD0F3A6, CPU_PadLock); }
        /* Cyrix MMX instructions */
        P A D D S I W { RET_INSN(7, cyrixmmx, 0x51, CPU_Cyrix|CPU_MMX); }
        P A V E B { RET_INSN(5, cyrixmmx, 0x50, CPU_Cyrix|CPU_MMX); }