#include <stddef.h>
#include <stdint.h>
#include <string.h>
+#include <stdio.h>
#include "unity.h"
#include "soc/soc.h"
#include "soc/dport_reg.h"
#include "freertos/semphr.h"
#include "freertos/task.h"
-/**
- * Tests for sending trace over JTAG
- *
- * block 1 as trace memory, block 0 as normal memory
- * CPU 0 and 1 write to BLK0 directly
- * when watermark is triggered (figure out how):
- * disable trace for block 1
- * set internal pointer to use block 1
- * switch tracemem mux to block 0
- *
- */
+// TODO: move these (and same definitions in trax.c to dport_reg.h)
#define TRACEMEM_MUX_PROBLK0_APPBLK1 0
#define TRACEMEM_MUX_BLK0_ONLY 1
#define TRACEMEM_MUX_BLK1_ONLY 2
#define TRACEMEM_MUX_PROBLK1_APPBLK0 3
-
static uint8_t* s_tracemem_blocks[] = {
- (uint8_t*) 0x3FFF8000,
- (uint8_t*) 0x3FFCC000
+ (uint8_t*) 0x3FFFC000,
+ (uint8_t*) 0x3FFF8000
};
static const size_t TRACEMEM_BLOCK_SIZE = 0x4000;
-//static void trace_enable()
-//{
-// if (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP) {
-// WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, (which == TRAX_ENA_PRO_APP_SWAP)?TRACEMEM_MUX_PROBLK1_APPBLK0:TRACEMEM_MUX_PROBLK0_APPBLK1);
-// } else {
-// WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK0_ONLY);
-// }
-// WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP || which == TRAX_ENA_PRO));
-// WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, (which == TRAX_ENA_PRO_APP || which == TRAX_ENA_PRO_APP_SWAP || which == TRAX_ENA_APP));
-//
-//}
-
typedef struct {
int block;
SemaphoreHandle_t done;
TEST_CASE("both CPUs can write to trace block 0", "[trace][ignore]")
{
+ // Configure block 1 as trace memory, enable access via both CPUs
+ WRITE_PERI_REG(DPORT_PRO_TRACEMEM_ENA_REG, DPORT_PRO_TRACEMEM_ENA_M);
+ WRITE_PERI_REG(DPORT_APP_TRACEMEM_ENA_REG, DPORT_APP_TRACEMEM_ENA_M);
WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK1_ONLY);
+ // Stop trace, if any (on the current CPU)
+ eri_write(ERI_TRAX_TRAXCTRL, eri_read(ERI_TRAX_TRAXCTRL) | TRAXCTRL_TRSTP);
+ eri_write(ERI_TRAX_TRAXCTRL, TRAXCTRL_TMEN);
+ // TODO: make sure trace is not running on the other CPU
+
+ // fill two halves of the first trace mem block
fill_tracemem_arg_t arg1 = {
.block = 0,
.done = xSemaphoreCreateBinary()
.block = 0,
.done = xSemaphoreCreateBinary()
};
-
xTaskCreatePinnedToCore(&fill_tracemem, "fill1", 2048, &arg1, 3, NULL, 0);
- xTaskCreatePinnedToCore(&fill_tracemem, "fill2", 2048, &arg2, 3, NULL, 0);
-
+ xTaskCreatePinnedToCore(&fill_tracemem, "fill2", 2048, &arg2, 3, NULL, 1);
xSemaphoreTake(arg1.done, 1);
xSemaphoreTake(arg2.done, 1);
+ vSemaphoreDelete(arg1.done);
+ vSemaphoreDelete(arg2.done);
+ // Block 0 is filled with data — configure it as trace memory so that it is accessible via TRAX module
WRITE_PERI_REG(DPORT_TRACEMEM_MUX_MODE_REG, TRACEMEM_MUX_BLK0_ONLY);
+ // Block 1 can now be filled with data
}
-
-