-//===- LexicalScopes.cpp - Collecting lexical scope info -*- C++ -*--------===//
+//===- LexicalScopes.cpp - Collecting lexical scope info --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DebugInfoMetadata.h"
-#include "llvm/IR/ValueHandle.h"
+#include <cassert>
#include <unordered_map>
#include <utility>
+
namespace llvm {
-class MachineInstr;
class MachineBasicBlock;
class MachineFunction;
+class MachineInstr;
//===----------------------------------------------------------------------===//
/// InsnRange - This is used to track range of instructions with identical
/// LexicalScope - This class is used to track scope information.
///
class LexicalScope {
-
public:
LexicalScope(LexicalScope *P, const DILocalScope *D, const DILocation *I,
bool A)
- : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A),
- LastInsn(nullptr), FirstInsn(nullptr), DFSIn(0), DFSOut(0) {
+ : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A) {
assert(D);
assert(D->getSubprogram()->getUnit()->getEmissionKind() !=
DICompileUnit::NoDebug &&
// Contents not owned.
SmallVector<InsnRange, 4> Ranges;
- const MachineInstr *LastInsn; // Last instruction of this scope.
- const MachineInstr *FirstInsn; // First instruction of this scope.
- unsigned DFSIn, DFSOut; // In & Out Depth use to determine
- // scope nesting.
+ const MachineInstr *LastInsn = nullptr; // Last instruction of this scope.
+ const MachineInstr *FirstInsn = nullptr; // First instruction of this scope.
+ unsigned DFSIn = 0; // In & Out Depth use to determine scope nesting.
+ unsigned DFSOut = 0;
};
//===----------------------------------------------------------------------===//
///
class LexicalScopes {
public:
- LexicalScopes() : MF(nullptr), CurrentFnLexicalScope(nullptr) {}
+ LexicalScopes() = default;
/// initialize - Scan machine function and constuct lexical scope nest, resets
/// the instance if necessary.
assignInstructionRanges(SmallVectorImpl<InsnRange> &MIRanges,
DenseMap<const MachineInstr *, LexicalScope *> &M);
-private:
- const MachineFunction *MF;
+ const MachineFunction *MF = nullptr;
/// LexicalScopeMap - Tracks the scopes in the current function.
// Use an unordered_map to ensure value pointer validity over insertion.
/// CurrentFnLexicalScope - Top level scope for the current function.
///
- LexicalScope *CurrentFnLexicalScope;
+ LexicalScope *CurrentFnLexicalScope = nullptr;
};
-} // end llvm namespace
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_LEXICALSCOPES_H
-//===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
+//===- LiveIntervalUnion.h - Live interval union data struct ---*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
#define LLVM_CODEGEN_LIVEINTERVALUNION_H
#include "llvm/ADT/IntervalMap.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include <cassert>
+#include <limits>
namespace llvm {
// LiveIntervalUnions share an external allocator.
typedef LiveSegments::Allocator Allocator;
- class Query;
-
private:
- unsigned Tag; // unique tag for current contents.
+ unsigned Tag = 0; // unique tag for current contents.
LiveSegments Segments; // union of virtual reg segments
public:
- explicit LiveIntervalUnion(Allocator &a) : Tag(0), Segments(a) {}
+ explicit LiveIntervalUnion(Allocator &a) : Segments(a) {}
// Iterate over all segments in the union of live virtual registers ordered
// by their starting position.
/// Query interferences between a single live virtual register and a live
/// interval union.
class Query {
- LiveIntervalUnion *LiveUnion;
- LiveInterval *VirtReg;
+ LiveIntervalUnion *LiveUnion = nullptr;
+ LiveInterval *VirtReg = nullptr;
LiveInterval::iterator VirtRegI; // current position in VirtReg
SegmentIter LiveUnionI; // current position in LiveUnion
SmallVector<LiveInterval*,4> InterferingVRegs;
- bool CheckedFirstInterference;
- bool SeenAllInterferences;
- bool SeenUnspillableVReg;
- unsigned Tag, UserTag;
+ bool CheckedFirstInterference = false;
+ bool SeenAllInterferences = false;
+ bool SeenUnspillableVReg = false;
+ unsigned Tag = 0;
+ unsigned UserTag = 0;
public:
- Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
-
+ Query() = default;
Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
- LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
- SeenAllInterferences(false), SeenUnspillableVReg(false)
- {}
+ LiveUnion(LIU), VirtReg(VReg) {}
+ Query(const Query &) = delete;
+ Query &operator=(const Query &) = delete;
void clear() {
LiveUnion = nullptr;
// Count the virtual registers in this union that interfere with this
// query's live virtual register, up to maxInterferingRegs.
- unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
+ unsigned collectInterferingVRegs(
+ unsigned MaxInterferingRegs = std::numeric_limits<unsigned>::max());
// Was this virtual register visited during collectInterferingVRegs?
bool isSeenInterference(LiveInterval *VReg) const;
const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
return InterferingVRegs;
}
-
- private:
- Query(const Query&) = delete;
- void operator=(const Query&) = delete;
};
// Array of LiveIntervalUnions.
class Array {
- unsigned Size;
- LiveIntervalUnion *LIUs;
+ unsigned Size = 0;
+ LiveIntervalUnion *LIUs = nullptr;
+
public:
- Array() : Size(0), LIUs(nullptr) {}
+ Array() = default;
~Array() { clear(); }
// Initialize the array to have Size entries.
} // end namespace llvm
-#endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION_H)
+#endif // LLVM_CODEGEN_LIVEINTERVALUNION_H
-//===-- LiveRegMatrix.h - Track register interference ---------*- C++ -*---===//
+//===- LiveRegMatrix.h - Track register interference ----------*- C++ -*---===//
//
// The LLVM Compiler Infrastructure
//
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/LiveIntervalUnion.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include <memory>
namespace llvm {
+class AnalysisUsage;
class LiveInterval;
-class LiveIntervalAnalysis;
+class LiveIntervals;
+class MachineFunction;
class TargetRegisterInfo;
class VirtRegMap;
VirtRegMap *VRM;
// UserTag changes whenever virtual registers have been modified.
- unsigned UserTag;
+ unsigned UserTag = 0;
// The matrix is represented as a LiveIntervalUnion per register unit.
LiveIntervalUnion::Allocator LIUAlloc;
std::unique_ptr<LiveIntervalUnion::Query[]> Queries;
// Cached register mask interference info.
- unsigned RegMaskTag;
- unsigned RegMaskVirtReg;
+ unsigned RegMaskTag = 0;
+ unsigned RegMaskVirtReg = 0;
BitVector RegMaskUsable;
// MachineFunctionPass boilerplate.
- void getAnalysisUsage(AnalysisUsage&) const override;
- bool runOnMachineFunction(MachineFunction&) override;
+ void getAnalysisUsage(AnalysisUsage &) const override;
+ bool runOnMachineFunction(MachineFunction &) override;
void releaseMemory() override;
+
public:
static char ID;
+
LiveRegMatrix();
//===--------------------------------------------------------------------===//
#include "llvm/ADT/BitVector.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include <cstdint>
namespace llvm {
/// A set of register units used to track register liveness.
class LiveRegUnits {
- const TargetRegisterInfo *TRI;
+ const TargetRegisterInfo *TRI = nullptr;
BitVector Units;
public:
/// Constructs a new empty LiveRegUnits set.
- LiveRegUnits() : TRI(nullptr) {}
+ LiveRegUnits() = default;
/// Constructs and initialize an empty LiveRegUnits set.
LiveRegUnits(const TargetRegisterInfo &TRI) {
}
};
-} // namespace llvm
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_LIVEREGUNITS_H
-//== llvm/CodeGen/GlobalISel/LowLevelType.h -------------------- -*- C++ -*-==//
+//===- llvm/CodeGen/GlobalISel/LowLevelType.h -------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
#ifndef LLVM_CODEGEN_GLOBALISEL_LOWLEVELTYPE_H
#define LLVM_CODEGEN_GLOBALISEL_LOWLEVELTYPE_H
-#include <cassert>
#include "llvm/ADT/DenseMapInfo.h"
-#include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include <cassert>
+#include <cstdint>
namespace llvm {
class DataLayout;
-class LLVMContext;
-class Type;
class raw_ostream;
+class Type;
class LLT {
public:
+ friend struct DenseMapInfo<LLT>;
+
enum TypeKind : uint16_t {
Invalid,
Scalar,
Vector,
};
+ explicit LLT(TypeKind Kind, uint16_t NumElements, unsigned SizeInBits)
+ : SizeInBits(SizeInBits), ElementsOrAddrSpace(NumElements), Kind(Kind) {
+ assert((Kind != Vector || ElementsOrAddrSpace > 1) &&
+ "invalid number of vector elements");
+ }
+
+ explicit LLT() = default;
+
+ /// Construct a low-level type based on an LLVM type.
+ explicit LLT(Type &Ty, const DataLayout &DL);
+
+ explicit LLT(MVT VT);
+
/// Get a low-level scalar or aggregate "bag of bits".
static LLT scalar(unsigned SizeInBits) {
assert(SizeInBits > 0 && "invalid scalar size");
return LLT{Vector, NumElements, ScalarTy.getSizeInBits()};
}
- explicit LLT(TypeKind Kind, uint16_t NumElements, unsigned SizeInBits)
- : SizeInBits(SizeInBits), ElementsOrAddrSpace(NumElements), Kind(Kind) {
- assert((Kind != Vector || ElementsOrAddrSpace > 1) &&
- "invalid number of vector elements");
- }
-
- explicit LLT() : SizeInBits(0), ElementsOrAddrSpace(0), Kind(Invalid) {}
-
- /// Construct a low-level type based on an LLVM type.
- explicit LLT(Type &Ty, const DataLayout &DL);
-
- explicit LLT(MVT VT);
-
bool isValid() const { return Kind != Invalid; }
bool isScalar() const { return Kind == Scalar; }
bool operator!=(const LLT &RHS) const { return !(*this == RHS); }
- friend struct DenseMapInfo<LLT>;
private:
- unsigned SizeInBits;
- uint16_t ElementsOrAddrSpace;
- TypeKind Kind;
+ unsigned SizeInBits = 0;
+ uint16_t ElementsOrAddrSpace = 0;
+ TypeKind Kind = Invalid;
};
inline raw_ostream& operator<<(raw_ostream &OS, const LLT &Ty) {
static inline LLT getEmptyKey() {
return LLT{LLT::Invalid, 0, -1u};
}
+
static inline LLT getTombstoneKey() {
return LLT{LLT::Invalid, 0, -2u};
}
+
static inline unsigned getHashValue(const LLT &Ty) {
uint64_t Val = ((uint64_t)Ty.SizeInBits << 32) |
((uint64_t)Ty.ElementsOrAddrSpace << 16) | (uint64_t)Ty.Kind;
return DenseMapInfo<uint64_t>::getHashValue(Val);
}
+
static bool isEqual(const LLT &LHS, const LLT &RHS) {
return LHS == RHS;
}
};
-}
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_GLOBALISEL_LOWLEVELTYPE_H
-//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
+//===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/IndexedMap.h"
-#include "llvm/ADT/PointerUnion.h"
#include "llvm/ADT/iterator_range.h"
-// PointerUnion needs to have access to the full RegisterBank type.
+#include "llvm/ADT/PointerUnion.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/LowLevelType.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/MC/LaneBitmask.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <vector>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <iterator>
+#include <memory>
+#include <utility>
namespace llvm {
+
class PSetIterator;
/// Convenient type to represent either a register class or a register bank.
public:
class Delegate {
virtual void anchor();
+
public:
- virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
+ virtual ~Delegate() = default;
- virtual ~Delegate() {}
+ virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
};
private:
MachineFunction *MF;
- Delegate *TheDelegate;
+ Delegate *TheDelegate = nullptr;
/// True if subregister liveness is tracked.
const bool TracksSubRegLiveness;
/// Live in values are typically arguments in registers. LiveIn values are
/// allowed to have virtual registers associated with them, stored in the
/// second element.
- std::vector<std::pair<unsigned, unsigned> > LiveIns;
+ std::vector<std::pair<unsigned, unsigned>> LiveIns;
- MachineRegisterInfo(const MachineRegisterInfo&) = delete;
- void operator=(const MachineRegisterInfo&) = delete;
public:
explicit MachineRegisterInfo(MachineFunction *MF);
+ MachineRegisterInfo(const MachineRegisterInfo &) = delete;
+ MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
const TargetRegisterInfo *getTargetRegisterInfo() const {
return MF->getSubtarget().getRegisterInfo();
template<bool, bool, bool, bool, bool, bool>
friend class defusechain_instr_iterator;
-
-
/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
/// register.
typedef defusechain_iterator<true,true,false,true,false,false>
// Iteration support for the live-ins set. It's kept in sorted order
// by register number.
- typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
+ typedef std::vector<std::pair<unsigned,unsigned>>::const_iterator
livein_iterator;
livein_iterator livein_begin() const { return LiveIns.begin(); }
livein_iterator livein_end() const { return LiveIns.end(); }
bool ByOperand, bool ByInstr, bool ByBundle>
class defusechain_iterator
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
- MachineOperand *Op;
+ friend class MachineRegisterInfo;
+
+ MachineOperand *Op = nullptr;
+
explicit defusechain_iterator(MachineOperand *op) : Op(op) {
// If the first node isn't one we're interested in, advance to one that
// we are interested in.
advance();
}
}
- friend class MachineRegisterInfo;
void advance() {
assert(Op && "Cannot increment end iterator!");
Op = getNextOperandForReg(Op);
}
}
+
public:
typedef std::iterator<std::forward_iterator_tag,
MachineInstr, ptrdiff_t>::reference reference;
typedef std::iterator<std::forward_iterator_tag,
MachineInstr, ptrdiff_t>::pointer pointer;
- defusechain_iterator() : Op(nullptr) {}
+ defusechain_iterator() = default;
bool operator==(const defusechain_iterator &x) const {
return Op == x.Op;
bool ByOperand, bool ByInstr, bool ByBundle>
class defusechain_instr_iterator
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
- MachineOperand *Op;
+ friend class MachineRegisterInfo;
+
+ MachineOperand *Op = nullptr;
+
explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
// If the first node isn't one we're interested in, advance to one that
// we are interested in.
advance();
}
}
- friend class MachineRegisterInfo;
void advance() {
assert(Op && "Cannot increment end iterator!");
Op = getNextOperandForReg(Op);
}
}
+
public:
typedef std::iterator<std::forward_iterator_tag,
MachineInstr, ptrdiff_t>::reference reference;
typedef std::iterator<std::forward_iterator_tag,
MachineInstr, ptrdiff_t>::pointer pointer;
- defusechain_instr_iterator() : Op(nullptr) {}
+ defusechain_instr_iterator() = default;
bool operator==(const defusechain_instr_iterator &x) const {
return Op == x.Op;
/// register. If Reg is physical, it must be a register unit (from
/// MCRegUnitIterator).
class PSetIterator {
- const int *PSet;
- unsigned Weight;
+ const int *PSet = nullptr;
+ unsigned Weight = 0;
+
public:
- PSetIterator(): PSet(nullptr), Weight(0) {}
+ PSetIterator() = default;
+
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
if (*PSet == -1)
PSet = nullptr;
}
+
bool isValid() const { return PSet; }
unsigned getWeight() const { return Weight; }
return PSetIterator(RegUnit, this);
}
-} // End llvm namespace
+} // end namespace llvm
-#endif
+#endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H
//
//===----------------------------------------------------------------------===//
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LexicalScopes.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/IR/DebugInfo.h"
-#include "llvm/IR/Function.h"
+#include "llvm/IR/DebugInfoMetadata.h"
+#include "llvm/IR/Metadata.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+#include <string>
+#include <tuple>
+#include <utility>
+
using namespace llvm;
#define DEBUG_TYPE "lexicalscopes"
void LexicalScopes::extractLexicalScopes(
SmallVectorImpl<InsnRange> &MIRanges,
DenseMap<const MachineInstr *, LexicalScope *> &MI2ScopeMap) {
-
// Scan each instruction and create scopes. First build working set of scopes.
for (const auto &MBB : *MF) {
const MachineInstr *RangeBeginMI = nullptr;
void LexicalScopes::assignInstructionRanges(
SmallVectorImpl<InsnRange> &MIRanges,
DenseMap<const MachineInstr *, LexicalScope *> &MI2ScopeMap) {
-
LexicalScope *PrevLexicalScope = nullptr;
for (const auto &R : MIRanges) {
LexicalScope *S = MI2ScopeMap.lookup(R.first);
-//===-- LiveIntervalUnion.cpp - Live interval union data structure --------===//
+//===- LiveIntervalUnion.cpp - Live interval union data structure ---------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/LiveIntervalUnion.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SparseBitVector.h"
-#include "llvm/Support/Debug.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/CodeGen/LiveInterval.h"
+#include "llvm/CodeGen/LiveIntervalUnion.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
-#include <algorithm>
+#include <cassert>
+#include <cstdlib>
using namespace llvm;
#define DEBUG_TYPE "regalloc"
-
// Merge a LiveInterval's segments. Guarantee no overlaps.
void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
if (Range.empty())
LiveRange::const_iterator RegEnd = Range.end();
SegmentIter SegPos = Segments.find(RegPos->start);
- for (;;) {
+ while (true) {
assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
SegPos.erase();
if (!SegPos.valid())
-//===-- LiveRegMatrix.cpp - Track register interference -------------------===//
+//===- LiveRegMatrix.cpp - Track register interference --------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/LiveRegMatrix.h"
#include "RegisterCoalescer.h"
#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/CodeGen/LiveIntervalUnion.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Pass.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cassert>
using namespace llvm;
INITIALIZE_PASS_END(LiveRegMatrix, "liveregmatrix",
"Live Register Matrix", false, false)
-LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID),
- UserTag(0), RegMaskTag(0), RegMaskVirtReg(0) {}
+LiveRegMatrix::LiveRegMatrix() : MachineFunctionPass(ID) {}
void LiveRegMatrix::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
-//===--- LiveRegUnits.cpp - Register Unit Set -----------------------------===//
+//===- LiveRegUnits.cpp - Register Unit Set -------------------------------===//
//
// The LLVM Compiler Infrastructure
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/LiveRegUnits.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Target/TargetRegisterInfo.h"
+
using namespace llvm;
void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
-//===-- llvm/CodeGen/GlobalISel/LowLevelType.cpp --------------------------===//
+//===- llvm/CodeGen/GlobalISel/LowLevelType.cpp ---------------------------===//
//
// The LLVM Compiler Infrastructure
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/LowLevelType.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Type.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include <cassert>
+
using namespace llvm;
LLT::LLT(Type &Ty, const DataLayout &DL) {
-//===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
+//===- lib/Codegen/MachineRegisterInfo.cpp --------------------------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
-#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/ADT/iterator_range.h"
+#include "llvm/CodeGen/LowLevelType.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/Attributes.h"
+#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
-#include "llvm/Support/raw_os_ostream.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <cassert>
using namespace llvm;
void MachineRegisterInfo::Delegate::anchor() {}
MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
- : MF(MF), TheDelegate(nullptr),
- TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
- EnableSubRegLiveness) {
+ : MF(MF), TracksSubRegLiveness(MF->getSubtarget().enableSubRegLiveness() &&
+ EnableSubRegLiveness) {
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
VRegInfo.reserve(256);
RegAllocHints.reserve(256);
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