/// %EAX - a physical register
/// %physreg17 - a physical register when no TRI instance given.
///
-/// Usage: OS << PrintReg(Reg, TRI) << '\n';
-Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
+/// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
+Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
unsigned SubRegIdx = 0);
/// Create Printable object to print register units on a \ref raw_ostream.
/// AL - Single root.
/// FP0~ST7 - Dual roots.
///
-/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
-Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
+/// Usage: OS << printRegUnit(Unit, TRI) << '\n';
+Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
/// \brief Create Printable object to print virtual registers and physical
/// registers on a \ref raw_ostream.
-Printable PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
+Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
} // end namespace llvm
if (!Hints.empty()) {
dbgs() << "hints:";
for (unsigned I = 0, E = Hints.size(); I != E; ++I)
- dbgs() << ' ' << PrintReg(Hints[I], TRI);
+ dbgs() << ' ' << printReg(Hints[I], TRI);
dbgs() << '\n';
}
});
SmallString<128> Str;
raw_svector_ostream OS(Str);
OS << "implicit-def: "
- << PrintReg(RegNo, MF->getSubtarget().getRegisterInfo());
+ << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
OutStreamer->AddComment(OS.str());
OutStreamer->AddBlankLine();
const MachineOperand &Op = MI->getOperand(i);
assert(Op.isReg() && "KILL instruction must have only register operands");
OS << ' '
- << PrintReg(Op.getReg(),
+ << printReg(Op.getReg(),
AP.MF->getSubtarget().getRegisterInfo())
<< (Op.isDef() ? "<def>" : "<kill>");
}
}
if (MemLoc)
OS << '[';
- OS << PrintReg(Reg, AP.MF->getSubtarget().getRegisterInfo());
+ OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo());
}
if (MemLoc)
for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
const VRegInfo &Info = VRegInfos[RegIdx];
- dbgs() << PrintReg(Reg, nullptr)
+ dbgs() << printReg(Reg, nullptr)
<< " Used: " << PrintLaneMask(Info.UsedLanes)
<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
}
dbgs() << "Would clobber";
for (SparseSet<unsigned>::const_iterator
i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
- dbgs() << ' ' << PrintRegUnit(*i, TRI);
+ dbgs() << ' ' << printRegUnit(*i, TRI);
dbgs() << " live before " << *I;
});
continue;
MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first;
DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
}
- DEBUG(dbgs() << "Update use with: " << PrintReg(NewVRegIt->second)
+ DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
<< '\n');
// Update the user reg.
MOUse.setReg(NewVRegIt->second);
// same types because the type is a placeholder when this function is called.
MachineInstr *MI =
MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src);
- DEBUG(dbgs() << "Copy: " << PrintReg(Src) << " to: " << PrintReg(Dst)
+ DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
<< '\n');
// TODO:
// Check if MI is legal. if not, we need to legalize all the
}
unsigned OrigReg = MO.getReg();
unsigned NewReg = *NewRegs.begin();
- DEBUG(dbgs() << " changed, replace " << PrintReg(OrigReg, nullptr));
+ DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
MO.setReg(NewReg);
- DEBUG(dbgs() << " with " << PrintReg(NewReg, nullptr));
+ DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
// The OperandsMapper creates plain scalar, we may have to fix that.
// Check if the types match and if not, fix that.
if (!IsFirst)
OS << ", ";
IsFirst = false;
- OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
+ OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
bool IsFirstNewVReg = true;
for (unsigned VReg : getVRegs(Idx)) {
if (!IsFirstNewVReg)
OS << ", ";
IsFirstNewVReg = false;
- OS << PrintReg(VReg, TRI);
+ OS << printReg(VReg, TRI);
}
OS << "])";
}
/// spillAroundUses - insert spill code around each use of Reg.
void InlineSpiller::spillAroundUses(unsigned Reg) {
- DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n');
+ DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
LiveInterval &OldLI = LIS.getInterval(Reg);
// Iterate over instructions using Reg.
DEBUG(dbgs() << "Inline spilling "
<< TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
<< ':' << edit.getParent()
- << "\nFrom original " << PrintReg(Original) << '\n');
+ << "\nFrom original " << printReg(Original) << '\n');
assert(edit.getParent().isSpillable() &&
"Attempting to spill already spilled value.");
assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
// Check if the register is the location of a debug value.
for (unsigned ID : OpenRanges.getVarLocs()) {
if (VarLocIDs[ID].isDescribedByReg() == Reg) {
- DEBUG(dbgs() << "Spilling Register " << PrintReg(Reg, TRI) << '('
+ DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
<< VarLocIDs[ID].Var.getVar()->getName() << ")\n");
// Create a DBG_VALUE instruction to describe the Var in its spilled
}
void LiveInterval::print(raw_ostream &OS) const {
- OS << PrintReg(reg) << ' ';
+ OS << printReg(reg) << ' ';
super::print(OS);
// Print subranges
for (const SubRange &SR : subranges())
// Dump the regunits.
for (unsigned Unit = 0, UnitE = RegUnitRanges.size(); Unit != UnitE; ++Unit)
if (LiveRange *LR = RegUnitRanges[Unit])
- OS << PrintRegUnit(Unit, TRI) << ' ' << *LR << '\n';
+ OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n';
// Dump the virtregs.
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
}
VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
(void)VNI;
- DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
+ DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
}
}
DEBUG(dbgs() << '\n');
DEBUG({
dbgs() << " ";
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
- dbgs() << PrintReg(Reg);
+ dbgs() << printReg(Reg);
if (LaneMask.any())
dbgs() << " L" << PrintLaneMask(LaneMask);
} else {
- dbgs() << PrintRegUnit(Reg, &TRI);
+ dbgs() << printRegUnit(Reg, &TRI);
}
dbgs() << ":\t" << LR << '\n';
});
}
for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) {
OS << " [" << SI.start() << ' ' << SI.stop() << "):"
- << PrintReg(SI.value()->reg, TRI);
+ << printReg(SI.value()->reg, TRI);
}
OS << '\n';
}
}
for (const_iterator I = begin(), E = end(); I != E; ++I)
- OS << " " << PrintReg(*I, TRI);
+ OS << " " << printReg(*I, TRI);
OS << "\n";
}
#ifndef NDEBUG
if (MBB->pred_empty()) {
MBB->getParent()->verify();
- errs() << "Use of " << PrintReg(PhysReg)
+ errs() << "Use of " << printReg(PhysReg)
<< " does not have a corresponding definition on every path:\n";
const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);
if (MI != nullptr)
!MBB->isLiveIn(PhysReg)) {
MBB->getParent()->verify();
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
- errs() << "The register " << PrintReg(PhysReg, TRI)
+ errs() << "The register " << printReg(PhysReg, TRI)
<< " needs to be live in to BB#" << MBB->getNumber()
<< ", but is missing from the live-in list.\n";
report_fatal_error("Invalid global physical register");
if (MRI.recomputeRegClass(LI.reg))
DEBUG({
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
+ dbgs() << "Inflated " << printReg(LI.reg) << " to "
<< TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
});
VRAI.calculateSpillWeightAndHint(LI);
}
void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
- DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
- << " to " << PrintReg(PhysReg, TRI) << ':');
+ DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI)
+ << " to " << printReg(PhysReg, TRI) << ':');
assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) {
- DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range);
+ DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
Matrix[Unit].unify(VirtReg, Range);
return false;
});
void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
unsigned PhysReg = VRM->getPhys(VirtReg.reg);
- DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
- << " from " << PrintReg(PhysReg, TRI) << ':');
+ DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI)
+ << " from " << printReg(PhysReg, TRI) << ':');
VRM->clearVirt(VirtReg.reg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) {
- DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI));
+ DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
Matrix[Unit].extract(VirtReg, Range);
return false;
});
} // end namespace yaml
} // end namespace llvm
-static void printReg(unsigned Reg, raw_ostream &OS,
- const TargetRegisterInfo *TRI) {
+static void printRegMIR(unsigned Reg, raw_ostream &OS,
+ const TargetRegisterInfo *TRI) {
// TODO: Print Stack Slots.
if (!Reg)
OS << '_';
llvm_unreachable("Can't print this kind of register yet");
}
-static void printReg(unsigned Reg, yaml::StringValue &Dest,
- const TargetRegisterInfo *TRI) {
+static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
+ const TargetRegisterInfo *TRI) {
raw_string_ostream OS(Dest.Value);
- printReg(Reg, OS, TRI);
+ printRegMIR(Reg, OS, TRI);
}
void MIRPrinter::print(const MachineFunction &MF) {
if (RegMask[I / 32] & (1u << (I % 32))) {
if (IsRegInRegMaskFound)
OS << ',';
- printReg(I, OS, TRI);
+ printRegMIR(I, OS, TRI);
IsRegInRegMaskFound = true;
}
}
printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
if (PreferredReg)
- printReg(PreferredReg, VReg.PreferredRegister, TRI);
+ printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
MF.VirtualRegisters.push_back(VReg);
}
// Print the live ins.
for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
yaml::MachineFunctionLiveIn LiveIn;
- printReg(LI.first, LiveIn.Register, TRI);
+ printRegMIR(LI.first, LiveIn.Register, TRI);
if (LI.second)
- printReg(LI.second, LiveIn.VirtualRegister, TRI);
+ printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
MF.LiveIns.push_back(LiveIn);
}
std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
yaml::FlowStringValue Reg;
- printReg(*I, Reg, TRI);
+ printRegMIR(*I, Reg, TRI);
CalleeSavedRegisters.push_back(Reg);
}
MF.CalleeSavedRegisters = CalleeSavedRegisters;
for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
yaml::StringValue Reg;
- printReg(CSInfo.getReg(), Reg, TRI);
+ printRegMIR(CSInfo.getReg(), Reg, TRI);
auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
assert(StackObjectInfo != StackObjectOperandMapping.end() &&
"Invalid stack object index");
if (!First)
OS << ", ";
First = false;
- printReg(LI.PhysReg, OS, &TRI);
+ printRegMIR(LI.PhysReg, OS, &TRI);
if (!LI.LaneMask.all())
OS << ":0x" << PrintLaneMask(LI.LaneMask);
}
OS << "early-clobber ";
if (Op.isDebug())
OS << "debug-use ";
- printReg(Reg, OS, TRI);
+ printRegMIR(Reg, OS, TRI);
// Print the sub register.
if (Op.getSubReg() != 0)
OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
if (IsCommaNeeded)
OS << ", ";
- printReg(Reg, OS, TRI);
+ printRegMIR(Reg, OS, TRI);
IsCommaNeeded = true;
}
}
OS << "<badreg>";
return;
}
- printReg(Reg, OS, TRI);
+ printRegMIR(Reg, OS, TRI);
}
void MIPrinter::print(const MCCFIInstruction &CFI,
if (Indexes) OS << '\t';
OS << " Live Ins:";
for (const auto &LI : LiveIns) {
- OS << ' ' << PrintReg(LI.PhysReg, TRI);
+ OS << ' ' << printReg(LI.PhysReg, TRI);
if (!LI.LaneMask.all())
OS << ':' << PrintLaneMask(LI.LaneMask);
}
OS << "Function Live Ins: ";
for (MachineRegisterInfo::livein_iterator
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
- OS << PrintReg(I->first, TRI);
+ OS << printReg(I->first, TRI);
if (I->second)
- OS << " in " << PrintReg(I->second, TRI);
+ OS << " in " << printReg(I->second, TRI);
if (std::next(I) != E)
OS << ", ";
}
const TargetIntrinsicInfo *IntrinsicInfo) const {
switch (getType()) {
case MachineOperand::MO_Register:
- OS << PrintReg(getReg(), TRI, getSubReg());
+ OS << printReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isInternalRead() || isEarlyClobber() || isTied()) {
if (getRegMask()[MaskWord] & (1 << MaskBit)) {
if (PrintRegMaskNumRegs < 0 ||
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
- OS << " " << PrintReg(i, TRI);
+ OS << " " << printReg(i, TRI);
NumRegsEmitted++;
}
NumRegsInMask++;
else
OS << " "
<< TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
- OS << ':' << PrintReg(VirtRegs[i]);
+ OS << ':' << printReg(VirtRegs[i]);
for (unsigned j = i+1; j != VirtRegs.size();) {
if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
++j;
continue;
}
if (VirtRegs[i] != VirtRegs[j])
- OS << "," << PrintReg(VirtRegs[j]);
+ OS << "," << printReg(VirtRegs[j]);
VirtRegs.erase(VirtRegs.begin()+j);
}
}
MachineOperand *MO = &M;
MachineInstr *MI = MO->getParent();
if (!MI) {
- errs() << PrintReg(Reg, getTargetRegisterInfo())
+ errs() << printReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO
<< " has no parent instruction.\n";
Valid = false;
MachineOperand *MO0 = &MI->getOperand(0);
unsigned NumOps = MI->getNumOperands();
if (!(MO >= MO0 && MO < MO0+NumOps)) {
- errs() << PrintReg(Reg, getTargetRegisterInfo())
+ errs() << printReg(Reg, getTargetRegisterInfo())
<< " use list MachineOperand " << MO
<< " doesn't belong to parent MI: " << *MI;
Valid = false;
}
if (!MO->isReg()) {
- errs() << PrintReg(Reg, getTargetRegisterInfo())
+ errs() << printReg(Reg, getTargetRegisterInfo())
<< " MachineOperand " << MO << ": " << *MO
<< " is not a register\n";
Valid = false;
}
if (MO->getReg() != Reg) {
- errs() << PrintReg(Reg, getTargetRegisterInfo())
+ errs() << printReg(Reg, getTargetRegisterInfo())
<< " use-list MachineOperand " << MO << ": "
<< *MO << " is the wrong register\n";
Valid = false;
PDiff.addPressureChange(Reg, Decrement, &MRI);
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
- << PrintReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
+ << printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
<< ' ' << *SU.getInstr();
dbgs() << " to ";
PDiff.dump(*TRI);
}
} else {
assert(P.LaneMask.any());
- DEBUG(dbgs() << " LiveReg: " << PrintVRegOrUnit(Reg, TRI) << "\n");
+ DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
// This may be called before CurrentBottom has been initialized. However,
// BotRPTracker must have a valid position. We want the value live into the
// instruction or live out of the block, so ask for the previous
for (LiveInReg &LIR : TBI.LiveIns) {
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
LIR.Height = Heights.lookup(DefMI);
- DEBUG(dbgs() << ' ' << PrintReg(LIR.Reg) << '@' << LIR.Height);
+ DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
}
// Transfer the live regunits to the live-in list.
for (SparseSet<LiveRegUnit>::const_iterator
RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) {
TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
- DEBUG(dbgs() << ' ' << PrintRegUnit(RI->RegUnit, MTM.TRI)
+ DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI)
<< '@' << RI->Cycle);
}
DEBUG(dbgs() << '\n');
}
void MachineVerifier::report_context_vreg(unsigned VReg) const {
- errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n';
+ errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
}
void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
report_context_vreg(VRegOrUnit);
} else {
- errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n';
+ errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
}
}
++I)
if (MInfo.regsKilled.count(*I)) {
report("Virtual register killed in block, but needed live out.", &MBB);
- errs() << "Virtual register " << PrintReg(*I)
+ errs() << "Virtual register " << printReg(*I)
<< " is used after the block.\n";
}
}
if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB);
- errs() << "Virtual register " << PrintReg(Reg)
+ errs() << "Virtual register " << printReg(Reg)
<< " must be live through the block.\n";
}
} else {
if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB);
- errs() << "Virtual register " << PrintReg(Reg)
+ errs() << "Virtual register " << printReg(Reg)
<< " is not needed live through the block.\n";
}
}
if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF);
- errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
+ errs() << printReg(Reg, TRI) << " still has defs or uses\n";
continue;
}
IncomingReg = entry;
reusedIncoming = true;
++NumReused;
- DEBUG(dbgs() << "Reusing " << PrintReg(IncomingReg) << " for " << *MPhi);
+ DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi);
} else {
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
continue;
if (ShouldSplit) {
- DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#"
+ DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge BB#"
<< PreMBB->getNumber() << " -> BB#" << MBB.getNumber()
<< ": " << *BBI);
}
// instruction, not on the spill.
bool SpillKill = MachineBasicBlock::iterator(LR.LastUse) != MI;
LR.Dirty = false;
- DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
- << " in " << PrintReg(LR.PhysReg, TRI));
+ DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI)
+ << " in " << printReg(LR.PhysReg, TRI));
const TargetRegisterClass &RC = *MRI->getRegClass(LRI->VirtReg);
int FI = getStackSpaceFor(LRI->VirtReg, RC);
DEBUG(dbgs() << " to stack slot #" << FI << "\n");
/// \returns spillImpossible when PhysReg or an alias can't be spilled.
unsigned RegAllocFast::calcSpillCost(MCPhysReg PhysReg) const {
if (isRegUsedInInstr(PhysReg)) {
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n");
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << " is already used in instr.\n");
return spillImpossible;
}
switch (unsigned VirtReg = PhysRegState[PhysReg]) {
case regFree:
return 0;
case regReserved:
- DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding "
- << PrintReg(PhysReg, TRI) << " is reserved already.\n");
+ DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding "
+ << printReg(PhysReg, TRI) << " is reserved already.\n");
return spillImpossible;
default: {
LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
}
// This is a disabled register, add up cost of aliases.
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n");
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n");
unsigned Cost = 0;
for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
MCPhysReg Alias = *AI;
/// proper container for VirtReg now. The physical register must not be used
/// for anything else when this is called.
void RegAllocFast::assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) {
- DEBUG(dbgs() << "Assigning " << PrintReg(LR.VirtReg, TRI) << " to "
- << PrintReg(PhysReg, TRI) << "\n");
+ DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to "
+ << printReg(PhysReg, TRI) << "\n");
PhysRegState[PhysReg] = LR.VirtReg;
assert(!LR.PhysReg && "Already assigned a physreg");
LR.PhysReg = PhysReg;
}
}
- DEBUG(dbgs() << "Allocating " << PrintReg(VirtReg) << " from "
+ DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from "
<< TRI->getRegClassName(&RC) << "\n");
unsigned BestReg = 0;
unsigned BestCost = spillImpossible;
for (MCPhysReg PhysReg : AO) {
unsigned Cost = calcSpillCost(PhysReg);
- DEBUG(dbgs() << "\tRegister: " << PrintReg(PhysReg, TRI) << "\n");
+ DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n");
DEBUG(dbgs() << "\tCost: " << Cost << "\n");
DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n");
// Cost is 0 when all aliases are already disabled.
LRI = allocVirtReg(MI, LRI, Hint);
const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
- DEBUG(dbgs() << "Reloading " << PrintReg(VirtReg, TRI) << " into "
- << PrintReg(LRI->PhysReg, TRI) << "\n");
+ DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
+ << printReg(LRI->PhysReg, TRI) << "\n");
TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, &RC, TRI);
++NumLoads;
} else if (LRI->Dirty) {
if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) ||
(MO.getSubReg() && MI.readsVirtualRegister(Reg))) {
if (ThroughRegs.insert(Reg).second)
- DEBUG(dbgs() << ' ' << PrintReg(Reg));
+ DEBUG(dbgs() << ' ' << printReg(Reg));
}
}
if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
unsigned Reg = MO.getReg();
if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
- DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI)
<< " as used in instr\n");
markRegUsedInInstr(Reg);
}
dbgs() << "*";
break;
default: {
- dbgs() << '=' << PrintReg(PhysRegState[Reg]);
+ dbgs() << '=' << printReg(PhysRegState[Reg]);
LiveRegMap::iterator I = findLiveVirtReg(PhysRegState[Reg]);
assert(I != LiveVirtRegs.end() && "Missing VirtReg entry");
if (I->Dirty)
// preferred register.
if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
if (Order.isHint(Hint)) {
- DEBUG(dbgs() << "missed hint " << PrintReg(Hint, TRI) << '\n');
+ DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n');
EvictionCost MaxCost;
MaxCost.setBrokenHints(1);
if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
if (!Cost)
return PhysReg;
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is available at cost " << Cost
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " << Cost
<< '\n');
unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
return CheapReg ? CheapReg : PhysReg;
}
if (PhysReg)
DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
- << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI)
+ << printReg(PrevReg, TRI) << " to " << printReg(PhysReg, TRI)
<< '\n');
return PhysReg;
}
if (!Cascade)
Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
- DEBUG(dbgs() << "evicting " << PrintReg(PhysReg, TRI)
+ DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
<< " interference: Cascade " << Cascade << '\n');
// Collect all interfering virtregs first.
// The first use of a callee-saved register in a function has cost 1.
// Don't start using a CSR when the CostPerUseLimit is low.
if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR "
- << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
+ << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
<< '\n');
continue;
}
SpillPlacer->prepare(Cand.LiveBundles);
BlockFrequency Cost;
if (!addSplitConstraints(Cand.Intf, Cost)) {
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tno positive bundles\n");
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
continue;
}
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << "\tstatic = ";
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = ";
MBFI->printBlockFreq(dbgs(), Cost));
if (Cost >= BestCost) {
DEBUG({
dbgs() << " worse than no bundles\n";
else
dbgs() << " worse than "
- << PrintReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
+ << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
});
continue;
}
// See splitCanCauseEvictionChain for detailed description of bad
// eviction chain scenarios.
DEBUG(dbgs() << "Best split candidate of vreg "
- << PrintReg(VirtReg.reg, TRI) << " may ");
+ << printReg(VirtReg.reg, TRI) << " may ");
if (!(*CanCauseEvictionChain))
DEBUG(dbgs() << "not ");
DEBUG(dbgs() << "cause bad eviction chain\n");
if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
UsedCands.push_back(BestCand);
Cand.IntvIdx = SE->openIntv();
- DEBUG(dbgs() << "Split for " << PrintReg(Cand.PhysReg, TRI) << " in "
+ DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
<< B << " bundles, intv " << Cand.IntvIdx << ".\n");
(void)B;
}
const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
- DEBUG(dbgs() << PrintReg(PhysReg, TRI) << ' '
+ DEBUG(dbgs() << printReg(PhysReg, TRI) << ' '
<< Uses[SplitBefore] << '-' << Uses[SplitAfter]
<< " i=" << MaxGap);
for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
if (IntvMap[i] == 1) {
setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
- DEBUG(dbgs() << PrintReg(LREdit.get(i)));
+ DEBUG(dbgs() << printReg(LREdit.get(i)));
}
DEBUG(dbgs() << '\n');
}
Order.rewind();
while (unsigned PhysReg = Order.next()) {
DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
- << PrintReg(PhysReg, TRI) << '\n');
+ << printReg(PhysReg, TRI) << '\n');
RecoloringCandidates.clear();
VirtRegToPhysReg.clear();
CurrentNewVRegs.clear();
}
DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
- << PrintReg(PhysReg, TRI) << '\n');
+ << printReg(PhysReg, TRI) << '\n');
// The recoloring attempt failed, undo the changes.
FixedRegisters = SaveFixedRegisters;
continue;
}
DEBUG(dbgs() << "Recoloring of " << *LI
- << " succeeded with: " << PrintReg(PhysReg, TRI) << '\n');
+ << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
Matrix->assign(*LI, PhysReg);
FixedRegisters.insert(LI->reg);
Visited.insert(Reg);
RecoloringCandidates.push_back(Reg);
- DEBUG(dbgs() << "Trying to reconcile hints for: " << PrintReg(Reg, TRI) << '('
- << PrintReg(PhysReg, TRI) << ")\n");
+ DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) << '('
+ << printReg(PhysReg, TRI) << ")\n");
do {
Reg = RecoloringCandidates.pop_back_val();
Matrix->checkInterference(LI, PhysReg)))
continue;
- DEBUG(dbgs() << PrintReg(Reg, TRI) << '(' << PrintReg(CurrPhys, TRI)
+ DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
<< ") is recolorable.\n");
// Gather the hint info.
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
(void)TRI;
- DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> SPILLED (Cost: "
+ DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: "
<< LRE.getParent().weight << ", New vregs: ");
// Copy any newly inserted live intervals into the list of regs to
I != E; ++I) {
const LiveInterval &LI = LIS.getInterval(*I);
assert(!LI.empty() && "Empty spill range.");
- DEBUG(dbgs() << PrintReg(LI.reg, &TRI) << " ");
+ DEBUG(dbgs() << printReg(LI.reg, &TRI) << " ");
VRegsToAlloc.insert(LI.reg);
}
if (AllocOption != PBQP::RegAlloc::getSpillOptionIdx()) {
unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1];
- DEBUG(dbgs() << "VREG " << PrintReg(VReg, &TRI) << " -> "
+ DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> "
<< TRI.getName(PReg) << "\n");
assert(PReg != 0 && "Invalid preg selected.");
VRM.assignVirt2Phys(VReg, PReg);
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
unsigned VReg = G.getNodeMetadata(NId).getVReg();
const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
- OS << NId << " (" << RegClassName << ':' << PrintReg(VReg, TRI) << ')';
+ OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')';
});
}
DEBUG({
dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
for (unsigned I = 0; I != RCI.NumRegs; ++I)
- dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
+ dbgs() << ' ' << printReg(RCI.Order[I], TRI);
dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
});
// in IntB, we can merge them.
if (ValS+1 != BS) return false;
- DEBUG(dbgs() << "Extending: " << PrintReg(IntB.reg, TRI));
+ DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI));
SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
// We are about to delete CopyMI, so need to remove it as the 'instruction
// Enforce policies.
if (CP.isPhys()) {
- DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), TRI)
- << " with " << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx())
+ DEBUG(dbgs() << "\tConsidering merging " << printReg(CP.getSrcReg(), TRI)
+ << " with " << printReg(CP.getDstReg(), TRI, CP.getSrcIdx())
<< '\n');
if (!canJoinPhys(CP)) {
// Before giving up coalescing, if definition of source is defined by
dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with ";
if (CP.getDstIdx() && CP.getSrcIdx())
- dbgs() << PrintReg(CP.getDstReg()) << " in "
+ dbgs() << printReg(CP.getDstReg()) << " in "
<< TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
- << PrintReg(CP.getSrcReg()) << " in "
+ << printReg(CP.getSrcReg()) << " in "
<< TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
else
- dbgs() << PrintReg(CP.getSrcReg(), TRI) << " in "
- << PrintReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
+ dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
+ << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
});
}
TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
DEBUG({
- dbgs() << "\tSuccess: " << PrintReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
- << " -> " << PrintReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
+ dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
+ << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = ";
if (CP.isPhys())
- dbgs() << PrintReg(CP.getDstReg(), TRI);
+ dbgs() << printReg(CP.getDstReg(), TRI);
else
dbgs() << LIS->getInterval(CP.getDstReg());
dbgs() << '\n';
return false;
}
if (RHS.overlaps(LIS->getRegUnit(*UI))) {
- DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
+ DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI) << '\n');
return false;
}
}
// We're going to remove the copy which defines a physical reserved
// register, so remove its valno, etc.
- DEBUG(dbgs() << "\t\tRemoving phys reg def of " << PrintReg(DstReg, TRI)
+ DEBUG(dbgs() << "\t\tRemoving phys reg def of " << printReg(DstReg, TRI)
<< " at " << CopyRegIdx << "\n");
LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
assert(V.OtherVNI && "OtherVNI not assigned, can't merge.");
assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion");
Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
- DEBUG(dbgs() << "\t\tmerge " << PrintReg(Reg) << ':' << ValNo << '@'
+ DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
<< LR.getValNumInfo(ValNo)->def << " into "
- << PrintReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
+ << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
<< V.OtherVNI->def << " --> @"
<< NewVNInfo[Assignments[ValNo]]->def << '\n');
break;
for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
computeAssignment(i, Other);
if (Vals[i].Resolution == CR_Impossible) {
- DEBUG(dbgs() << "\t\tinterference at " << PrintReg(Reg) << ':' << i
+ DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
<< '@' << LR.getValNumInfo(i)->def << '\n');
return false;
}
// lanes escape the block.
SlotIndex End = OtherI->end;
if (End >= MBBEnd) {
- DEBUG(dbgs() << "\t\ttaints global " << PrintReg(Other.Reg) << ':'
+ DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
<< OtherI->valno->id << '@' << OtherI->start << '\n');
return false;
}
- DEBUG(dbgs() << "\t\ttaints local " << PrintReg(Other.Reg) << ':'
+ DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
<< OtherI->valno->id << '@' << OtherI->start
<< " to " << End << '\n');
// A dead def is not a problem.
assert(V.Resolution != CR_Impossible && "Unresolvable conflict");
if (V.Resolution != CR_Unresolved)
continue;
- DEBUG(dbgs() << "\t\tconflict at " << PrintReg(Reg) << ':' << i
+ DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i
<< '@' << LR.getValNumInfo(i)->def << '\n');
if (SubRangeJoin)
return false;
if (!EraseImpDef)
EndPoints.push_back(Def);
}
- DEBUG(dbgs() << "\t\tpruned " << PrintReg(Other.Reg) << " at " << Def
+ DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
<< ": " << Other.LR << '\n');
break;
}
// computeAssignment(), the value that was originally copied could have
// been replaced.
LIS->pruneValue(LR, Def, &EndPoints);
- DEBUG(dbgs() << "\t\tpruned all of " << PrintReg(Reg) << " at "
+ DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
<< Def << ": " << LR << '\n');
}
break;
R.LaneMask = Mask;
}
}
- DEBUG(dbgs() << "\t\tLHST = " << PrintReg(CP.getDstReg())
+ DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg())
<< ' ' << LHS << '\n');
// Determine lanemasks of RHS in the coalesced register and merge subranges.
continue;
// Check that OtherReg interfere with DstReg.
if (LIS->getInterval(OtherReg).overlaps(DstLI)) {
- DEBUG(dbgs() << "Apply terminal rule for: " << PrintReg(DstReg) << '\n');
+ DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg) << '\n');
return true;
}
}
if (MRI->reg_nodbg_empty(Reg))
continue;
if (MRI->recomputeRegClass(Reg)) {
- DEBUG(dbgs() << PrintReg(Reg) << " inflated to "
+ DEBUG(dbgs() << printReg(Reg) << " inflated to "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n');
++NumInflated;
dumpRegSetPressure(MaxSetPressure, TRI);
dbgs() << "Live In: ";
for (const RegisterMaskPair &P : LiveInRegs) {
- dbgs() << PrintVRegOrUnit(P.RegUnit, TRI);
+ dbgs() << printVRegOrUnit(P.RegUnit, TRI);
if (!P.LaneMask.all())
dbgs() << ':' << PrintLaneMask(P.LaneMask);
dbgs() << ' ';
dbgs() << '\n';
dbgs() << "Live Out: ";
for (const RegisterMaskPair &P : LiveOutRegs) {
- dbgs() << PrintVRegOrUnit(P.RegUnit, TRI);
+ dbgs() << printVRegOrUnit(P.RegUnit, TRI);
if (!P.LaneMask.all())
dbgs() << ':' << PrintLaneMask(P.LaneMask);
dbgs() << ' ';
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
Scavenged.Restore = &*std::prev(SpillBefore);
LiveUnits.removeReg(Reg);
- DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
<< " until " << *SpillBefore);
} else {
- DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n');
+ DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) << '\n');
}
return Reg;
}
const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
SmallVector<LiveInterval*, 4> Intervals;
Intervals.push_back(&LI);
- DEBUG(dbgs() << PrintReg(Reg) << ": Found " << Classes.getNumClasses()
+ DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses()
<< " equivalence classes.\n");
- DEBUG(dbgs() << PrintReg(Reg) << ": Splitting into newly created:");
+ DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
++I) {
unsigned NewVReg = MRI->createVirtualRegister(RegClass);
LiveInterval &NewLI = LIS->createEmptyInterval(NewVReg);
Intervals.push_back(&NewLI);
- DEBUG(dbgs() << ' ' << PrintReg(NewVReg));
+ DEBUG(dbgs() << ' ' << printReg(NewVReg));
}
DEBUG(dbgs() << '\n');
case Data:
OS << " Latency=" << getLatency();
if (TRI && isAssignedRegDep())
- OS << " Reg=" << PrintReg(getReg(), TRI);
+ OS << " Reg=" << printReg(getReg(), TRI);
break;
case Anti:
case Output:
OS << LBB->getName() << " ";
OS << (const void*)BBDN->getBasicBlock() << ">";
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
- OS << ' ' << PrintReg(R->getReg(),
+ OS << ' ' << printReg(R->getReg(),
G ? G->getSubtarget().getRegisterInfo() : nullptr);
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(this)) {
// The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx
- << '(' << PrintReg(Edit->get(RegIdx)) << ')');
+ << '(' << printReg(Edit->get(RegIdx)) << ')');
LiveInterval &LI = LIS.getInterval(Edit->get(RegIdx));
// Check for a simply defined value that can be blitted directly.
continue;
for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
- dbgs() << "Error: Super register " << PrintReg(*SR, this)
- << " of reserved register " << PrintReg(Reg, this)
+ dbgs() << "Error: Super register " << printReg(*SR, this)
+ << " of reserved register " << printReg(Reg, this)
<< " is not reserved.\n";
return false;
}
namespace llvm {
-Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
+Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
unsigned SubIdx) {
return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
if (!Reg)
});
}
-Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
// Generic printout when TRI is missing.
if (!TRI) {
});
}
-Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
+Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
return Printable([Unit, TRI](raw_ostream &OS) {
if (TRI && TRI->isVirtualRegister(Unit)) {
OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
} else {
- OS << PrintRegUnit(Unit, TRI);
+ OS << printRegUnit(Unit, TRI);
}
});
}
LLVM_DUMP_METHOD
void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
const TargetRegisterInfo *TRI) {
- dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
+ dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
}
#endif
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
- OS << '[' << PrintReg(Reg, TRI) << " -> "
- << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
+ OS << '[' << printReg(Reg, TRI) << " -> "
+ << printReg(Virt2PhysMap[Reg], TRI) << "] "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
}
}
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
- OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
+ OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
<< "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
}
}
if (TagMap.count(NewTag))
continue;
- DEBUG(dbgs() << "Changing base reg to: " << PrintReg(ScratchReg, TRI)
+ DEBUG(dbgs() << "Changing base reg to: " << printReg(ScratchReg, TRI)
<< '\n');
// Rewrite:
// well to update the real base register.
if (LdI.IsPrePost) {
DEBUG(dbgs() << "Doing post MOV of incremented reg: "
- << PrintReg(ScratchReg, TRI) << '\n');
+ << printReg(ScratchReg, TRI) << '\n');
MI.getOperand(0).setReg(
ScratchReg); // Change tied operand pre/post update dest.
BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL,
DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";
for (unsigned Reg : SavedRegs.set_bits())
- dbgs() << ' ' << PrintReg(Reg, RegInfo);
+ dbgs() << ' ' << printReg(Reg, RegInfo);
dbgs() << "\n";);
// If any callee-saved registers are used, the frame cannot be eliminated.
// here.
if (BigStack) {
if (!ExtraCSSpill && UnspilledCSGPR != AArch64::NoRegister) {
- DEBUG(dbgs() << "Spilling " << PrintReg(UnspilledCSGPR, RegInfo)
+ DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
<< " to get a scratch register.\n");
SavedRegs.set(UnspilledCSGPR);
// MachO's compact unwind format relies on all registers being stored in
// Do some Chain management
if (Chains.count(Ra)) {
if (Rd != Ra) {
- DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to "
- << PrintReg(Rd, TRI) << '\n';);
+ DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) << " to "
+ << printReg(Rd, TRI) << '\n';);
Chains.remove(Ra);
Chains.insert(Rd);
}
} else {
- DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI)
+ DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI)
<< '\n';);
Chains.insert(Rd);
}
for (auto r : Chains) {
SmallVector<unsigned, 8> toDel;
if(regJustKilledBefore(LIs, r, MI)) {
- DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at ";
+ DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at ";
MI.print(dbgs()););
toDel.push_back(r);
}
}
if (isRegister())
- OS << "Reg " << PrintReg(getRegister(), TRI) << '\n';
+ OS << "Reg " << printReg(getRegister(), TRI) << '\n';
else
OS << "Stack offset " << getStackOffset() << '\n';
}
dbgs() << "=PHIInfo Start=\n";
for (auto PII : this->PHIInfo) {
PHIInfoElementT &Element = *PII;
- dbgs() << "Dest: " << PrintReg(Element.DestReg, TRI)
+ dbgs() << "Dest: " << printReg(Element.DestReg, TRI)
<< " Sources: {";
for (auto &SI : Element.Sources) {
- dbgs() << PrintReg(SI.first, TRI) << "(BB#"
+ dbgs() << printReg(SI.first, TRI) << "(BB#"
<< SI.second->getNumber() << "),";
}
dbgs() << "}\n";
void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
dumpDepth(depth);
dbgs() << "MBB: " << getMBB()->getNumber();
- dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI);
- dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n";
+ dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
+ dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
}
};
void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
dumpDepth(depth);
dbgs() << "Region: " << (void *)Region;
- dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI);
- dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n";
+ dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
+ dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
dumpDepth(depth);
if (getSucc())
const TargetRegisterInfo *TRI,
PHILinearize &PHIInfo) {
if (TRI->isVirtualRegister(Reg)) {
- DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n");
+ DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n");
// If this is a source register to a PHI we are chaining, it
// must be live out.
if (PHIInfo.isSource(Reg)) {
- DEBUG(dbgs() << "Add LiveOut (PHI): " << PrintReg(Reg, TRI) << "\n");
+ DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg);
} else {
// If this is live out of the MBB
for (auto &UI : MRI->use_operands(Reg)) {
if (UI.getParent()->getParent() != MBB) {
DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber()
- << "): " << PrintReg(Reg, TRI) << "\n");
+ << "): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg);
} else {
// If the use is in the same MBB we have to make sure
MIE = UseInstr->getParent()->instr_end();
MII != MIE; ++MII) {
if ((&(*MII)) == DefInstr) {
- DEBUG(dbgs() << "Add LiveOut (Loop): " << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI)
<< "\n");
addLiveOut(Reg);
}
const TargetRegisterInfo *TRI,
PHILinearize &PHIInfo) {
if (TRI->isVirtualRegister(Reg)) {
- DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n");
+ DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) << "\n");
for (auto &UI : MRI->use_operands(Reg)) {
if (!Region->contains(UI.getParent()->getParent())) {
DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Region
- << "): " << PrintReg(Reg, TRI) << "\n");
+ << "): " << printReg(Reg, TRI) << "\n");
addLiveOut(Reg);
}
}
unsigned PHIReg = getPHISourceReg(PHI, i);
DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber()
<< " -> BB#" << (*SI)->getNumber()
- << "): " << PrintReg(PHIReg, TRI) << "\n");
+ << "): " << printReg(PHIReg, TRI) << "\n");
addLiveOut(PHIReg);
}
}
if (Region->contains(getPHIPred(PHI, i))) {
unsigned PHIReg = getPHISourceReg(PHI, i);
DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Region
- << "): " << PrintReg(PHIReg, TRI) << "\n");
+ << "): " << printReg(PHIReg, TRI) << "\n");
addLiveOut(PHIReg);
}
}
}
OS << "} (" << Entry->getNumber() << ", "
<< (Exit == nullptr ? -1 : Exit->getNumber())
- << "): In:" << PrintReg(getBBSelectRegIn(), TRI)
- << " Out:" << PrintReg(getBBSelectRegOut(), TRI) << " {";
+ << "): In:" << printReg(getBBSelectRegIn(), TRI)
+ << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {";
for (auto &LI : LiveOuts) {
- OS << PrintReg(LI, TRI) << " ";
+ OS << printReg(LI, TRI) << " ";
}
OS << "} \n";
}
assert(Register != NewRegister && "Cannot replace a reg with itself");
DEBUG(dbgs() << "Pepareing to replace register (region): "
- << PrintReg(Register, MRI->getTargetRegisterInfo()) << " with "
- << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
+ << printReg(Register, MRI->getTargetRegisterInfo()) << " with "
+ << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
// If we are replacing outside, we also need to update the LiveOuts
if (ReplaceOutside &&
if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) {
DEBUG(dbgs() << "Trying to substitute physical register: "
- << PrintReg(NewRegister, MRI->getTargetRegisterInfo())
+ << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n");
llvm_unreachable("Cannot substitute physical registers");
} else {
DEBUG(dbgs() << "Replacing register (region): "
- << PrintReg(Register, MRI->getTargetRegisterInfo())
+ << printReg(Register, MRI->getTargetRegisterInfo())
<< " with "
- << PrintReg(NewRegister, MRI->getTargetRegisterInfo())
+ << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n");
O.setReg(NewRegister);
}
continue;
if (!MRI->hasOneDef(Reg)) {
DEBUG(this->getEntry()->getParent()->dump());
- DEBUG(dbgs() << PrintReg(Reg, TRI) << "\n");
+ DEBUG(dbgs() << printReg(Reg, TRI) << "\n");
}
if (MRI->def_begin(Reg) == MRI->def_end()) {
DEBUG(dbgs() << "Register "
- << PrintReg(Reg, MRI->getTargetRegisterInfo())
+ << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has NO defs\n");
} else if (!MRI->hasOneDef(Reg)) {
DEBUG(dbgs() << "Register "
- << PrintReg(Reg, MRI->getTargetRegisterInfo())
+ << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has multiple defs\n");
}
bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
if (UseIsOutsideDefMBB && UseOperand->isKill()) {
DEBUG(dbgs() << "Removing kill flag on register: "
- << PrintReg(Reg, TRI) << "\n");
+ << printReg(Reg, TRI) << "\n");
UseOperand->setIsKill(false);
}
}
unsigned *ReplaceReg) {
DEBUG(dbgs() << "Shrink PHI: ");
DEBUG(PHI.dump());
- DEBUG(dbgs() << " to " << PrintReg(getPHIDestReg(PHI), TRI)
+ DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI)
<< "<def> = PHI(");
bool Replaced = false;
if (SourceMBB) {
MIB.addReg(CombinedSourceReg);
MIB.addMBB(SourceMBB);
- DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< SourceMBB->getNumber());
}
MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg);
MIB.addMBB(SourcePred);
- DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber());
}
DEBUG(dbgs() << ")\n");
SmallVector<unsigned, 2> &PHIRegionIndices) {
DEBUG(dbgs() << "Replace PHI: ");
DEBUG(PHI.dump());
- DEBUG(dbgs() << " with " << PrintReg(getPHIDestReg(PHI), TRI)
+ DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI)
<< "<def> = PHI(");
bool HasExternalEdge = false;
getPHIDestReg(PHI));
MIB.addReg(CombinedSourceReg);
MIB.addMBB(LastMerge);
- DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< LastMerge->getNumber());
for (unsigned i = 0; i < NumInputs; ++i) {
if (isPHIRegionIndex(PHIRegionIndices, i)) {
MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg);
MIB.addMBB(SourcePred);
- DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber());
}
DEBUG(dbgs() << ")\n");
if (NumNonRegionInputs == 0) {
auto DestReg = getPHIDestReg(PHI);
replaceRegisterWith(DestReg, CombinedSourceReg);
- DEBUG(dbgs() << " register " << PrintReg(CombinedSourceReg, TRI) << "\n");
+ DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI) << "\n");
PHI.eraseFromParent();
} else {
- DEBUG(dbgs() << PrintReg(getPHIDestReg(PHI), TRI) << "<def> = PHI(");
+ DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << "<def> = PHI(");
MachineBasicBlock *MBB = PHI.getParent();
MachineInstrBuilder MIB =
BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
getPHIDestReg(PHI));
MIB.addReg(CombinedSourceReg);
MIB.addMBB(IfMBB);
- DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", BB#"
<< IfMBB->getNumber());
unsigned NumInputs = getPHINumInputs(PHI);
for (unsigned i = 0; i < NumInputs; ++i) {
MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
MIB.addReg(SourceReg);
MIB.addMBB(SourcePred);
- DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< SourcePred->getNumber());
}
DEBUG(dbgs() << ")\n");
}
}
- DEBUG(dbgs() << "Register " << PrintReg(Reg, TRI) << " is "
+ DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is "
<< (IsDead ? "dead" : "alive") << " after PHI replace\n");
if (IsDead) {
LRegion->removeLiveOut(Reg);
return;
}
DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber()
- << "): " << PrintReg(DestRegister, TRI) << "<def> = PHI("
- << PrintReg(IfSourceRegister, TRI) << ", BB#"
- << IfBB->getNumber() << PrintReg(CodeSourceRegister, TRI)
+ << "): " << printReg(DestRegister, TRI) << "<def> = PHI("
+ << printReg(IfSourceRegister, TRI) << ", BB#"
+ << IfBB->getNumber() << printReg(CodeSourceRegister, TRI)
<< ", BB#" << CodeBB->getNumber() << ")\n");
const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin());
MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL,
MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) {
if (MRI->def_begin(Reg) == MRI->def_end()) {
- DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo())
+ DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has NO defs\n");
} else if (!MRI->hasOneDef(Reg)) {
- DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo())
+ DEBUG(dbgs() << "Register " << printReg(Reg, MRI->getTargetRegisterInfo())
<< " has multiple defs\n");
DEBUG(dbgs() << "DEFS BEGIN:\n");
for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) {
}
for (auto LI : OldLiveOuts) {
- DEBUG(dbgs() << "LiveOut: " << PrintReg(LI, TRI));
+ DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI));
if (!containsDef(CodeBB, InnerRegion, LI) ||
(!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) {
// If the register simly lives through the CodeBB, we don't have
unsigned IfSourceReg = MRI->createVirtualRegister(RegClass);
// Create initializer, this value is never used, but is needed
// to satisfy SSA.
- DEBUG(dbgs() << "Initializer for reg: " << PrintReg(Reg) << "\n");
+ DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n");
TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(),
IfSourceReg, 0);
const DebugLoc &DL = Entry->findDebugLoc(Entry->begin());
MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL,
TII->get(TargetOpcode::PHI), DestReg);
- DEBUG(dbgs() << "Entry PHI " << PrintReg(DestReg, TRI) << "<def> = PHI(");
+ DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << "<def> = PHI(");
unsigned CurrentBackedgeReg = 0;
BackedgePHI.addMBB((*SRI).second);
CurrentBackedgeReg = NewBackedgeReg;
DEBUG(dbgs() << "Inserting backedge PHI: "
- << PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
- << PrintReg(CurrentBackedgeReg, TRI) << ", BB#"
+ << printReg(NewBackedgeReg, TRI) << "<def> = PHI("
+ << printReg(CurrentBackedgeReg, TRI) << ", BB#"
<< getPHIPred(*PHIDefInstr, 0)->getNumber() << ", "
- << PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI)
+ << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI)
<< ", BB#" << (*SRI).second->getNumber());
}
} else {
MIB.addReg(SourceReg);
MIB.addMBB((*SRI).second);
- DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(SourceReg, TRI) << ", BB#"
<< (*SRI).second->getNumber() << ", ");
}
}
if (CurrentBackedgeReg != 0) {
MIB.addReg(CurrentBackedgeReg);
MIB.addMBB(Exit);
- DEBUG(dbgs() << PrintReg(CurrentBackedgeReg, TRI) << ", BB#"
+ DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", BB#"
<< Exit->getNumber() << ")\n");
} else {
DEBUG(dbgs() << ")\n");
++I;
if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) {
DEBUG(dbgs() << "Trying to substitute physical register: "
- << PrintReg(NewRegister, MRI->getTargetRegisterInfo())
+ << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n");
llvm_unreachable("Cannot substitute physical registers");
// We don't handle physical registers, but if we need to
// O.substPhysReg(NewRegister, *TRI);
} else {
DEBUG(dbgs() << "Replacing register: "
- << PrintReg(Register, MRI->getTargetRegisterInfo())
+ << printReg(Register, MRI->getTargetRegisterInfo())
<< " with "
- << PrintReg(NewRegister, MRI->getTargetRegisterInfo())
+ << printReg(NewRegister, MRI->getTargetRegisterInfo())
<< "\n");
O.setReg(NewRegister);
}
for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
++DRI) {
unsigned DestReg = *DRI;
- DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) << "\n");
+ DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n");
auto SRI = PHIInfo.sources_begin(DestReg);
unsigned SourceReg = (*SRI).first;
- DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI)
- << " SourceReg: " << PrintReg(SourceReg, TRI) << "\n");
+ DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI)
+ << " SourceReg: " << printReg(SourceReg, TRI) << "\n");
assert(PHIInfo.sources_end(DestReg) == ++SRI &&
"More than one phi source in entry node");
MachineInstrBuilder MIB =
BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(),
TII->get(TargetOpcode::PHI), NewDestReg);
- DEBUG(dbgs() << "Split Entry PHI " << PrintReg(NewDestReg, TRI)
+ DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI)
<< "<def> = PHI(");
MIB.addReg(PHISource);
MIB.addMBB(Entry);
- DEBUG(dbgs() << PrintReg(PHISource, TRI) << ", BB#" << Entry->getNumber());
+ DEBUG(dbgs() << printReg(PHISource, TRI) << ", BB#" << Entry->getNumber());
MIB.addReg(RegionSourceReg);
MIB.addMBB(RegionSourceMBB);
- DEBUG(dbgs() << " ," << PrintReg(RegionSourceReg, TRI) << ", BB#"
+ DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", BB#"
<< RegionSourceMBB->getNumber() << ")\n");
}
BBSelectRegOut = Child->getBBSelectRegOut();
BBSelectRegIn = Child->getBBSelectRegIn();
- DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI)
+ DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
<< "\n");
- DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI)
+ DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
<< "\n");
MachineBasicBlock *IfEnd = CurrentMerge;
BBSelectRegOut = Child->getBBSelectRegOut();
BBSelectRegIn = Child->getBBSelectRegIn();
- DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI)
+ DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
<< "\n");
- DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI)
+ DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
<< "\n");
MachineBasicBlock *IfEnd = CurrentMerge;
LinearizedRegion *LRegion = new LinearizedRegion();
if (SelectOut) {
LRegion->addLiveOut(SelectOut);
- DEBUG(dbgs() << "Add LiveOut (BBSelect): " << PrintReg(SelectOut, TRI)
+ DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI)
<< "\n");
}
LRegion->setRegionMRT(Region);
for (const auto &S : LI.subranges()) {
if (!S.liveAt(SI)) continue;
if (firstTime) {
- dbgs() << " " << PrintReg(Reg, MRI.getTargetRegisterInfo())
+ dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
<< '\n';
firstTime = false;
}
for (auto const &P : TrackedLR) {
auto I = LISLR.find(P.first);
if (I == LISLR.end()) {
- dbgs() << " " << PrintReg(P.first, TRI)
+ dbgs() << " " << printReg(P.first, TRI)
<< ":L" << PrintLaneMask(P.second)
<< " isn't found in LIS reported set\n";
}
else if (I->second != P.second) {
- dbgs() << " " << PrintReg(P.first, TRI)
+ dbgs() << " " << printReg(P.first, TRI)
<< " masks doesn't match: LIS reported "
<< PrintLaneMask(I->second)
<< ", tracked "
for (auto const &P : LISLR) {
auto I = TrackedLR.find(P.first);
if (I == TrackedLR.end()) {
- dbgs() << " " << PrintReg(P.first, TRI)
+ dbgs() << " " << printReg(P.first, TRI)
<< ":L" << PrintLaneMask(P.second)
<< " isn't found in tracked set\n";
}
unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
auto It = LiveRegs.find(Reg);
if (It != LiveRegs.end() && It->second.any())
- OS << ' ' << PrintVRegOrUnit(Reg, TRI) << ':'
+ OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
<< PrintLaneMask(It->second);
}
OS << '\n';
<< LiveOutPressure[DAG->getVGPRSetID()] << "\n\n";
dbgs() << "LiveIns:\n";
for (unsigned Reg : LiveInRegs)
- dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
+ dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
dbgs() << "\nLiveOuts:\n";
for (unsigned Reg : LiveOutRegs)
- dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
+ dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
}
dbgs() << "\nInstructions:\n";
dbgs() << Block->getID() << ' ';
dbgs() << "\nCurrent Live:\n";
for (unsigned Reg : LiveRegs)
- dbgs() << PrintVRegOrUnit(Reg, DAG->getTRI()) << ' ';
+ dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
dbgs() << '\n';
dbgs() << "Current VGPRs: " << VregCurrentUsage << '\n';
dbgs() << "Current SGPRs: " << SregCurrentUsage << '\n';
if (J->modifiesRegister(CopyToExec, TRI)) {
if (SaveExecInst) {
DEBUG(dbgs() << "Multiple instructions modify "
- << PrintReg(CopyToExec, TRI) << '\n');
+ << printReg(CopyToExec, TRI) << '\n');
SaveExecInst = nullptr;
break;
}
"Only support 4-byte stores to stack now.");
assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
"Only support GPR32 stores to stack now.");
- DEBUG(dbgs() << "Created store reg=" << PrintReg(SrcReg, TRI)
+ DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)
<< " to FrameIndex=" << FrameIndex << "\n");
BuildMI(MBB, I, dl, get(ARC::ST_rs9))
.addReg(SrcReg, getKillRegState(isKill))
"Only support 4-byte loads from stack now.");
assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&
"Only support GPR32 stores to stack now.");
- DEBUG(dbgs() << "Created load reg=" << PrintReg(DestReg, TRI)
+ DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI)
<< " from FrameIndex=" << FrameIndex << "\n");
BuildMI(MBB, I, dl, get(ARC::LD_rs9))
.addReg(DestReg, RegState::Define)
MBB.getParent()->getSubtarget().getRegisterInfo();
BaseReg = RS->scavengeRegister(&ARC::GPR32RegClass, II, SPAdj);
assert(BaseReg && "Register scavenging failed.");
- DEBUG(dbgs() << "Scavenged register " << PrintReg(BaseReg, TRI)
- << " for FrameReg=" << PrintReg(FrameReg, TRI)
+ DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
+ << " for FrameReg=" << printReg(FrameReg, TRI)
<< "+Offset=" << Offset << "\n");
(void)TRI;
RS->setRegUsed(BaseReg);
MRI->getRegClass(MI->getOperand(1).getReg());
if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
DEBUG(dbgs() << "Subreg copy is compatible - returning ");
- DEBUG(dbgs() << PrintReg(FullReg) << "\n");
+ DEBUG(dbgs() << printReg(FullReg) << "\n");
eraseInstrWithNoUses(MI);
return FullReg;
}
DEBUG(dbgs() << "Replacing operand "
<< **I << " with "
- << PrintReg(NewReg) << "\n");
+ << printReg(NewReg) << "\n");
(*I)->substVirtReg(NewReg, 0, *TRI);
}
}
for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
if (!MF.getRegInfo().isLiveIn(Reg)) {
--EntryRegDeficit;
- DEBUG(dbgs() << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << printReg(Reg, TRI)
<< " is unused argument register, EntryRegDeficit = "
<< EntryRegDeficit << "\n");
}
for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
if (SavedRegs.test(Reg)) {
--RegDeficit;
- DEBUG(dbgs() << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << printReg(Reg, TRI)
<< " is saved low register, RegDeficit = " << RegDeficit
<< "\n");
} else {
AvailableRegs.push_back(Reg);
DEBUG(dbgs()
- << PrintReg(Reg, TRI)
+ << printReg(Reg, TRI)
<< " is non-saved low register, adding to AvailableRegs\n");
}
}
for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
if (SavedRegs.test(Reg)) {
++RegDeficit;
- DEBUG(dbgs() << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << printReg(Reg, TRI)
<< " is saved high register, RegDeficit = " << RegDeficit
<< "\n");
}
DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {
unsigned Reg = AvailableRegs.pop_back_val();
- DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
<< " to make up reg deficit\n");
SavedRegs.set(Reg);
NumGPRSpills++;
(STI.isTargetWindows() && Reg == ARM::R11) ||
isARMLowRegister(Reg) || Reg == ARM::LR) {
SavedRegs.set(Reg);
- DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
<< " to make up alignment\n");
if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
ExtraCSSpill = true;
} else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
unsigned Reg = UnspilledCS2GPRs.front();
SavedRegs.set(Reg);
- DEBUG(dbgs() << "Spilling " << PrintReg(Reg, TRI)
+ DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
<< " to make up alignment\n");
if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
ExtraCSSpill = true;
void BitTracker::print_cells(raw_ostream &OS) const {
for (const std::pair<unsigned, RegisterCell> P : Map)
- dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
+ dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
}
BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F)
RegisterRef RU = PI.getOperand(i);
RegisterCell ResC = ME.getCell(RU, Map);
if (Trace)
- dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
+ dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
<< " cell: " << ResC << "\n";
Changed |= DefC.meet(ResC, DefRR.Reg);
}
if (Changed) {
if (Trace)
- dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
+ dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
<< " cell: " << DefC << "\n";
ME.putCell(DefRR, DefC, Map);
visitUsesOf(DefRR.Reg);
if (!MO.isReg() || !MO.isUse())
continue;
RegisterRef RU(MO);
- dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
+ dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
<< " cell: " << ME.getCell(RU, Map) << "\n";
}
dbgs() << "Outputs:\n";
for (const std::pair<unsigned, RegisterCell> &P : ResMap) {
RegisterRef RD(P.first);
- dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: "
+ dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "
<< ME.getCell(RD, ResMap) << "\n";
}
}
void BT::visitUsesOf(unsigned Reg) {
if (Trace)
- dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
+ dbgs() << "visiting uses of " << printReg(Reg, &ME.TRI) << "\n";
for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) {
if (!InstrExec.count(&UseI))
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
- OS << ' ' << PrintReg(R, P.TRI);
+ OS << ' ' << printReg(R, P.TRI);
OS << " }";
return OS;
}
return false;
DEBUG({
- dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub)
+ dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
<< ", MI: " << *MI;
dbgs() << "Cell: " << RC << '\n';
dbgs() << "Expected bitfield size: " << Len << " bits, "
DEBUG({
dbgs() << "Phis: {";
for (auto &I : Phis) {
- dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi("
- << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
- << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
+ dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
+ << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
+ << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
<< I.LB->getNumber() << ')';
}
dbgs() << " }\n";
for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
InstrGroup &G = Groups[i];
dbgs() << "Group[" << i << "] inp: "
- << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)
- << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
+ << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
+ << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
for (unsigned j = 0, m = G.Ins.size(); j < m; ++j)
dbgs() << " " << *G.Ins[j];
}
break;
}
#ifndef NDEBUG
- dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class "
+ dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
<< TRI.getRegClassName(&RC) << '\n';
#endif
llvm_unreachable("Unexpected register/subregister");
const HexagonBlockRanges::PrintRangeMap &P) {
for (auto &I : P.Map) {
const HexagonBlockRanges::RangeList &RL = I.second;
- OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
+ OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
}
return OS;
}
LLVM_ATTRIBUTE_UNUSED
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) {
if (P.Rs.Reg != 0)
- OS << PrintReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
+ OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
else
OS << "noreg";
return OS;
raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) {
OS << "## " << (P.Ex.Neg ? "- " : "+ ");
if (P.Ex.Rs.Reg != 0)
- OS << PrintReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
+ OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
else
OS << "__";
OS << " << " << P.Ex.S;
const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
OS << "bb#" << MBB.getNumber() << ": ";
if (ED.Rd.Reg != 0)
- OS << PrintReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
+ OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
else
OS << "__";
OS << " = " << PrintExpr(ED.Expr, HRI);
: Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
void print(const TargetRegisterInfo *TRI = nullptr) const {
- dbgs() << PrintReg(Reg, TRI, SubReg);
+ dbgs() << printReg(Reg, TRI, SubReg);
}
bool operator== (const Register &R) const {
void MachineConstPropagator::CellMap::print(raw_ostream &os,
const TargetRegisterInfo &TRI) const {
for (auto &I : Map)
- dbgs() << " " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n';
+ dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
}
#endif
LatticeCell SrcC;
bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
DEBUG(dbgs() << " edge from BB#" << PBN << ": "
- << PrintReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
+ << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
<< SrcC << '\n');
Changed |= Eval ? DefC.meet(SrcC)
: DefC.setBottom();
}
void MachineConstPropagator::visitUsesOf(unsigned Reg) {
- DEBUG(dbgs() << "Visiting uses of " << PrintReg(Reg, &MCE.TRI)
+ DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
<< Cells.get(Reg) << '\n');
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
// Do not process non-executable instructions. They can become exceutable
HasUse = true;
// PHIs can legitimately have "top" cells after propagation.
if (!MI.isPHI() && !Inputs.has(R.Reg)) {
- dbgs() << "Top " << PrintReg(R.Reg, &HRI, R.SubReg)
+ dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
<< " in MI: " << MI;
continue;
}
if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue;
unsigned R = MO.getReg();
- dbgs() << PrintReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
+ dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
}
}
}
const PrintFP &P) LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) {
OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
- << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
+ << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
<< ", TrueB:" << PrintMB(P.FP.TrueB)
<< ", FalseB:" << PrintMB(P.FP.FalseB)
<< ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
DEBUG(dbgs() << "compatible registers: ("
<< (Overlap ? "overlap" : "disjoint") << ")\n "
- << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
- << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
+ << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
+ << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
if (R1.Sub || R2.Sub)
return false;
if (Overlap)
dbgs() << '{';
for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
unsigned R = x;
- dbgs() << ' ' << PrintReg(R, &TRI);
+ dbgs() << ' ' << printReg(R, &TRI);
}
dbgs() << " }";
}
DEBUG(dbgs() << "Initial CS registers: {");
for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
unsigned R = CSI[i].getReg();
- DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
+ DEBUG(dbgs() << ' ' << printReg(R, TRI));
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
SRegs[*SR] = true;
}
for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
int FI = CSI[i].getFrameIdx();
int Off = MFI.getObjectOffset(FI);
- dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
+ dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
if (Off >= 0)
dbgs() << '+';
dbgs() << Off;
bool MissedReg = false;
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
unsigned R = x;
- dbgs() << PrintReg(R, TRI) << ' ';
+ dbgs() << printReg(R, TRI) << ' ';
MissedReg = true;
}
if (MissedReg)
auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
// The this-> is needed to unconfuse MSVC.
unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
- DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n');
+ DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n');
if (FoundR == 0)
continue;
#ifndef NDEBUG
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
- OS << ' ' << PrintReg(R, P.TRI);
+ OS << ' ' << printReg(R, P.TRI);
OS << " }";
return OS;
}
for (OrderedRegisterList::const_iterator I = B; I != E; ++I) {
if (I != B)
OS << ", ";
- OS << PrintReg(*I, P.TRI);
+ OS << printReg(*I, P.TRI);
}
OS << ')';
return OS;
raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) {
unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;
- OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI)
+ OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
<< ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')';
return OS;
}
using iterator = IFMapType::const_iterator;
for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- dbgs() << " " << PrintReg(I->first, HRI) << ":\n";
+ dbgs() << " " << printReg(I->first, HRI) << ":\n";
const IFListType &LL = I->second;
for (unsigned i = 0, n = LL.size(); i < n; ++i)
dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
OrderedRegisterList &AVs) {
if (isDebug()) {
- dbgs() << __func__ << ": " << PrintReg(VR, HRI)
+ dbgs() << __func__ << ": " << printReg(VR, HRI)
<< " AVs: " << PrintORL(AVs, HRI) << "\n";
}
if (AVs.size() == 0)
}
if (isDebug()) {
- dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n";
+ dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) {
dbgs() << " L=" << I->first << ':';
const RSListType &LL = I->second;
for (unsigned i = 0, n = LL.size(); i < n; ++i)
- dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@"
+ dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
<< LL[i].second << ')';
dbgs() << '\n';
}
if (!isValidInsertForm(VR, SrcR, InsR, L, S))
continue;
if (isDebug()) {
- dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI)
- << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#"
+ dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
+ << ',' << printReg(InsR, HRI) << ",#" << L << ",#"
<< S << ")\n";
}
IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet());
for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end();
I != E; ++I) {
unsigned VR = I->first, Pos = I->second;
- dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n";
+ dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
}
}
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
- return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
+ return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
}
class HexagonGenPredicate : public MachineFunctionPass {
void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
DEBUG(dbgs() << __func__ << ": "
- << PrintReg(Reg.R, TRI, Reg.S) << "\n");
+ << printReg(Reg.R, TRI, Reg.S) << "\n");
using use_iterator = MachineRegisterInfo::use_iterator;
use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
if (I == E) {
- DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n');
+ DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
MachineInstr *DefI = MRI->getVRegDef(Reg.R);
DefI->eraseFromParent();
return;
}
void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
- if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
+ if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
if (isImm()) { OS << Contents.ImmVal; }
}
};
#ifndef NDEBUG
// Show the invalid registers to ease debugging.
dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
- << ": " << PrintReg(DestReg, &HRI)
- << " = " << PrintReg(SrcReg, &HRI) << '\n';
+ << ": " << printReg(DestReg, &HRI)
+ << " = " << printReg(SrcReg, &HRI) << '\n';
#endif
llvm_unreachable("Unimplemented");
}
const USet &Part, const TargetRegisterInfo &TRI) {
dbgs() << '{';
for (auto I : Part)
- dbgs() << ' ' << PrintReg(I, &TRI);
+ dbgs() << ' ' << printReg(I, &TRI);
dbgs() << " }";
}
#endif
if (FixedRegs[x])
continue;
unsigned R = TargetRegisterInfo::index2VirtReg(x);
- DEBUG(dbgs() << PrintReg(R, TRI) << " ~~");
+ DEBUG(dbgs() << printReg(R, TRI) << " ~~");
USet &Asc = AssocMap[R];
for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
U != Z; ++U) {
unsigned u = TargetRegisterInfo::virtReg2Index(T);
if (FixedRegs[u])
continue;
- DEBUG(dbgs() << ' ' << PrintReg(T, TRI));
+ DEBUG(dbgs() << ' ' << printReg(T, TRI));
Asc.insert(T);
// Make it symmetric.
AssocMap[T].insert(R);
unsigned LoR = MRI->createVirtualRegister(IntRC);
unsigned HiR = MRI->createVirtualRegister(IntRC);
- DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> "
- << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n');
+ DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
+ << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n');
PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
}
raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
OS << '{';
for (auto &I : P.Obj) {
- OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{';
+ OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second);
if (++J != E)
void RegisterAggr::print(raw_ostream &OS) const {
OS << '{';
for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
- OS << ' ' << PrintRegUnit(U, &PRI.getTRI());
+ OS << ' ' << printRegUnit(U, &PRI.getTRI());
OS << " }";
}
projects / llvm / commitdiff