PR9377: Handle x86 str with register operand in a way consistent with gas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td
index 6a24d145c6967c1a5523440e97ee04da440b7fc9..be7d5efa5a9bef902689594c1dfd335156b3a16c 100644 (file)
--- a/lib/Target/X86/X86InstrSystem.td
+++ b/lib/Target/X86/X86InstrSystem.td
@@ -207,10 +207,15 @@ def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
 
 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
 
-def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
-             "str{w}\t{$dst}", []>, TB;
-def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
-             "str{w}\t{$dst}", []>, TB;
+def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
+               "str{w}\t{$dst}", []>, TB, OpSize;
+def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
+               "str{l}\t{$dst}", []>, TB;
+def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
+                "str{q}\t{$dst}", []>, TB;
+def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
+               "str{w}\t{$dst}", []>, TB;
+
 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
              "ltr{w}\t{$src}", []>, TB;
 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),

diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s
index 723983da6de6a5729f02910635aab072f711f229..9dba65298c1c225dd930587c9c46cd9f5d6fd054 100644 (file)
--- a/test/MC/X86/x86-32.s
+++ b/test/MC/X86/x86-32.s
@@ -816,3 +816,11 @@ pshufw $90, %mm4, %mm0
 // CHECK: loopne 0
 // CHECK: encoding: [0xe0,A]
        loopnz 0
+
+// CHECK: strw
+// CHECK: encoding: [0x66,0x0f,0x00,0xc8]
+       str %ax
+
+// CHECK: strl
+// CHECK: encoding: [0x0f,0x00,0xc8]
+       str %eax