[ARM] GlobalISel: Support loading from the stack

Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit
scalars only). This will be useful for functions that need to pass arguments on
the stack.

First part of https://reviews.llvm.org/D27195.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290096 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp
index 53298f6476d12be54a1a55e8ec7e5c8fff8c8e5d..c01043dddeadca9575e3bb0f11419fe6f67cc656 100644 (file)
--- a/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -75,11 +75,27 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
     return true;
   }
 
-  if (I.getOpcode() == TargetOpcode::G_ADD) {
+  MachineInstrBuilder MIB{MF, I};
+
+  using namespace TargetOpcode;
+  switch (I.getOpcode()) {
+  case G_ADD:
     I.setDesc(TII.get(ARM::ADDrr));
-    AddDefaultCC(AddDefaultPred(MachineInstrBuilder(MF, I)));
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+    AddDefaultCC(AddDefaultPred(MIB));
+    break;
+  case G_FRAME_INDEX:
+    // Add 0 to the given frame index and hope it will eventually be folded into
+    // the user(s).
+    I.setDesc(TII.get(ARM::ADDri));
+    AddDefaultCC(AddDefaultPred(MIB.addImm(0)));
+    break;
+  case G_LOAD:
+    I.setDesc(TII.get(ARM::LDRi12));
+    AddDefaultPred(MIB.addImm(0));
+    break;
+  default:
+    return false;
   }
 
-  return false;
+  return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }

diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp
index 65679507aca7a362db0102eb209b6081079bf072..66801960d8359c54bc2018925399a42852620a93 100644 (file)
--- a/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -25,8 +25,14 @@ using namespace llvm;
 
 ARMLegalizerInfo::ARMLegalizerInfo() {
   using namespace TargetOpcode;
+  const LLT p0 = LLT::pointer(0, 32);
   const LLT s32 = LLT::scalar(32);
 
+  setAction({G_FRAME_INDEX, p0}, Legal);
+
+  setAction({G_LOAD, s32}, Legal);
+  setAction({G_LOAD, 1, p0}, Legal);
+
   setAction({G_ADD, s32}, Legal);
 
   computeTables();

diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 02100aadfbd4347b1e39a56ae7549056b61a01ba..9bd036a1eaceb26ea7ea758fe5965e18b5994765 100644 (file)
--- a/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -103,12 +103,25 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       return Mapping;
   }
 
-  if (Opc == TargetOpcode::G_ADD) {
-    unsigned NumOperands = MI.getNumOperands();
-    ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
-    return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
-                              NumOperands};
+  using namespace TargetOpcode;
+
+  unsigned NumOperands = MI.getNumOperands();
+  const ValueMapping *OperandsMapping = &ARM::ValueMappings[0];
+
+  switch (Opc) {
+  case G_ADD:
+  case G_LOAD:
+    // FIXME: We're abusing the fact that everything lives in a GPR for now; in
+    // the real world we would use different mappings.
+    OperandsMapping = &ARM::ValueMappings[0];
+    break;
+  case G_FRAME_INDEX:
+    OperandsMapping = getOperandsMapping({&ARM::ValueMappings[0], nullptr});
+    break;
+  default:
+    return InstructionMapping{};
   }
 
-  return InstructionMapping{};
+  return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
+                            NumOperands};
 }

diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 41e238a68082a58a25fe303aca29a0d442676314..22ae8fcd5aa6a76032dac3a3ca106d5be96b396e 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -1,6 +1,7 @@
 # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 --- |
   define void @test_adds32() { ret void }
+  define void @test_load_from_stack() { ret void }
 ...
 ---
 name:            test_adds32
@@ -35,3 +36,33 @@ body:             |
     BX_RET 14, _, implicit %r0
     ; CHECK: BX_RET 14, _, implicit %r0
 ...
+---
+name:            test_load_from_stack
+# CHECK-LABEL: name: test_load_from_stack
+legalized:       true
+regBankSelected: true
+selected:        false
+# CHECK: selected: true
+registers:
+  - { id: 0, class: gprb }
+  - { id: 1, class: gprb }
+  - { id: 2, class: gprb }
+  - { id: 3, class: gprb }
+fixedStack:
+  - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+# CHECK: id: [[FRAME_INDEX:[0-9]+]], offset: 8
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3
+
+    %0(p0) = G_FRAME_INDEX %fixed-stack.2
+    ; CHECK: [[FIVREG:%[0-9]+]] = ADDri %fixed-stack.[[FRAME_INDEX]], 0, 14, _, _
+
+    %1(s32) = G_LOAD %0(p0)
+    ; CHECK: {{%[0-9]+}} = LDRi12 [[FIVREG]], 0, 14, _
+
+    BX_RET 14, _
+    ; CHECK: BX_RET 14, _
+...

diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
index 228296d58289c04d01bd36d21db4781780a30b58..f6006da4dc51cf1538d383074d1291387bedd317 100644 (file)
--- a/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
+++ b/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
@@ -1,6 +1,7 @@
 # RUN: llc -mtriple arm-- -global-isel -run-pass=legalizer %s -o - | FileCheck %s
 --- |
   define void @test_add_s32() { ret void }
+  define void @test_load_from_stack() { ret void }
 ...
 ---
 name:            test_add_s32
@@ -27,3 +28,33 @@ body:             |
     BX_RET 14, _, implicit %r0
 
 ...
+---
+name:            test_load_from_stack
+# CHECK-LABEL: name: test_load_from_stack
+legalized:       false
+# CHECK: legalized: true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+fixedStack:
+  - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
+  # CHECK: id: [[FRAME_INDEX:[0-9]+]], offset: 8
+body:             |
+  bb.0:
+    liveins: %r0, %r1, %r2, %r3
+
+    ; This is legal, so we should find it unchanged in the output
+    ; CHECK: [[FIVREG:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
+    ; CHECK: {{%[0-9]+}}(s32) = G_LOAD [[FIVREG]](p0)
+    %0(p0) = G_FRAME_INDEX %fixed-stack.2
+    %1(s32) = G_LOAD %0(p0)
+    BX_RET 14, _
+
+...