[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets

This is a follow on to D58632, with the same logic. Given a memory operation which needs ordering, but doesn't need to modify any particular address, prefer to use a locked stack op over an mfence.

Differential Revision: https://reviews.llvm.org/D61863

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360649 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index cb19bc2741f8a5c69fba123673459646954b324a..b905d2794d2c5c861db89dc39d46980c7cc8b55f 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -26456,9 +26456,10 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG,
                                               Ops, MVT::i64,
                                               Node->getMemOperand());
 
-      // If this is a sequentially consistent store, also emit an mfence.
+      // If this is a sequentially consistent store, also emit an appropriate
+      // barrier.
       if (IsSeqCst)
-        Chain = DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Chain);
+        Chain = emitLockedStackOp(DAG, Subtarget, Chain, dl);
 
       return Chain;
     }

diff --git a/test/CodeGen/X86/atomic-load-store-wide.ll b/test/CodeGen/X86/atomic-load-store-wide.ll
index f79bd7527ae1fdb3f621c2385748ddd44bb883d6..bdb88564cf844562f72326c42f7716488ef272ad 100644 (file)
--- a/test/CodeGen/X86/atomic-load-store-wide.ll
+++ b/test/CodeGen/X86/atomic-load-store-wide.ll
@@ -11,7 +11,7 @@ define void @test1(i64* %ptr, i64 %val1) {
 ; SSE42-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE42-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE42-NEXT:    movlps %xmm0, (%eax)
-; SSE42-NEXT:    mfence
+; SSE42-NEXT:    lock orl $0, (%esp)
 ; SSE42-NEXT:    retl
 ;
 ; NOSSE-LABEL: test1:

diff --git a/test/CodeGen/X86/atomic-non-integer.ll b/test/CodeGen/X86/atomic-non-integer.ll
index 39446c40e5bfbb59606f7bb2f8cd7580d0dd8078..d40eb76315f46aec4dbd1de2075f8332eefa9c2c 100644 (file)
--- a/test/CodeGen/X86/atomic-non-integer.ll
+++ b/test/CodeGen/X86/atomic-non-integer.ll
@@ -710,7 +710,7 @@ define void @store_double_seq_cst(double* %fptr, double %v) {
 ; X86-SSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-SSE2-NEXT:    movlps %xmm0, (%eax)
-; X86-SSE2-NEXT:    mfence
+; X86-SSE2-NEXT:    lock orl $0, (%esp)
 ; X86-SSE2-NEXT:    retl
 ;
 ; X86-AVX-LABEL: store_double_seq_cst:
@@ -718,7 +718,7 @@ define void @store_double_seq_cst(double* %fptr, double %v) {
 ; X86-AVX-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X86-AVX-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; X86-AVX-NEXT:    vmovlps %xmm0, (%eax)
-; X86-AVX-NEXT:    mfence
+; X86-AVX-NEXT:    lock orl $0, (%esp)
 ; X86-AVX-NEXT:    retl
 ;
 ; X86-NOSSE-LABEL: store_double_seq_cst: