IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
[]>;
-
-// FIXME: Verify encoding after integrated assembler is working.
def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
(outs), (ins DPR:$Dd, DPR:$Dm),
IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
let Inst{5} = 0;
}
-// FIXME: Verify encoding after integrated assembler is working.
def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
(outs), (ins DPR:$Dd),
IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
// Between half, single and double-precision. For disassembly only.
-// FIXME: Verify encoding after integrated assembler is working.
def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
[/* For disassembly only; pattern left blank */]>,
// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
let Uses = [FPSCR] in {
-// FIXME: Verify encoding after integrated assembler is working.
def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
(outs SPR:$Sd), (ins DPR:$Dm),
IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
+ vcmp.f64 d17, d16
+ vcmp.f32 s1, s0
+
+@ CHECK: vcmp.f64 d17, d16 @ encoding: [0x60,0x1b,0xf4,0xee]
+@ CHECK: vcmp.f32 s1, s0 @ encoding: [0x40,0x0a,0xf4,0xee]
+
+ vcmp.f64 d17, #0.0
+ vcmp.f32 s1, #0.0
+
+@ CHECK: vcmp.f64 d17, #0 @ encoding: [0x40,0x1b,0xf5,0xee]
+@ CHECK: vcmp.f32 s1, #0 @ encoding: [0x40,0x0a,0xf5,0xee]
+
vcmpe.f64 d17, d16
vcmpe.f32 s1, s0