Reverting r272778 because there's an assertion

failure when running the test CodeGen/ARM/intrinsics-coprocessor.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272791 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td
index 0995985968853982a994868ce0fe94f4e546b611..3240f49b2fd93fab80bfd26f9deb9c47e1b81fe2 100644 (file)
--- a/include/llvm/IR/IntrinsicsARM.td
+++ b/include/llvm/IR/IntrinsicsARM.td
@@ -123,15 +123,12 @@ def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
                   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 
 // Move from two registers to coprocessor
-def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
-                                  llvm_i32_ty, llvm_i32_ty], []>;
-def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
-                                   llvm_i32_ty, llvm_i32_ty], []>;
-
-def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
-                              llvm_i32_ty, llvm_i32_ty], []>;
-def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
-                               llvm_i32_ty, llvm_i32_ty], []>;
+def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
+   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
+                  llvm_i32_ty, llvm_i32_ty], []>;
+def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
+   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
+                  llvm_i32_ty, llvm_i32_ty], []>;
 
 //===----------------------------------------------------------------------===//
 // CRC32

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 15f4f506f7fac36ad7b67c89d9db6b578dd6e22e..4af21748374cc0513fff3ba57e94b1ee5bbfa848 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -3335,34 +3335,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
     default:
       break;
 
-    case Intrinsic::arm_mrrc:
-    case Intrinsic::arm_mrrc2: {
-      SDLoc dl(N);
-      SDValue Chain = N->getOperand(0);
-      unsigned Opc;
-
-      if (Subtarget->isThumb())
-        Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2);
-      else
-        Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2);
-
-      SmallVector<SDValue, 5> Ops;
-      Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */
-      Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */
-      Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */
-      Ops.push_back(getAL(CurDAG, dl));
-      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
-      Ops.push_back(Chain);
-
-      // Writes to two registers.
-      std::vector<EVT> RetType;
-      RetType.push_back(MVT::i32);
-      RetType.push_back(MVT::i32);
-      RetType.push_back(MVT::Other);
-
-      ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops));
-      return;
-    }
     case Intrinsic::arm_ldaexd:
     case Intrinsic::arm_ldrexd: {
       SDLoc dl(N);

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index fa18ecd276403cff02f847334eaf782fb792ce78..37db70dfbbb832eefb62ed3b9f0589dfe6fc6032 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -5145,9 +5145,9 @@ def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */,
                       (outs GPRnopc:$Rt, GPRnopc:$Rt2),
                       (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
 
-class MovRRCopro2<string opc, bit direction, dag oops, dag iops,
-                  list<dag> pattern = []>
-  : ABXI<0b1100, oops, iops, NoItinerary,
+class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
+  : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
+         GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
     Requires<[PreV8]> {
   let Inst{31-28} = 0b1111;
@@ -5166,18 +5166,13 @@ class MovRRCopro2<string opc, bit direction, dag oops, dag iops,
   let Inst{7-4}   = opc1;
   let Inst{3-0}   = CRm;
 
-  let DecoderMethod = "DecoderForMRRC2AndMCRR2";
+  let DecoderMethod = "DecodeMRRC2";
 }
 
 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
-                        (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt,
-                        GPRnopc:$Rt2, c_imm:$CRm),
                         [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
                                         GPRnopc:$Rt2, imm:$CRm)]>;
-
-def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */,
-                       (outs GPRnopc:$Rt, GPRnopc:$Rt2),
-                       (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>;
+def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
 
 //===----------------------------------------------------------------------===//
 // Move between special register and ARM core register

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 3196a57ccc3e97e33e9163f91feb916af6c6782f..ad1e03ae1e7f93f1ef264ac09cb60dca7e053c0d 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -395,8 +395,8 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
 
 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
                                 uint64_t Address, const void *Decoder);
-static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
-                                            uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
+                                uint64_t Address, const void *Decoder);
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,
@@ -5265,8 +5265,8 @@ static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
   return S;
 }
 
-static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
-                                            uint64_t Address, const void *Decoder) {
+static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
+                                uint64_t Address, const void *Decoder) {
 
   DecodeStatus S = MCDisassembler::Success;
 
@@ -5282,30 +5282,12 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val,
   if (Rt == Rt2)
     S = MCDisassembler::SoftFail;
 
-  // We have to check if the instruction is MRRC2
-  // or MCRR2 when constructing the operands for
-  // Inst. Reason is because MRRC2 stores to two
-  // registers so it's tablegen desc has has two
-  // outputs whereas MCRR doesn't store to any
-  // registers so all of it's operands are listed
-  // as inputs, therefore the operand order for
-  // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
-  // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
-
-  if (Inst.getOpcode() == ARM::MRRC2) {
-    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
-      return MCDisassembler::Fail;
-    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
-      return MCDisassembler::Fail;
-  }
   Inst.addOperand(MCOperand::createImm(cop));
   Inst.addOperand(MCOperand::createImm(opc1));
-  if (Inst.getOpcode() == ARM::MCRR2) {
-    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
-      return MCDisassembler::Fail;
-    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
-      return MCDisassembler::Fail;
-  }
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+    return MCDisassembler::Fail;
+  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createImm(CRm));
 
   return S;

diff --git a/test/CodeGen/ARM/intrinsics-coprocessor.ll b/test/CodeGen/ARM/intrinsics-coprocessor.ll
index 8fea49b39fb6074f4334713f96306f283c4a3bd7..ccaf5c29fad2735324ce71c0102b7e312402182d 100644 (file)
--- a/test/CodeGen/ARM/intrinsics-coprocessor.ll
+++ b/test/CodeGen/ARM/intrinsics-coprocessor.ll
@@ -35,10 +35,6 @@ entry:
   tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind
   ; CHECK: stc2l p7, c3, [r{{[0-9]+}}]
   tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind
-  ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
-  %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind
-  ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3
-  %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind
   ret void
 }
 
@@ -73,7 +69,3 @@ declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind
 declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind
 
 declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind
-
-declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind
-
-declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind