AMDGPU: Set correct sched model on v_mad_u64_u32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317645 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/VOP3Instructions.td b/lib/Target/AMDGPU/VOP3Instructions.td
index aa041aab51c8db713a9dd12ba003b4049efd8fa3..666b80107dc693752e72c22660e804ce71f47023 100644 (file)
--- a/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/lib/Target/AMDGPU/VOP3Instructions.td
@@ -399,8 +399,10 @@ def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_
 } // End Constraints = "@earlyclobber $vdst"
 
 let isCommutable = 1 in {
+let SchedRW = [WriteDouble, WriteSALU] in {
 def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
+} // End SchedRW = [WriteDouble, WriteSALU]
 } // End isCommutable = 1
 
 } // End SubtargetPredicate = isCIVI

diff --git a/test/CodeGen/AMDGPU/mul.ll b/test/CodeGen/AMDGPU/mul.ll
index 8839fcdffbc452245a1285871b5a4639514c2f6c..555c65a6ffe9cea248e37706455fca1f349ac020 100644 (file)
--- a/test/CodeGen/AMDGPU/mul.ll
+++ b/test/CodeGen/AMDGPU/mul.ll
@@ -227,10 +227,10 @@ endif:
 
 
 ; VI: s_mul_i32
-; VI: s_mul_i32
-; VI: v_mul_hi_u32
 ; VI: v_mul_hi_u32
 ; VI: v_mad_u64_u32
+; VI: s_mul_i32
+; VI: v_mul_hi_u32
 ; VI: v_mad_u64_u32
 ; VI: v_mad_u64_u32
 
@@ -254,7 +254,7 @@ define amdgpu_kernel void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b)
 ; GCN-DAG: v_mul_hi_u32
 ; GCN-DAG: v_mul_lo_i32
 ; GCN-DAG: v_mul_lo_i32
-; GCN: v_add_i32_e32
+; GCN-DAG: v_add_i32_e32
 
 ; SI-DAG: v_mul_hi_u32
 ; SI-DAG: v_mul_lo_i32
@@ -265,7 +265,7 @@ define amdgpu_kernel void @s_mul_i128(i128 addrspace(1)* %out, i128 %a, i128 %b)
 ; SI-DAG: v_mul_lo_i32
 ; SI-DAG: v_mul_lo_i32
 
-; VI: v_mad_u64_u32
+; VI-DAG: v_mad_u64_u32
 ; VI: v_mad_u64_u32
 ; VI: v_mad_u64_u32