[ARM] Don't generate deprecated T1 STM.

This prevents generating stm r1!, {r0, r1} on Thumb1, where value
stored for r1 is UNKONWN.

Patch by Zhaoshi Zheng.

Differential Revision: https://reviews.llvm.org/D27910

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296538 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index c87f70397b71292a3a409c91c4e273a5423520a9..8e51f136b32fc4b75fe8f90fa25d3f0cc951b1cc 100644 (file)
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -609,13 +609,12 @@ MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(
   // Exception: If the base register is in the input reglist, Thumb1 LDM is
   // non-writeback.
   // It's also not possible to merge an STR of the base register in Thumb1.
-  if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
+  if (isThumb1 && ContainsReg(Regs, Base)) {
     assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
-    if (Opcode == ARM::tLDRi) {
+    if (Opcode == ARM::tLDRi)
       Writeback = false;
-    } else if (Opcode == ARM::tSTRi) {
+    else if (Opcode == ARM::tSTRi)
       return nullptr;
-    }
   }
 
   ARM_AM::AMSubMode Mode = ARM_AM::ia;

diff --git a/test/CodeGen/Thumb/stm-deprecated.ll b/test/CodeGen/Thumb/stm-deprecated.ll
new file mode 100644 (file)
index 0000000..ffe2c0a
--- /dev/null
+++ b/test/CodeGen/Thumb/stm-deprecated.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv5e-linux-gnueabi -verify-machineinstrs %s -o - | FileCheck %s
+
+%0 = type { %0*, %0*, i32 }
+
+@x1 = external global %0, align 4
+@x2 = external global %0, align 4
+
+; CHECK: str r0, [r1]
+; CHECK-NEXT: str r1, [r1, #4]
+; CHECK-NOT: stm
+
+define void @foo(i32 %unused, %0* %x) {
+  %first = getelementptr inbounds %0, %0* %x, i32 0, i32 0
+  %second = getelementptr inbounds %0, %0* %x, i32 0, i32 1
+  store %0* @x1, %0** %first
+  store %0* %x, %0** %second
+  unreachable
+}