esp32: fix incorrect clock enable bit name for UART0

Closes https://github.com/espressif/esp-idf/issues/1301

diff --git a/components/esp32/clk.c b/components/esp32/clk.c
index 15b8af36c603845df5d852b362fec309dce4b670..4c6209762fb2ca30dd66abd4079363b08be9e3dd 100644 (file)
--- a/components/esp32/clk.c
+++ b/components/esp32/clk.c
@@ -187,7 +187,7 @@ void esp_perip_clk_init(void)
         common_perip_clk = DPORT_WDG_CLK_EN |
                               DPORT_I2S0_CLK_EN |
 #if CONFIG_CONSOLE_UART_NUM != 0
-                              DPORT_UART0_CLK_EN |
+                              DPORT_UART_CLK_EN |
 #endif
 #if CONFIG_CONSOLE_UART_NUM != 1
                               DPORT_UART1_CLK_EN |