soc: fix/update definitions related to FRC timers

1. BIT(8) of CTRL is actually read-only bit indicating interrupt status

2. BIT(0) or CTRL had inverted meaning: 1 is “level”, 0 is “edge”

3. Add definitions of prescaler values

diff --git a/components/soc/esp32/include/soc/frc_timer_reg.h b/components/soc/esp32/include/soc/frc_timer_reg.h
index d76199c4f357ca0cce84bb6d201fca96ad513f2d..a2152c5c91aeafb94ae6da5e4b451edd468f78a3 100644 (file)
--- a/components/soc/esp32/include/soc/frc_timer_reg.h
+++ b/components/soc/esp32/include/soc/frc_timer_reg.h
@@ -32,12 +32,15 @@
 #define FRC_TIMER_COUNT_S               0
 
 #define FRC_TIMER_CTRL_REG(i)           (REG_FRC_TIMER_BASE(i) + 0x8)
-#define FRC_TIMER_INT_ENABLE            (BIT(8))        // enable interrupt
+#define FRC_TIMER_INT_STATUS            (BIT(8))        // interrupt status (RO)
 #define FRC_TIMER_ENABLE                (BIT(7))        // enable timer
 #define FRC_TIMER_AUTOLOAD              (BIT(6))        // enable autoload
-#define FRC_TIMER_PRESCALER             0x00000007      // 0: divide by 1, 2: divide by 16, 4: divide by 256
+#define FRC_TIMER_PRESCALER             0x00000007
 #define FRC_TIMER_PRESCALER_S           1
-#define FRC_TIMER_EDGE_INT              (BIT(0))        // 0: level, 1: edge
+#define FRC_TIMER_PRESCALER_1           (0 << FRC_TIMER_PRESCALER_S)
+#define FRC_TIMER_PRESCALER_16          (2 << FRC_TIMER_PRESCALER_S)
+#define FRC_TIMER_PRESCALER_256         (4 << FRC_TIMER_PRESCALER_S)
+#define FRC_TIMER_LEVEL_INT             (BIT(0))        // 1: level, 0: edge
 
 #define FRC_TIMER_INT_REG(i)            (REG_FRC_TIMER_BASE(i) + 0xC)
 #define FRC_TIMER_INT_CLR               (BIT(0))        // clear interrupt