--- /dev/null
+//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a target parser to recognise hardware features such as
+// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_TARGETPARSER_H
+#define LLVM_SUPPORT_TARGETPARSER_H
+
+namespace llvm {
+ class StringRef;
+
+// Target specific information into their own namespaces. These should be
+// generated from TableGen because the information is already there, and there
+// is where new information about targets will be added.
+// FIXME: To TableGen this we need to make some table generated files available
+// even if the back-end is not compiled with LLVM, plus we need to create a new
+// back-end to TableGen to create these clean tables.
+namespace ARM {
+ // FPU names.
+ enum FPUKind {
+ INVALID_FPU = 0,
+ VFP,
+ VFPV2,
+ VFPV3,
+ VFPV3_D16,
+ VFPV4,
+ VFPV4_D16,
+ FPV5_D16,
+ FP_ARMV8,
+ NEON,
+ NEON_VFPV4,
+ NEON_FP_ARMV8,
+ CRYPTO_NEON_FP_ARMV8,
+ SOFTVFP,
+ LAST_FPU
+ };
+
+ // Arch names.
+ enum ArchKind {
+ INVALID_ARCH = 0,
+ ARMV2,
+ ARMV2A,
+ ARMV3,
+ ARMV3M,
+ ARMV4,
+ ARMV4T,
+ ARMV5,
+ ARMV5T,
+ ARMV5TE,
+ ARMV6,
+ ARMV6J,
+ ARMV6K,
+ ARMV6T2,
+ ARMV6Z,
+ ARMV6ZK,
+ ARMV6M,
+ ARMV7,
+ ARMV7A,
+ ARMV7R,
+ ARMV7M,
+ ARMV8A,
+ ARMV8_1A,
+ IWMMXT,
+ IWMMXT2,
+ LAST_ARCH
+ };
+
+ // Arch extension modifiers for CPUs.
+ enum ArchExtKind {
+ INVALID_ARCHEXT = 0,
+ CRC,
+ CRYPTO,
+ FP,
+ HWDIV,
+ MP,
+ SEC,
+ VIRT,
+ LAST_ARCHEXT
+ };
+
+} // namespace ARM
+
+// Target Parsers, one per architecture.
+class ARMTargetParser {
+ static StringRef getFPUSynonym(StringRef FPU);
+ static StringRef getArchSynonym(StringRef Arch);
+
+public:
+ // Information by ID
+ static const char * getFPUName(unsigned ID);
+ static const char * getArchName(unsigned ID);
+ static unsigned getArchDefaultCPUArch(unsigned ID);
+ static const char * getArchDefaultCPUName(unsigned ID);
+ static const char * getArchExtName(unsigned ID);
+
+ // Parser
+ static unsigned parseFPU(StringRef FPU);
+ static unsigned parseArch(StringRef Arch);
+ static unsigned parseArchExt(StringRef ArchExt);
+};
+
+} // namespace llvm
+
+#endif
StringPool.cpp
StringRef.cpp
SystemUtils.cpp
+ TargetParser.cpp
Timer.cpp
ToolOutputFile.cpp
Triple.cpp
--- /dev/null
+//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a target parser to recognise hardware features such as
+// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/TargetParser.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+
+using namespace llvm;
+
+namespace {
+
+// List of canonical FPU names (use getFPUSynonym)
+// FIXME: TableGen this.
+struct {
+ const char * Name;
+ ARM::FPUKind ID;
+} FPUNames[] = {
+ { "invalid", ARM::INVALID_FPU },
+ { "vfp", ARM::VFP },
+ { "vfpv2", ARM::VFPV2 },
+ { "vfpv3", ARM::VFPV3 },
+ { "vfpv3-d16", ARM::VFPV3_D16 },
+ { "vfpv4", ARM::VFPV4 },
+ { "vfpv4-d16", ARM::VFPV4_D16 },
+ { "fpv5-d16", ARM::FPV5_D16 },
+ { "fp-armv8", ARM::FP_ARMV8 },
+ { "neon", ARM::NEON },
+ { "neon-vfpv4", ARM::NEON_VFPV4 },
+ { "neon-fp-armv8", ARM::NEON_FP_ARMV8 },
+ { "crypto-neon-fp-armv8", ARM::CRYPTO_NEON_FP_ARMV8 },
+ { "softvfp", ARM::SOFTVFP }
+};
+// List of canonical arch names (use getArchSynonym)
+// FIXME: TableGen this.
+struct {
+ const char *Name;
+ ARM::ArchKind ID;
+ const char *DefaultCPU;
+ ARMBuildAttrs::CPUArch DefaultArch;
+} ARCHNames[] = {
+ { "invalid", ARM::INVALID_ARCH, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
+ { "armv2", ARM::ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
+ { "armv2a", ARM::ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
+ { "armv3", ARM::ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
+ { "armv3m", ARM::ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
+ { "armv4", ARM::ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
+ { "armv4t", ARM::ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
+ { "armv5", ARM::ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
+ { "armv5t", ARM::ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
+ { "armv5te", ARM::ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
+ { "armv6", ARM::ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
+ { "armv6j", ARM::ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
+ { "armv6k", ARM::ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
+ { "armv6t2", ARM::ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
+ { "armv6z", ARM::ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
+ { "armv6zk", ARM::ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
+ { "armv6-m", ARM::ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
+ { "armv7", ARM::ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7-a", ARM::ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7-r", ARM::ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
+ { "armv7-m", ARM::ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
+ { "armv8-a", ARM::ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
+ { "armv8.1-a", ARM::ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
+ { "iwmmxt", ARM::IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
+ { "iwmmxt2", ARM::IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }
+};
+// List of canonical ARCH names (use getARCHSynonym)
+// FIXME: TableGen this.
+struct {
+ const char *Name;
+ ARM::ArchExtKind ID;
+} ARCHExtNames[] = {
+ { "invalid", ARM::INVALID_ARCHEXT },
+ { "crc", ARM::CRC },
+ { "crypto", ARM::CRYPTO },
+ { "fp", ARM::FP },
+ { "idiv", ARM::HWDIV },
+ { "mp", ARM::MP },
+ { "sec", ARM::SEC },
+ { "virt", ARM::VIRT }
+};
+
+} // namespace
+
+namespace llvm {
+
+// ======================================================= //
+// Information by ID
+// ======================================================= //
+
+const char *ARMTargetParser::getFPUName(unsigned ID) {
+ if (ID >= ARM::LAST_FPU)
+ return nullptr;
+ return FPUNames[ID].Name;
+}
+
+const char *ARMTargetParser::getArchName(unsigned ID) {
+ if (ID >= ARM::LAST_ARCH)
+ return nullptr;
+ return ARCHNames[ID].Name;
+}
+
+const char *ARMTargetParser::getArchDefaultCPUName(unsigned ID) {
+ if (ID >= ARM::LAST_ARCH)
+ return nullptr;
+ return ARCHNames[ID].DefaultCPU;
+}
+
+unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ID) {
+ if (ID >= ARM::LAST_ARCH)
+ return 0;
+ return ARCHNames[ID].DefaultArch;
+}
+
+const char *ARMTargetParser::getArchExtName(unsigned ID) {
+ if (ID >= ARM::LAST_ARCHEXT)
+ return nullptr;
+ return ARCHExtNames[ID].Name;
+}
+
+// ======================================================= //
+// Parsers
+// ======================================================= //
+
+StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) {
+ return StringSwitch<StringRef>(FPU)
+ .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
+ .Case("vfp2", "vfpv2")
+ .Case("vfp3", "vfpv3")
+ .Case("vfp4", "vfpv4")
+ .Case("vfp3-d16", "vfpv3-d16")
+ .Case("vfp4-d16", "vfpv4-d16")
+ // FIXME: sp-16 is NOT the same as d16
+ .Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16")
+ .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
+ .Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16")
+ .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
+ // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
+ .Case("neon-vfpv3", "neon")
+ .Default(FPU);
+}
+
+StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
+ return StringSwitch<StringRef>(Arch)
+ .Case("armv5tej", "armv5te")
+ .Case("armv6m", "armv6-m")
+ .Case("armv7a", "armv7-a")
+ .Case("armv7r", "armv7-r")
+ .Case("armv7m", "armv7-m")
+ .Case("armv8a", "armv8-a")
+ .Case("armv8.1a", "armv8.1-a")
+ .Default(Arch);
+}
+
+unsigned ARMTargetParser::parseFPU(StringRef FPU) {
+ StringRef Syn = getFPUSynonym(FPU);
+ for (const auto F : FPUNames) {
+ if (Syn == F.Name)
+ return F.ID;
+ }
+ return ARM::INVALID_FPU;
+}
+
+unsigned ARMTargetParser::parseArch(StringRef Arch) {
+ StringRef Syn = getArchSynonym(Arch);
+ for (const auto A : ARCHNames) {
+ if (Syn == A.Name)
+ return A.ID;
+ }
+ return ARM::INVALID_ARCH;
+}
+
+unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
+ for (const auto A : ARCHExtNames) {
+ if (ArchExt == A.Name)
+ return A.ID;
+ }
+ return ARM::INVALID_ARCHEXT;
+}
+
+} // namespace llvm
.Default(UnknownArch);
}
+// FIXME: Use ARMTargetParser. This would require Triple::arm/thumb
+// to be recogniseable universally.
static Triple::ArchType parseARMArch(StringRef ArchName) {
size_t offset = StringRef::npos;
Triple::ArchType arch = Triple::UnknownArch;
.Default(Triple::UnknownObjectFormat);
}
+// FIXME: Use ARMTargetParser. This would require using Triple::ARMSubArch*
+// in ARMBuildAttrs and in ARCHNames' DefaultArch fields.
static Triple::SubArchType parseSubArch(StringRef SubArchName) {
if (SubArchName.endswith("eb"))
SubArchName = SubArchName.substr(0, SubArchName.size() - 2);
return T;
}
-// FIXME: tblgen this.
+// FIXME: Use ARMTargetParser. This would require ARCHNames to hold
+// specific CPU names, as well as default CPU arch.
const char *Triple::getARMCPUForArch(StringRef MArch) const {
if (MArch.empty())
MArch = getArchName();
+++ /dev/null
-//===-- ARMArchExtName.def - List of the ARM Extension names ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the list of the supported ARM Architecture Extension
-// names. These can be used to enable the extension through .arch_extension
-// attribute
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-#ifndef ARM_ARCHEXT_NAME
-#error "You must define ARM_ARCHEXT_NAME(NAME, ID) before including ARMArchExtName.h"
-#endif
-
-ARM_ARCHEXT_NAME("crc", CRC)
-ARM_ARCHEXT_NAME("crypto", CRYPTO)
-ARM_ARCHEXT_NAME("fp", FP)
-ARM_ARCHEXT_NAME("idiv", HWDIV)
-ARM_ARCHEXT_NAME("mp", MP)
-ARM_ARCHEXT_NAME("sec", SEC)
-ARM_ARCHEXT_NAME("virt", VIRT)
-
-#undef ARM_ARCHEXT_NAME
+++ /dev/null
-//===-- ARMArchExtName.h - List of the ARM Extension names ------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_ARM_ARMARCHEXTNAME_H
-#define LLVM_LIB_TARGET_ARM_ARMARCHEXTNAME_H
-
-namespace llvm {
-namespace ARM {
-
-enum ArchExtKind {
- INVALID_ARCHEXT = 0
-
-#define ARM_ARCHEXT_NAME(NAME, ID) , ID
-#include "ARMArchExtName.def"
-};
-
-} // namespace ARM
-} // namespace llvm
-
-#endif
#include "ARMAsmPrinter.h"
#include "ARM.h"
#include "ARMConstantPoolValue.h"
-#include "ARMFPUName.h"
-#include "ARMArchExtName.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMTargetMachine.h"
#include "ARMTargetObjectFile.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/TargetParser.h"
#include "llvm/Support/COFF.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
+++ /dev/null
-//===-- ARMFPUName.def - List of the ARM FPU names --------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the list of the supported ARM FPU names.
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-#ifndef ARM_FPU_NAME
-#error "You must define ARM_FPU_NAME(NAME, ID) before including ARMFPUName.h"
-#endif
-
-ARM_FPU_NAME("vfp", VFP)
-ARM_FPU_NAME("vfpv2", VFPV2)
-ARM_FPU_NAME("vfpv3", VFPV3)
-ARM_FPU_NAME("vfpv3-d16", VFPV3_D16)
-ARM_FPU_NAME("vfpv4", VFPV4)
-ARM_FPU_NAME("vfpv4-d16", VFPV4_D16)
-ARM_FPU_NAME("fpv5-d16", FPV5_D16)
-ARM_FPU_NAME("fp-armv8", FP_ARMV8)
-ARM_FPU_NAME("neon", NEON)
-ARM_FPU_NAME("neon-vfpv4", NEON_VFPV4)
-ARM_FPU_NAME("neon-fp-armv8", NEON_FP_ARMV8)
-ARM_FPU_NAME("crypto-neon-fp-armv8", CRYPTO_NEON_FP_ARMV8)
-ARM_FPU_NAME("softvfp", SOFTVFP)
-
-#undef ARM_FPU_NAME
+++ /dev/null
-//===-- ARMFPUName.h - List of the ARM FPU names ----------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_ARM_ARMFPUNAME_H
-#define LLVM_LIB_TARGET_ARM_ARMFPUNAME_H
-
-namespace llvm {
-namespace ARM {
-
-enum FPUKind {
- INVALID_FPU = 0
-
-#define ARM_FPU_NAME(NAME, ID) , ID
-#include "ARMFPUName.def"
-};
-
-} // namespace ARM
-} // namespace llvm
-
-#endif
//
//===----------------------------------------------------------------------===//
-#include "ARMFPUName.h"
#include "ARMFeatures.h"
#include "MCTargetDesc/ARMAddressingModes.h"
-#include "MCTargetDesc/ARMArchName.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "MCTargetDesc/ARMMCExpr.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/MC/MCTargetAsmParser.h"
#include "llvm/Support/ARMBuildAttributes.h"
#include "llvm/Support/ARMEHABI.h"
+#include "llvm/Support/TargetParser.h"
#include "llvm/Support/COFF.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ELF.h"
bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
StringRef Arch = getParser().parseStringToEndOfStatement().trim();
- unsigned ID = StringSwitch<unsigned>(Arch)
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
- .Case(NAME, ARM::ID)
-#define ARM_ARCH_ALIAS(NAME, ID) \
- .Case(NAME, ARM::ID)
-#include "MCTargetDesc/ARMArchName.def"
- .Default(ARM::INVALID_ARCH);
+ unsigned ID = ARMTargetParser::parseArch(Arch);
if (ID == ARM::INVALID_ARCH) {
Error(L, "Unknown arch name");
SMLoc FPUNameLoc = getTok().getLoc();
StringRef FPU = getParser().parseStringToEndOfStatement().trim();
- unsigned ID = StringSwitch<unsigned>(FPU)
-#define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
-#include "ARMFPUName.def"
- .Default(ARM::INVALID_FPU);
+ unsigned ID = ARMTargetParser::parseFPU(FPU);
if (ID == ARM::INVALID_FPU) {
Error(FPUNameLoc, "Unknown FPU name");
SMLoc ArchLoc = Parser.getTok().getLoc();
getLexer().Lex();
- unsigned ID = StringSwitch<unsigned>(Arch)
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
- .Case(NAME, ARM::ID)
-#define ARM_ARCH_ALIAS(NAME, ID) \
- .Case(NAME, ARM::ID)
-#include "MCTargetDesc/ARMArchName.def"
-#undef ARM_ARCH_NAME
-#undef ARM_ARCH_ALIAS
- .Default(ARM::INVALID_ARCH);
+ unsigned ID = ARMTargetParser::parseArch(Arch);
if (ID == ARM::INVALID_ARCH) {
Error(ArchLoc, "unknown architecture '" + Arch + "'");
+++ /dev/null
-//===-- ARMArchName.def - List of the ARM arch names ------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the list of the supported ARM architecture names,
-// i.e. the supported value for -march= option.
-//
-//===----------------------------------------------------------------------===//
-
-// NOTE: NO INCLUDE GUARD DESIRED!
-
-#ifndef ARM_ARCH_NAME
-#error "You must define ARM_ARCH_NAME before including ARMArchName.def"
-#endif
-
-// ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH)
-ARM_ARCH_NAME("armv2", ARMV2, "2", v4)
-ARM_ARCH_NAME("armv2a", ARMV2A, "2A", v4)
-ARM_ARCH_NAME("armv3", ARMV3, "3", v4)
-ARM_ARCH_NAME("armv3m", ARMV3M, "3M", v4)
-ARM_ARCH_NAME("armv4", ARMV4, "4", v4)
-ARM_ARCH_NAME("armv4t", ARMV4T, "4T", v4T)
-ARM_ARCH_NAME("armv5", ARMV5, "5", v5T)
-ARM_ARCH_NAME("armv5t", ARMV5T, "5T", v5T)
-ARM_ARCH_NAME("armv5te", ARMV5TE, "5TE", v5TE)
-ARM_ARCH_NAME("armv6", ARMV6, "6", v6)
-ARM_ARCH_NAME("armv6j", ARMV6J, "6J", v6)
-ARM_ARCH_NAME("armv6k", ARMV6K, "6K", v6K)
-ARM_ARCH_NAME("armv6t2", ARMV6T2, "6T2", v6T2)
-ARM_ARCH_NAME("armv6z", ARMV6Z, "6Z", v6KZ)
-ARM_ARCH_NAME("armv6zk", ARMV6ZK, "6ZK", v6KZ)
-ARM_ARCH_NAME("armv6-m", ARMV6M, "6-M", v6_M)
-ARM_ARCH_NAME("armv7", ARMV7, "7", v7)
-ARM_ARCH_NAME("armv7-a", ARMV7A, "7-A", v7)
-ARM_ARCH_ALIAS("armv7a", ARMV7A)
-ARM_ARCH_NAME("armv7-r", ARMV7R, "7-R", v7)
-ARM_ARCH_ALIAS("armv7r", ARMV7R)
-ARM_ARCH_NAME("armv7-m", ARMV7M, "7-M", v7)
-ARM_ARCH_ALIAS("armv7m", ARMV7M)
-ARM_ARCH_NAME("armv8-a", ARMV8A, "8-A", v8)
-ARM_ARCH_ALIAS("armv8a", ARMV8A)
-ARM_ARCH_NAME("armv8.1-a", ARMV8_1A, "8.1-A", v8)
-ARM_ARCH_ALIAS("armv8.1a", ARMV8_1A)
-ARM_ARCH_NAME("iwmmxt", IWMMXT, "iwmmxt", v5TE)
-ARM_ARCH_NAME("iwmmxt2", IWMMXT2, "iwmmxt2", v5TE)
-
-#undef ARM_ARCH_NAME
-#undef ARM_ARCH_ALIAS
+++ /dev/null
-//===-- ARMArchName.h - List of the ARM arch names --------------*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMARCHNAME_H
-#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMARCHNAME_H
-
-namespace llvm {
-namespace ARM {
-
-enum ArchKind {
- INVALID_ARCH = 0
-
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) , ID
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
-};
-
-} // namespace ARM
-} // namespace llvm
-
-#endif
//
//===----------------------------------------------------------------------===//
-#include "ARMArchName.h"
-#include "ARMFPUName.h"
-#include "ARMArchExtName.h"
#include "ARMRegisterInfo.h"
#include "ARMUnwindOpAsm.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/ARMBuildAttributes.h"
#include "llvm/Support/ARMEHABI.h"
+#include "llvm/Support/TargetParser.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/FormattedStream.h"
return (Twine("__aeabi_unwind_cpp_pr") + Twine(Index)).str();
}
-static const char *GetFPUName(unsigned ID) {
- switch (ID) {
- default:
- llvm_unreachable("Unknown FPU kind");
- break;
-#define ARM_FPU_NAME(NAME, ID) case ARM::ID: return NAME;
-#include "ARMFPUName.def"
- }
- return nullptr;
-}
-
-static const char *GetArchName(unsigned ID) {
- switch (ID) {
- default:
- llvm_unreachable("Unknown ARCH kind");
- break;
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
- case ARM::ID: return NAME;
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
- }
- return nullptr;
-}
-
-static const char *GetArchDefaultCPUName(unsigned ID) {
- switch (ID) {
- default:
- llvm_unreachable("Unknown ARCH kind");
- break;
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
- case ARM::ID: return DEFAULT_CPU_NAME;
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
- }
- return nullptr;
-}
-
-static unsigned GetArchDefaultCPUArch(unsigned ID) {
- switch (ID) {
- default:
- llvm_unreachable("Unknown ARCH kind");
- break;
-#define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
- case ARM::ID: return ARMBuildAttrs::DEFAULT_CPU_ARCH;
-#define ARM_ARCH_ALIAS(NAME, ID) /* empty */
-#include "ARMArchName.def"
- }
- return 0;
-}
-
-static const char *GetArchExtName(unsigned ID) {
- switch (ID) {
- default:
- llvm_unreachable("Unknown ARCH Extension kind");
- break;
-#define ARM_ARCHEXT_NAME(NAME, ID) \
- case ARM::ID: \
- return NAME;
-#include "ARMArchExtName.def"
- }
- return nullptr;
-}
-
namespace {
class ARMELFStreamer;
OS << "\n";
}
void ARMTargetAsmStreamer::emitArch(unsigned Arch) {
- OS << "\t.arch\t" << GetArchName(Arch) << "\n";
+ OS << "\t.arch\t" << ARMTargetParser::getArchName(Arch) << "\n";
}
void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) {
- OS << "\t.arch_extension\t" << GetArchExtName(ArchExt) << "\n";
+ OS << "\t.arch_extension\t" << ARMTargetParser::getArchExtName(ArchExt) << "\n";
}
void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) {
- OS << "\t.object_arch\t" << GetArchName(Arch) << '\n';
+ OS << "\t.object_arch\t" << ARMTargetParser::getArchName(Arch) << '\n';
}
void ARMTargetAsmStreamer::emitFPU(unsigned FPU) {
- OS << "\t.fpu\t" << GetFPUName(FPU) << "\n";
+ OS << "\t.fpu\t" << ARMTargetParser::getFPUName(FPU) << "\n";
}
void ARMTargetAsmStreamer::finishAttributeSection() {
}
void ARMTargetELFStreamer::emitArchDefaultAttributes() {
using namespace ARMBuildAttrs;
- setAttributeItem(CPU_name, GetArchDefaultCPUName(Arch), false);
+ setAttributeItem(CPU_name,
+ ARMTargetParser::getArchDefaultCPUName(Arch),
+ false);
+
if (EmittedArch == ARM::INVALID_ARCH)
- setAttributeItem(CPU_arch, GetArchDefaultCPUArch(Arch), false);
+ setAttributeItem(CPU_arch,
+ ARMTargetParser::getArchDefaultCPUArch(Arch),
+ false);
else
- setAttributeItem(CPU_arch, GetArchDefaultCPUArch(EmittedArch), false);
+ setAttributeItem(CPU_arch,
+ ARMTargetParser::getArchDefaultCPUArch(EmittedArch),
+ false);
switch (Arch) {
case ARM::ARMV2:
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