Fix segreg mov instructions.

svn path=/trunk/yasm/; revision=759

diff --git a/modules/arch/x86/tests/segmov.asm b/modules/arch/x86/tests/segmov.asm
new file mode 100644 (file)
index 0000000..4a6eb0a
--- /dev/null
+++ b/modules/arch/x86/tests/segmov.asm
@@ -0,0 +1,9 @@
+mov [0], ds
+mov word [0], ds
+mov ax, ds
+mov eax, ds
+mov ds, ax
+mov ds, eax
+mov ds, [0]
+mov ds, word [0]
+mov word ds, [0]

diff --git a/modules/arch/x86/tests/segmov.errwarn b/modules/arch/x86/tests/segmov.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/modules/arch/x86/tests/segmov.hex b/modules/arch/x86/tests/segmov.hex
new file mode 100644 (file)
index 0000000..8f5d969
--- /dev/null
+++ b/modules/arch/x86/tests/segmov.hex
@@ -0,0 +1,29 @@
+8c 
+1e 
+00 
+00 
+8c 
+1e 
+00 
+00 
+8c 
+d8 
+66 
+8c 
+d8 
+8e 
+d8 
+8e 
+d8 
+8e 
+1e 
+00 
+00 
+8e 
+1e 
+00 
+00 
+8e 
+1e 
+00 
+00 

diff --git a/modules/arch/x86/x86id.re b/modules/arch/x86/x86id.re
index 137073423c3b851fe2c2159fcd347b88b3142f57..342eb105afb689ffc9ccdd31bd04368b54ad3cfe 100644 (file)
--- a/modules/arch/x86/x86id.re
+++ b/modules/arch/x86/x86id.re
@@ -331,29 +331,18 @@ static const x86_insn_info mov_insn[] = {
     { CPU_386, 0, 32, 1, {0x8B, 0, 0}, 0, 2,
       {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
 
-    /* Need two sets here, one for strictness on left side, one for right. */
-    { CPU_Any, 0, 16, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_SegReg|OPS_16|OPA_Spare, 0} },
-    { CPU_386, 0, 32, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_SegReg|OPS_32|OPA_Spare, 0} },
+    { CPU_Any, 0, 0, 1, {0x8C, 0, 0}, 0, 2,
+      {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA,
+       OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
     { CPU_Any, 0, 16, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_16|OPA_EA, OPT_SegReg|OPS_Any|OPA_Spare, 0} },
+      {OPT_Reg|OPS_16|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
     { CPU_386, 0, 32, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_32|OPA_EA, OPT_SegReg|OPS_Any|OPA_Spare, 0} },
-    /* These allow for unspecified sized moves /to/ a segreg */
+      {OPT_Reg|OPS_32|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
     { CPU_Any, 0, 0, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_Any|OPA_EA, 0} },
+      {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare,
+       OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
     { CPU_386, 0, 0, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_Any|OPA_EA, 0} },
-    /* Need two sets here, one for strictness on left side, one for right. */
-    { CPU_Any, 0, 16, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
-    { CPU_386, 0, 32, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
-    { CPU_Any, 0, 16, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_16|OPA_EA, 0} },
-    { CPU_386, 0, 32, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_32|OPA_EA, 0} },
+      {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, 0} },
 
     { CPU_Any, 0, 0, 1, {0xB0, 0, 0}, 0, 2,
       {OPT_Reg|OPS_8|OPA_Op0Add, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },

diff --git a/src/arch/x86/tests/segmov.asm b/src/arch/x86/tests/segmov.asm
new file mode 100644 (file)
index 0000000..4a6eb0a
--- /dev/null
+++ b/src/arch/x86/tests/segmov.asm
@@ -0,0 +1,9 @@
+mov [0], ds
+mov word [0], ds
+mov ax, ds
+mov eax, ds
+mov ds, ax
+mov ds, eax
+mov ds, [0]
+mov ds, word [0]
+mov word ds, [0]

diff --git a/src/arch/x86/tests/segmov.errwarn b/src/arch/x86/tests/segmov.errwarn
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/src/arch/x86/tests/segmov.hex b/src/arch/x86/tests/segmov.hex
new file mode 100644 (file)
index 0000000..8f5d969
--- /dev/null
+++ b/src/arch/x86/tests/segmov.hex
@@ -0,0 +1,29 @@
+8c 
+1e 
+00 
+00 
+8c 
+1e 
+00 
+00 
+8c 
+d8 
+66 
+8c 
+d8 
+8e 
+d8 
+8e 
+d8 
+8e 
+1e 
+00 
+00 
+8e 
+1e 
+00 
+00 
+8e 
+1e 
+00 
+00 

diff --git a/src/arch/x86/x86id.re b/src/arch/x86/x86id.re
index 137073423c3b851fe2c2159fcd347b88b3142f57..342eb105afb689ffc9ccdd31bd04368b54ad3cfe 100644 (file)
--- a/src/arch/x86/x86id.re
+++ b/src/arch/x86/x86id.re
@@ -331,29 +331,18 @@ static const x86_insn_info mov_insn[] = {
     { CPU_386, 0, 32, 1, {0x8B, 0, 0}, 0, 2,
       {OPT_Reg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
 
-    /* Need two sets here, one for strictness on left side, one for right. */
-    { CPU_Any, 0, 16, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, OPT_SegReg|OPS_16|OPA_Spare, 0} },
-    { CPU_386, 0, 32, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, OPT_SegReg|OPS_32|OPA_Spare, 0} },
+    { CPU_Any, 0, 0, 1, {0x8C, 0, 0}, 0, 2,
+      {OPT_Mem|OPS_16|OPS_Relaxed|OPA_EA,
+       OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
     { CPU_Any, 0, 16, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_16|OPA_EA, OPT_SegReg|OPS_Any|OPA_Spare, 0} },
+      {OPT_Reg|OPS_16|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
     { CPU_386, 0, 32, 1, {0x8C, 0, 0}, 0, 2,
-      {OPT_RM|OPS_32|OPA_EA, OPT_SegReg|OPS_Any|OPA_Spare, 0} },
-    /* These allow for unspecified sized moves /to/ a segreg */
+      {OPT_Reg|OPS_32|OPA_EA, OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, 0} },
     { CPU_Any, 0, 0, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_Any|OPA_EA, 0} },
+      {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare,
+       OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
     { CPU_386, 0, 0, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_Any|OPA_EA, 0} },
-    /* Need two sets here, one for strictness on left side, one for right. */
-    { CPU_Any, 0, 16, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_16|OPA_Spare, OPT_RM|OPS_16|OPS_Relaxed|OPA_EA, 0} },
-    { CPU_386, 0, 32, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_32|OPA_Spare, OPT_RM|OPS_32|OPS_Relaxed|OPA_EA, 0} },
-    { CPU_Any, 0, 16, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_16|OPA_EA, 0} },
-    { CPU_386, 0, 32, 1, {0x8E, 0, 0}, 0, 2,
-      {OPT_SegReg|OPS_Any|OPA_Spare, OPT_RM|OPS_32|OPA_EA, 0} },
+      {OPT_SegReg|OPS_16|OPS_Relaxed|OPA_Spare, OPT_Reg|OPS_32|OPA_EA, 0} },
 
     { CPU_Any, 0, 0, 1, {0xB0, 0, 0}, 0, 2,
       {OPT_Reg|OPS_8|OPA_Op0Add, OPT_Imm|OPS_8|OPS_Relaxed|OPA_Imm, 0} },