[RISCV] Add implied zero offset load/store alias patterns

Allow load/store instructions with implied zero offset for compatibility with
GNU assembler.

Differential Revision: https://reviews.llvm.org/D57141
Patch by James Clarke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354581 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/RISCV/RISCVInstrInfo.td b/lib/Target/RISCV/RISCVInstrInfo.td
index c13bcf5be9d8dc1b1b2c6bb680f21cf3de083aa4..296e736ab10a1e683a849a43d6602a6353ec0d59 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/lib/Target/RISCV/RISCVInstrInfo.td
@@ -619,6 +619,24 @@ def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
 let EmitPriority = 0 in {
+def : InstAlias<"lb $rd, (${rs1})",
+                (LB  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lh $rd, (${rs1})",
+                (LH  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lw $rd, (${rs1})",
+                (LW  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lbu $rd, (${rs1})",
+                (LBU  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lhu $rd, (${rs1})",
+                (LHU  GPR:$rd, GPR:$rs1, 0)>;
+
+def : InstAlias<"sb $rs2, (${rs1})",
+                (SB  GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"sh $rs2, (${rs1})",
+                (SH  GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"sw $rs2, (${rs1})",
+                (SW  GPR:$rs2, GPR:$rs1, 0)>;
+
 def : InstAlias<"add $rd, $rs1, $imm12",
                 (ADDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"and $rd, $rs1, $imm12",
@@ -634,6 +652,13 @@ def : InstAlias<"srl $rd, $rs1, $shamt",
 def : InstAlias<"sra $rd, $rs1, $shamt",
                 (SRAI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
 let Predicates = [IsRV64] in {
+def : InstAlias<"lwu $rd, (${rs1})",
+                (LWU  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"ld $rd, (${rs1})",
+                (LD  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"sd $rs2, (${rs1})",
+                (SD  GPR:$rs2, GPR:$rs1, 0)>;
+
 def : InstAlias<"addw $rd, $rs1, $imm12",
                 (ADDIW  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"sllw $rd, $rs1, $shamt",

diff --git a/lib/Target/RISCV/RISCVInstrInfoC.td b/lib/Target/RISCV/RISCVInstrInfoC.td
index efb1587849fbd8ac5f5dad1d2342e50eabde9b3e..94477341eea7451de7248bb14d832dc5f1d4fbe2 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -522,6 +522,56 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> {
 
 } // Predicates = [HasStdExtC]
 
+//===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let EmitPriority = 0 in {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>;
+
+def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRC:$rs1, 0)>;
+
+def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SP:$rs1, 0)>;
+
+def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SP:$rs1, 0)>;
+
+def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SP:$rs1, 0)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/RISCV/RISCVInstrInfoD.td b/lib/Target/RISCV/RISCVInstrInfoD.td
index 1e48d24bfab5b3cad9d49c816498faf8cd9dfb8b..fdb9a41ec606890872af684a26bc62ef41a136cb 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -178,6 +178,9 @@ def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> {
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtD] in {
+def : InstAlias<"fld $rd, (${rs1})",  (FLD FPR64:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
+
 def : InstAlias<"fmv.d $rd, $rs",  (FSGNJ_D  FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;

diff --git a/lib/Target/RISCV/RISCVInstrInfoF.td b/lib/Target/RISCV/RISCVInstrInfoF.td
index c7fa72dfae113d45547a04da3d80dbc226d11a1b..17ba146730afb77910bf5e854cd0fe92d7cc541a 100644 (file)
--- a/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -206,6 +206,9 @@ def           : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtF] in {
+def : InstAlias<"flw $rd, (${rs1})",  (FLW FPR32:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
+
 def : InstAlias<"fmv.s $rd, $rs",  (FSGNJ_S  FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;

diff --git a/test/MC/RISCV/rv32fc-aliases-valid.s b/test/MC/RISCV/rv32fc-aliases-valid.s
new file mode 100644 (file)
index 0000000..19661d7
--- /dev/null
+++ b/test/MC/RISCV/rv32fc-aliases-valid.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+f < %s \
+# RUN:     | llvm-objdump -mattr=+c,+f -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+# CHECK-EXPAND: c.flw fs0, 0(s1)
+c.flw f8, (x9)
+# CHECK-EXPAND: c.fsw fs0, 0(s1)
+c.fsw f8, (x9)
+# CHECK-EXPAND: c.flwsp fs0, 0(sp)
+c.flwsp f8, (x2)
+# CHECK-EXPAND: c.fswsp fs0, 0(sp)
+c.fswsp f8, (x2)

diff --git a/test/MC/RISCV/rv32i-aliases-valid.s b/test/MC/RISCV/rv32i-aliases-valid.s
index f9866722cc16422e43eed9c4d567df27eeadfe31..e5adc3d047cf262d07f41e6093e589ed2dc158d5 100644 (file)
--- a/test/MC/RISCV/rv32i-aliases-valid.s
+++ b/test/MC/RISCV/rv32i-aliases-valid.s
@@ -104,3 +104,21 @@ rdcycleh x27
 # CHECK-INST: csrrs t3, timeh, zero
 # CHECK-ALIAS: rdtimeh t3
 rdtimeh x28
+
+# CHECK-EXPAND: lb a0, 0(a1)
+lb x10, (x11)
+# CHECK-EXPAND: lh a0, 0(a1)
+lh x10, (x11)
+# CHECK-EXPAND: lw a0, 0(a1)
+lw x10, (x11)
+# CHECK-EXPAND: lbu a0, 0(a1)
+lbu x10, (x11)
+# CHECK-EXPAND: lhu a0, 0(a1)
+lhu x10, (x11)
+
+# CHECK-EXPAND: sb a0, 0(a1)
+sb x10, (x11)
+# CHECK-EXPAND: sh a0, 0(a1)
+sh x10, (x11)
+# CHECK-EXPAND: sw a0, 0(a1)
+sw x10, (x11)

diff --git a/test/MC/RISCV/rv64c-aliases-valid.s b/test/MC/RISCV/rv64c-aliases-valid.s
index a645763c7886868e466adc7392022e588ed91830..a39527bd0e280ec4f16efbc6eca3ab4dafd8ba9e 100644 (file)
--- a/test/MC/RISCV/rv64c-aliases-valid.s
+++ b/test/MC/RISCV/rv64c-aliases-valid.s
@@ -94,3 +94,12 @@ li t3, 0x700000000B00000F
 li t4, 0x123456789abcdef0
 # CHECK-EXPAND: c.li t5, -1
 li t5, 0xFFFFFFFFFFFFFFFF
+
+# CHECK-EXPAND: c.ld s0, 0(s1)
+c.ld x8, (x9)
+# CHECK-EXPAND: c.sd s0, 0(s1)
+c.sd x8, (x9)
+# CHECK-EXPAND: c.ldsp s0, 0(sp)
+c.ldsp x8, (x2)
+# CHECK-EXPAND: c.sdsp s0, 0(sp)
+c.sdsp x8, (x2)

diff --git a/test/MC/RISCV/rv64i-aliases-valid.s b/test/MC/RISCV/rv64i-aliases-valid.s
index a705525a5a6927aeece901efaf3c12ab50384702..a53d3456d17f70b50443dd91fcfa2c2d0a355880 100644 (file)
--- a/test/MC/RISCV/rv64i-aliases-valid.s
+++ b/test/MC/RISCV/rv64i-aliases-valid.s
@@ -152,3 +152,10 @@ srlw a2,a3,4
 # CHECK-INST: sraiw a2, a3, 4
 # CHECK-ALIAS: sraiw a2, a3, 4
 sraw a2,a3,4
+
+# CHECK-EXPAND: lwu a0, 0(a1)
+lwu x10, (x11)
+# CHECK-EXPAND: ld a0, 0(a1)
+ld x10, (x11)
+# CHECK-EXPAND: sd a0, 0(a1)
+sd x10, (x11)

diff --git a/test/MC/RISCV/rvc-aliases-valid.s b/test/MC/RISCV/rvc-aliases-valid.s
new file mode 100644 (file)
index 0000000..dfafd2f
--- /dev/null
+++ b/test/MC/RISCV/rvc-aliases-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN:     | llvm-objdump -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
+# RUN:     | llvm-objdump -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+# CHECK-EXPAND: c.lw s0, 0(s1)
+c.lw x8, (x9)
+# CHECK-EXPAND: c.sw s0, 0(s1)
+c.sw x8, (x9)
+# CHECK-EXPAND: c.lwsp s0, 0(sp)
+c.lwsp x8, (x2)
+# CHECK-EXPAND: c.swsp s0, 0(sp)
+c.swsp x8, (x2)

diff --git a/test/MC/RISCV/rvd-aliases-valid.s b/test/MC/RISCV/rvd-aliases-valid.s
index 173d998b76a5ded1704cb3f02bd331398a36cf66..c1ad787bfb1c05c97f9f659fc406a2c659b702d2 100644 (file)
--- a/test/MC/RISCV/rvd-aliases-valid.s
+++ b/test/MC/RISCV/rvd-aliases-valid.s
@@ -43,6 +43,13 @@ fgt.d x4, f5, f6
 # CHECK-ALIAS: fle.d t2, fs1, fs0
 fge.d x7, f8, f9
 
+# CHECK-INST: fld ft0, 0(a0)
+# CHECK-ALIAS: fld ft0, 0(a0)
+fld f0, (x10)
+# CHECK-INST: fsd ft0, 0(a0)
+# CHECK-ALIAS: fsd ft0, 0(a0)
+fsd f0, (x10)
+
 ##===----------------------------------------------------------------------===##
 ## Aliases which omit the rounding mode.
 ##===----------------------------------------------------------------------===##

diff --git a/test/MC/RISCV/rvdc-aliases-valid.s b/test/MC/RISCV/rvdc-aliases-valid.s
new file mode 100644 (file)
index 0000000..5638f27
--- /dev/null
+++ b/test/MC/RISCV/rvdc-aliases-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+d < %s \
+# RUN:     | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+d < %s \
+# RUN:     | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+c.fld f8, (x9)
+# CHECK-EXPAND: c.fsd fs0, 0(s1)
+c.fsd f8, (x9)
+# CHECK-EXPAND: c.fldsp fs0, 0(sp)
+c.fldsp f8, (x2)
+# CHECK-EXPAND: c.fsdsp fs0, 0(sp)
+c.fsdsp f8, (x2)

diff --git a/test/MC/RISCV/rvf-aliases-valid.s b/test/MC/RISCV/rvf-aliases-valid.s
index 3307b9e03b4736c5f7cb0aa3ca1c2ca9971459b5..1d782e9cedaf2d7047ac8ebc952cc9a570a00ad5 100644 (file)
--- a/test/MC/RISCV/rvf-aliases-valid.s
+++ b/test/MC/RISCV/rvf-aliases-valid.s
@@ -94,6 +94,13 @@ fmv.x.s a2, fs7
 # CHECK-ALIAS: fmv.w.x ft1, a6
 fmv.s.x ft1, a6
 
+# CHECK-INST: flw ft0, 0(a0)
+# CHECK-ALIAS: flw ft0, 0(a0)
+flw f0, (x10)
+# CHECK-INST: fsw ft0, 0(a0)
+# CHECK-ALIAS: fsw ft0, 0(a0)
+fsw f0, (x10)
+
 ##===----------------------------------------------------------------------===##
 ## Aliases which omit the rounding mode.
 ##===----------------------------------------------------------------------===##