[MIPS GlobalISel] Select float and double phi

Select float and double phi for MIPS32.

Differential Revision: https://reviews.llvm.org/D64420

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365627 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstructionSelector.cpp b/lib/Target/Mips/MipsInstructionSelector.cpp
index b7a995529b779d5f2e9bb229ce467e56a9fcc1a7..45a47ad3c087ca79ca7023b10ccad40903af31c3 100644 (file)
--- a/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -41,6 +41,9 @@ private:
   bool materialize32BitImm(Register DestReg, APInt Imm,
                            MachineIRBuilder &B) const;
   bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  const TargetRegisterClass *
+  getRegClassForTypeOnBank(unsigned OpSize, const RegisterBank &RB,
+                           const RegisterBankInfo &RBI) const;
 
   const MipsTargetMachine &TM;
   const MipsSubtarget &STI;
@@ -104,6 +107,22 @@ bool MipsInstructionSelector::selectCopy(MachineInstr &I,
   return true;
 }
 
+const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank(
+    unsigned OpSize, const RegisterBank &RB,
+    const RegisterBankInfo &RBI) const {
+  if (RB.getID() == Mips::GPRBRegBankID)
+    return &Mips::GPR32RegClass;
+
+  if (RB.getID() == Mips::FPRBRegBankID)
+    return OpSize == 32
+               ? &Mips::FGR32RegClass
+               : STI.hasMips32r6() || STI.isFP64bit() ? &Mips::FGR64RegClass
+                                                      : &Mips::AFGR64RegClass;
+
+  llvm_unreachable("getRegClassForTypeOnBank can't find register class.");
+  return nullptr;
+}
+
 bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
                                                   MachineIRBuilder &B) const {
   assert(Imm.getBitWidth() == 32 && "Unsupported immediate size.");
@@ -262,13 +281,15 @@ bool MipsInstructionSelector::select(MachineInstr &I,
   }
   case G_PHI: {
     const Register DestReg = I.getOperand(0).getReg();
-    const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
     const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
 
-    if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
-      return false;
+    const TargetRegisterClass *DefRC = nullptr;
+    if (TargetRegisterInfo::isPhysicalRegister(DestReg))
+      DefRC = TRI.getRegClass(DestReg);
+    else
+      DefRC = getRegClassForTypeOnBank(OpSize,
+                                       *RBI.getRegBank(DestReg, MRI, TRI), RBI);
 
-    const TargetRegisterClass *DefRC = &Mips::GPR32RegClass;
     I.setDesc(TII.get(TargetOpcode::PHI));
     return RBI.constrainGenericRegister(DestReg, *DefRC, MRI);
   }

diff --git a/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir b/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
index 35dfa4e790c194d54aaf0f1f1fa794754b289f15..496756543618c520889b41728a44a73909d5b207 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
+++ b/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
@@ -1,8 +1,9 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP64
 --- |
 
-  define i32 @test_i32(i1 %cnd, i32 %a, i32 %b) {
+  define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
   entry:
     br i1 %cnd, label %cond.true, label %cond.false
 
@@ -17,34 +18,99 @@
     ret i32 %cond
   }
 
+  define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
+    ret i64 %cond
+  }
+
+  define float @phi_float(i1 %cnd, float %a, float %b) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
+    ret float %cond
+  }
+
+  define double @phi_double(double %a, double %b, i1 %cnd) {
+  entry:
+    br i1 %cnd, label %cond.true, label %cond.false
+
+  cond.true:                                        ; preds = %entry
+    br label %cond.end
+
+  cond.false:                                       ; preds = %entry
+    br label %cond.end
+
+  cond.end:                                         ; preds = %cond.false, %cond.true
+    %cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
+    ret double %cond
+  }
+
 ...
 ---
-name:            test_i32
+name:            phi_i32
 alignment:       2
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
-  ; MIPS32-LABEL: name: test_i32
-  ; MIPS32: bb.0.entry:
-  ; MIPS32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; MIPS32:   liveins: $a0, $a1, $a2
-  ; MIPS32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
-  ; MIPS32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
-  ; MIPS32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
-  ; MIPS32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
-  ; MIPS32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
-  ; MIPS32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
-  ; MIPS32:   J %bb.2, implicit-def $at
-  ; MIPS32: bb.1.cond.true:
-  ; MIPS32:   successors: %bb.3(0x80000000)
-  ; MIPS32:   J %bb.3, implicit-def $at
-  ; MIPS32: bb.2.cond.false:
-  ; MIPS32:   successors: %bb.3(0x80000000)
-  ; MIPS32: bb.3.cond.end:
-  ; MIPS32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
-  ; MIPS32:   $v0 = COPY [[PHI]]
-  ; MIPS32:   RetRA implicit $v0
+  ; MIPS32FP32-LABEL: name: phi_i32
+  ; MIPS32FP32: bb.0.entry:
+  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP32:   liveins: $a0, $a1, $a2
+  ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+  ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   J %bb.2, implicit-def $at
+  ; MIPS32FP32: bb.1.cond.true:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32:   J %bb.3, implicit-def $at
+  ; MIPS32FP32: bb.2.cond.false:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32: bb.3.cond.end:
+  ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
+  ; MIPS32FP32:   $v0 = COPY [[PHI]]
+  ; MIPS32FP32:   RetRA implicit $v0
+  ; MIPS32FP64-LABEL: name: phi_i32
+  ; MIPS32FP64: bb.0.entry:
+  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP64:   liveins: $a0, $a1, $a2
+  ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+  ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   J %bb.2, implicit-def $at
+  ; MIPS32FP64: bb.1.cond.true:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64:   J %bb.3, implicit-def $at
+  ; MIPS32FP64: bb.2.cond.false:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64: bb.3.cond.end:
+  ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[COPY2]], %bb.2
+  ; MIPS32FP64:   $v0 = COPY [[PHI]]
+  ; MIPS32FP64:   RetRA implicit $v0
   bb.1.entry:
     liveins: $a0, $a1, $a2
 
@@ -68,3 +134,239 @@ body:             |
     RetRA implicit $v0
 
 ...
+---
+name:            phi_i64
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 20, size: 4, alignment: 4, isImmutable: true }
+  - { id: 1, offset: 16, size: 4, alignment: 8, isImmutable: true }
+body:             |
+  ; MIPS32FP32-LABEL: name: phi_i64
+  ; MIPS32FP32: bb.0.entry:
+  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP32:   liveins: $a0, $a2, $a3
+  ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+  ; MIPS32FP32:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
+  ; MIPS32FP32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
+  ; MIPS32FP32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
+  ; MIPS32FP32:   [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
+  ; MIPS32FP32:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
+  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   J %bb.2, implicit-def $at
+  ; MIPS32FP32: bb.1.cond.true:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32:   J %bb.3, implicit-def $at
+  ; MIPS32FP32: bb.2.cond.false:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32: bb.3.cond.end:
+  ; MIPS32FP32:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
+  ; MIPS32FP32:   [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
+  ; MIPS32FP32:   $v0 = COPY [[PHI]]
+  ; MIPS32FP32:   $v1 = COPY [[PHI1]]
+  ; MIPS32FP32:   RetRA implicit $v0, implicit $v1
+  ; MIPS32FP64-LABEL: name: phi_i64
+  ; MIPS32FP64: bb.0.entry:
+  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP64:   liveins: $a0, $a2, $a3
+  ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a2
+  ; MIPS32FP64:   [[COPY2:%[0-9]+]]:gpr32 = COPY $a3
+  ; MIPS32FP64:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
+  ; MIPS32FP64:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
+  ; MIPS32FP64:   [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
+  ; MIPS32FP64:   [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu1]], 0 :: (load 4 from %fixed-stack.1)
+  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   J %bb.2, implicit-def $at
+  ; MIPS32FP64: bb.1.cond.true:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64:   J %bb.3, implicit-def $at
+  ; MIPS32FP64: bb.2.cond.false:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64: bb.3.cond.end:
+  ; MIPS32FP64:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY1]], %bb.1, [[LW]], %bb.2
+  ; MIPS32FP64:   [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY2]], %bb.1, [[LW1]], %bb.2
+  ; MIPS32FP64:   $v0 = COPY [[PHI]]
+  ; MIPS32FP64:   $v1 = COPY [[PHI1]]
+  ; MIPS32FP64:   RetRA implicit $v0, implicit $v1
+  bb.1.entry:
+    liveins: $a0, $a2, $a3
+
+    %3:gprb(s32) = COPY $a0
+    %4:gprb(s32) = COPY $a2
+    %5:gprb(s32) = COPY $a3
+    %8:gprb(p0) = G_FRAME_INDEX %fixed-stack.1
+    %6:gprb(s32) = G_LOAD %8(p0) :: (load 4 from %fixed-stack.1, align 8)
+    %9:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
+    %7:gprb(s32) = G_LOAD %9(p0) :: (load 4 from %fixed-stack.0)
+    %14:gprb(s32) = G_CONSTANT i32 1
+    %15:gprb(s32) = COPY %3(s32)
+    %13:gprb(s32) = G_AND %15, %14
+    G_BRCOND %13(s32), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %20:gprb(s32) = G_PHI %4(s32), %bb.2, %6(s32), %bb.3
+    %21:gprb(s32) = G_PHI %5(s32), %bb.2, %7(s32), %bb.3
+    $v0 = COPY %20(s32)
+    $v1 = COPY %21(s32)
+    RetRA implicit $v0, implicit $v1
+
+...
+---
+name:            phi_float
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; MIPS32FP32-LABEL: name: phi_float
+  ; MIPS32FP32: bb.0.entry:
+  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP32:   liveins: $a0, $a1, $a2
+  ; MIPS32FP32:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32FP32:   [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
+  ; MIPS32FP32:   [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
+  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   J %bb.2, implicit-def $at
+  ; MIPS32FP32: bb.1.cond.true:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32:   J %bb.3, implicit-def $at
+  ; MIPS32FP32: bb.2.cond.false:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32: bb.3.cond.end:
+  ; MIPS32FP32:   [[PHI:%[0-9]+]]:fgr32 = PHI [[MTC1_]], %bb.1, [[MTC1_1]], %bb.2
+  ; MIPS32FP32:   $f0 = COPY [[PHI]]
+  ; MIPS32FP32:   RetRA implicit $f0
+  ; MIPS32FP64-LABEL: name: phi_float
+  ; MIPS32FP64: bb.0.entry:
+  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP64:   liveins: $a0, $a1, $a2
+  ; MIPS32FP64:   [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+  ; MIPS32FP64:   [[MTC1_:%[0-9]+]]:fgr32 = MTC1 $a1
+  ; MIPS32FP64:   [[MTC1_1:%[0-9]+]]:fgr32 = MTC1 $a2
+  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[COPY]], [[ORi]]
+  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   J %bb.2, implicit-def $at
+  ; MIPS32FP64: bb.1.cond.true:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64:   J %bb.3, implicit-def $at
+  ; MIPS32FP64: bb.2.cond.false:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64: bb.3.cond.end:
+  ; MIPS32FP64:   [[PHI:%[0-9]+]]:fgr32 = PHI [[MTC1_]], %bb.1, [[MTC1_1]], %bb.2
+  ; MIPS32FP64:   $f0 = COPY [[PHI]]
+  ; MIPS32FP64:   RetRA implicit $f0
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    %3:gprb(s32) = COPY $a0
+    %1:fgr32(s32) = MTC1 $a1
+    %2:fgr32(s32) = MTC1 $a2
+    %6:gprb(s32) = G_CONSTANT i32 1
+    %7:gprb(s32) = COPY %3(s32)
+    %5:gprb(s32) = G_AND %7, %6
+    G_BRCOND %5(s32), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %4:fprb(s32) = G_PHI %1(s32), %bb.2, %2(s32), %bb.3
+    $f0 = COPY %4(s32)
+    RetRA implicit $f0
+
+...
+---
+name:            phi_double
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+fixedStack:
+  - { id: 0, offset: 16, size: 4, alignment: 8, isImmutable: true }
+body:             |
+  ; MIPS32FP32-LABEL: name: phi_double
+  ; MIPS32FP32: bb.0.entry:
+  ; MIPS32FP32:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP32:   liveins: $d6, $d7
+  ; MIPS32FP32:   [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+  ; MIPS32FP32:   [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
+  ; MIPS32FP32:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
+  ; MIPS32FP32:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
+  ; MIPS32FP32:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP32:   [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
+  ; MIPS32FP32:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP32:   J %bb.2, implicit-def $at
+  ; MIPS32FP32: bb.1.cond.true:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32:   J %bb.3, implicit-def $at
+  ; MIPS32FP32: bb.2.cond.false:
+  ; MIPS32FP32:   successors: %bb.3(0x80000000)
+  ; MIPS32FP32: bb.3.cond.end:
+  ; MIPS32FP32:   [[PHI:%[0-9]+]]:afgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
+  ; MIPS32FP32:   $d0 = COPY [[PHI]]
+  ; MIPS32FP32:   RetRA implicit $d0
+  ; MIPS32FP64-LABEL: name: phi_double
+  ; MIPS32FP64: bb.0.entry:
+  ; MIPS32FP64:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; MIPS32FP64:   liveins: $d6, $d7
+  ; MIPS32FP64:   [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+  ; MIPS32FP64:   [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
+  ; MIPS32FP64:   [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
+  ; MIPS32FP64:   [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 8)
+  ; MIPS32FP64:   [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
+  ; MIPS32FP64:   [[AND:%[0-9]+]]:gpr32 = AND [[LW]], [[ORi]]
+  ; MIPS32FP64:   BNE [[AND]], $zero, %bb.1, implicit-def $at
+  ; MIPS32FP64:   J %bb.2, implicit-def $at
+  ; MIPS32FP64: bb.1.cond.true:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64:   J %bb.3, implicit-def $at
+  ; MIPS32FP64: bb.2.cond.false:
+  ; MIPS32FP64:   successors: %bb.3(0x80000000)
+  ; MIPS32FP64: bb.3.cond.end:
+  ; MIPS32FP64:   [[PHI:%[0-9]+]]:fgr64 = PHI [[COPY]], %bb.1, [[COPY1]], %bb.2
+  ; MIPS32FP64:   $d0 = COPY [[PHI]]
+  ; MIPS32FP64:   RetRA implicit $d0
+  bb.1.entry:
+    liveins: $d6, $d7
+
+    %0:fprb(s64) = COPY $d6
+    %1:fprb(s64) = COPY $d7
+    %4:gprb(p0) = G_FRAME_INDEX %fixed-stack.0
+    %3:gprb(s32) = G_LOAD %4(p0) :: (load 4 from %fixed-stack.0, align 8)
+    %7:gprb(s32) = G_CONSTANT i32 1
+    %8:gprb(s32) = COPY %3(s32)
+    %6:gprb(s32) = G_AND %8, %7
+    G_BRCOND %6(s32), %bb.2
+    G_BR %bb.3
+
+  bb.2.cond.true:
+    G_BR %bb.4
+
+  bb.3.cond.false:
+
+  bb.4.cond.end:
+    %5:fprb(s64) = G_PHI %0(s64), %bb.2, %1(s64), %bb.3
+    $d0 = COPY %5(s64)
+    RetRA implicit $d0
+
+...

diff --git a/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll b/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
index fa2196ea3cd145ee7de158da587ebaec51a555f1..01985efded2858bee4ade99cd603b27b3914b831 100644 (file)
--- a/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
+++ b/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
@@ -221,3 +221,89 @@ cond.end:
   %cond = phi i64 [ %a, %cond.true ], [ %b, %cond.false ]
   ret i64 %cond
 }
+
+define float @phi_float(i1 %cnd, float %a, float %b) {
+; MIPS32-LABEL: phi_float:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -16
+; MIPS32-NEXT:    .cfi_def_cfa_offset 16
+; MIPS32-NEXT:    mtc1 $5, $f0
+; MIPS32-NEXT:    mtc1 $6, $f1
+; MIPS32-NEXT:    ori $1, $zero, 1
+; MIPS32-NEXT:    and $1, $4, $1
+; MIPS32-NEXT:    swc1 $f0, 12($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    swc1 $f1, 8($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    bnez $1, $BB5_2
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  # %bb.1: # %entry
+; MIPS32-NEXT:    j $BB5_3
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB5_2: # %cond.true
+; MIPS32-NEXT:    lwc1 $f0, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    swc1 $f0, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:    j $BB5_4
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB5_3: # %cond.false
+; MIPS32-NEXT:    lwc1 $f0, 8($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    swc1 $f0, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT:  $BB5_4: # %cond.end
+; MIPS32-NEXT:    lwc1 $f0, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 16
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  br i1 %cnd, label %cond.true, label %cond.false
+
+cond.true:
+  br label %cond.end
+
+cond.false:
+  br label %cond.end
+
+cond.end:
+  %cond = phi float [ %a, %cond.true ], [ %b, %cond.false ]
+  ret float %cond
+}
+
+define double @phi_double(double %a, double %b, i1 %cnd) {
+; MIPS32-LABEL: phi_double:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    addiu $sp, $sp, -24
+; MIPS32-NEXT:    .cfi_def_cfa_offset 24
+; MIPS32-NEXT:    addiu $1, $sp, 40
+; MIPS32-NEXT:    lw $1, 0($1)
+; MIPS32-NEXT:    ori $2, $zero, 1
+; MIPS32-NEXT:    and $1, $1, $2
+; MIPS32-NEXT:    sdc1 $f12, 16($sp) # 8-byte Folded Spill
+; MIPS32-NEXT:    sdc1 $f14, 8($sp) # 8-byte Folded Spill
+; MIPS32-NEXT:    bnez $1, $BB6_2
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  # %bb.1: # %entry
+; MIPS32-NEXT:    j $BB6_3
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB6_2: # %cond.true
+; MIPS32-NEXT:    ldc1 $f0, 16($sp) # 8-byte Folded Reload
+; MIPS32-NEXT:    sdc1 $f0, 0($sp) # 8-byte Folded Spill
+; MIPS32-NEXT:    j $BB6_4
+; MIPS32-NEXT:    nop
+; MIPS32-NEXT:  $BB6_3: # %cond.false
+; MIPS32-NEXT:    ldc1 $f0, 8($sp) # 8-byte Folded Reload
+; MIPS32-NEXT:    sdc1 $f0, 0($sp) # 8-byte Folded Spill
+; MIPS32-NEXT:  $BB6_4: # %cond.end
+; MIPS32-NEXT:    ldc1 $f0, 0($sp) # 8-byte Folded Reload
+; MIPS32-NEXT:    addiu $sp, $sp, 24
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  br i1 %cnd, label %cond.true, label %cond.false
+
+cond.true:
+  br label %cond.end
+
+cond.false:
+  br label %cond.end
+
+cond.end:
+  %cond = phi double [ %a, %cond.true ], [ %b, %cond.false ]
+  ret double %cond
+}