Reviewers: RKSimon
Subscribers: llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D29076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292924
91177308-0d34-0410-b5e6-
96231b3b80d8
// Out of range logical bit shifts are guaranteed to be zero.
// Out of range arithmetic bit shifts splat the sign bit.
APInt ShiftVal = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
- if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt))
+ if (ShiftVal.zextOrTrunc(8).uge(NumBitsPerElt)) {
if (LogicalShift)
return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(N));
else
ShiftVal = NumBitsPerElt - 1;
+ }
SDValue N0 = N->getOperand(0);