Merging r300429:

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r300429 | d0k | 2017-04-16 16:13:08 -0400 (Sun, 16 Apr 2017) | 7 lines

[X86] Remove special handling for 16 bit for A asm constraints.

Our 16 bit support is assembler-only + the terrible hack that is
.code16gcc. Simply using 32 bit registers does the right thing for the
latter.

Fixes PR32681.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@301437 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 0f376eb6e74abbd6c4c2f508ea5ed1bd9ba53914..de6c9a67ed850e4cb2dc0c0855a3bcd785858a1b 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -34722,14 +34722,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       if (Subtarget.is64Bit()) {
         Res.first = X86::RAX;
         Res.second = &X86::GR64_ADRegClass;
-      } else if (Subtarget.is32Bit()) {
+      } else {
+        assert((Subtarget.is32Bit() || Subtarget.is16Bit()) &&
+               "Expecting 64, 32 or 16 bit subtarget");
         Res.first = X86::EAX;
         Res.second = &X86::GR32_ADRegClass;
-      } else if (Subtarget.is16Bit()) {
-        Res.first = X86::AX;
-        Res.second = &X86::GR16_ADRegClass;
-      } else {
-        llvm_unreachable("Expecting 64, 32 or 16 bit subtarget");
       }
       return Res;
     }

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index a1172134c8637ac0563227d61bf84ac711a5e530..ad02a940f22c7b42aafe8bd6d1768d0a5e7ab3ef 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -438,7 +438,6 @@ def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32,
                                           (add LOW32_ADDR_ACCESS, RBP)>;
 
 // A class to support the 'A' assembler constraint: [ER]AX then [ER]DX.
-def GR16_AD : RegisterClass<"X86", [i16], 16, (add AX, DX)>;
 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
 

diff --git a/test/CodeGen/X86/x86-16.ll b/test/CodeGen/X86/x86-16.ll
index 775b2c447bbdb59a15d4da93433e20e6dd77764d..55b53a8047c514fa5a50e1114c47c781b3747e8b 100644 (file)
--- a/test/CodeGen/X86/x86-16.ll
+++ b/test/CodeGen/X86/x86-16.ll
@@ -12,9 +12,16 @@ define i32 @main() #0 {
 ; CHECK: .code16
 ; CHECK-LABEL: main
 
+define i64 @foo(i32 %index) #0 {
+  %asm = tail call i64 asm "rdmsr", "=A,{cx},~{dirflag},~{fpsr},~{flags}"(i32 %index)
+  ret i64 %asm
+}
+
+; CHECK-LABEL: foo
+; CHECK: rdmsr
 
 attributes #0 = { nounwind }
 
 !llvm.ident = !{!0}
 
-!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}
\ No newline at end of file
+!0 = !{!"clang version 3.9.0 (trunk 265439) (llvm/trunk 265567)"}