--- /dev/null
+\r
+/*----------------------------------------------------------------------------\r
+| One of the macros `BIGENDIAN' or `LITTLEENDIAN' must be defined.\r
+*----------------------------------------------------------------------------*/\r
+#define LITTLEENDIAN\r
+\r
+/*----------------------------------------------------------------------------\r
+| The macro `BITS64' can be defined to indicate that 64-bit integer types are\r
+| supported by the compiler.\r
+*----------------------------------------------------------------------------*/\r
+#define BITS64\r
+\r
+/*----------------------------------------------------------------------------\r
+| Each of the following `typedef's defines the most convenient type that holds\r
+| integers of at least as many bits as specified. For example, `uint8' should\r
+| be the most convenient type that can hold unsigned integers of as many as\r
+| 8 bits. The `flag' type must be able to hold either a 0 or 1. For most\r
+| implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed\r
+| to the same as `int'.\r
+*----------------------------------------------------------------------------*/\r
+typedef char flag;\r
+typedef unsigned char uint8;\r
+typedef signed char int8;\r
+typedef int uint16;\r
+typedef int int16;\r
+typedef unsigned int uint32;\r
+typedef signed int int32;\r
+#ifdef BITS64\r
+typedef unsigned long long int uint64;\r
+typedef signed long long int int64;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Each of the following `typedef's defines a type that holds integers\r
+| of _exactly_ the number of bits specified. For instance, for most\r
+| implementation of C, `bits16' and `sbits16' should be `typedef'ed to\r
+| `unsigned short int' and `signed short int' (or `short int'), respectively.\r
+*----------------------------------------------------------------------------*/\r
+typedef unsigned char bits8;\r
+typedef signed char sbits8;\r
+typedef unsigned short int bits16;\r
+typedef signed short int sbits16;\r
+typedef unsigned int bits32;\r
+typedef signed int sbits32;\r
+#ifdef BITS64\r
+typedef unsigned long long int bits64;\r
+typedef signed long long int sbits64;\r
+#endif\r
+\r
+#ifdef BITS64\r
+/*----------------------------------------------------------------------------\r
+| The `LIT64' macro takes as its argument a textual integer literal and\r
+| if necessary ``marks'' the literal as having a 64-bit integer type.\r
+| For example, the GNU C Compiler (`gcc') requires that 64-bit literals be\r
+| appended with the letters `LL' standing for `long long', which is `gcc's\r
+| name for the 64-bit integer type. Some compilers may allow `LIT64' to be\r
+| defined as the identity macro: `#define LIT64( a ) a'.\r
+*----------------------------------------------------------------------------*/\r
+#define LIT64( a ) a##LL\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| The macro `INLINE' can be used before functions that should be inlined. If\r
+| a compiler does not support explicit inlining, this macro should be defined\r
+| to be `static'.\r
+*----------------------------------------------------------------------------*/\r
+#define INLINE extern inline\r
+\r
--- /dev/null
+
+/*----------------------------------------------------------------------------
+| One of the macros `BIGENDIAN' or `LITTLEENDIAN' must be defined.
+*----------------------------------------------------------------------------*/
+#define BIGENDIAN
+
+/*----------------------------------------------------------------------------
+| The macro `BITS64' can be defined to indicate that 64-bit integer types are
+| supported by the compiler.
+*----------------------------------------------------------------------------*/
+#define BITS64
+
+/*----------------------------------------------------------------------------
+| Each of the following `typedef's defines the most convenient type that holds
+| integers of at least as many bits as specified. For example, `uint8' should
+| be the most convenient type that can hold unsigned integers of as many as
+| 8 bits. The `flag' type must be able to hold either a 0 or 1. For most
+| implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed
+| to the same as `int'.
+*----------------------------------------------------------------------------*/
+typedef int flag;
+typedef int uint8;
+typedef int int8;
+typedef int uint16;
+typedef int int16;
+typedef unsigned int uint32;
+typedef signed int int32;
+#ifdef BITS64
+typedef unsigned long long int uint64;
+typedef signed long long int int64;
+#endif
+
+/*----------------------------------------------------------------------------
+| Each of the following `typedef's defines a type that holds integers
+| of _exactly_ the number of bits specified. For instance, for most
+| implementation of C, `bits16' and `sbits16' should be `typedef'ed to
+| `unsigned short int' and `signed short int' (or `short int'), respectively.
+*----------------------------------------------------------------------------*/
+typedef unsigned char bits8;
+typedef signed char sbits8;
+typedef unsigned short int bits16;
+typedef signed short int sbits16;
+typedef unsigned int bits32;
+typedef signed int sbits32;
+#ifdef BITS64
+typedef unsigned long long int bits64;
+typedef signed long long int sbits64;
+#endif
+
+#ifdef BITS64
+/*----------------------------------------------------------------------------
+| The `LIT64' macro takes as its argument a textual integer literal and
+| if necessary ``marks'' the literal as having a 64-bit integer type.
+| For example, the GNU C Compiler (`gcc') requires that 64-bit literals be
+| appended with the letters `LL' standing for `long long', which is `gcc's
+| name for the 64-bit integer type. Some compilers may allow `LIT64' to be
+| defined as the identity macro: `#define LIT64( a ) a'.
+*----------------------------------------------------------------------------*/
+#define LIT64( a ) a##LL
+#endif
+
+/*----------------------------------------------------------------------------
+| The macro `INLINE' can be used before functions that should be inlined. If
+| a compiler does not support explicit inlining, this macro should be defined
+| to be `static'.
+*----------------------------------------------------------------------------*/
+#define INLINE extern inline
+
--- /dev/null
+\r
+Package Overview for SoftFloat Release 2b\r
+\r
+John R. Hauser\r
+2002 May 27\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Overview\r
+\r
+SoftFloat is a software implementation of floating-point that conforms to\r
+the IEC/IEEE Standard for Binary Floating-Point Arithmetic. SoftFloat is\r
+distributed in the form of C source code. Compiling the SoftFloat sources\r
+generates two things:\r
+\r
+-- A SoftFloat object file (typically `softfloat.o') containing the complete\r
+ set of IEC/IEEE floating-point routines.\r
+\r
+-- A `timesoftfloat' program for evaluating the speed of the SoftFloat\r
+ routines. (The SoftFloat module is linked into this program.)\r
+\r
+The SoftFloat package is documented in four text files:\r
+\r
+ SoftFloat.txt Documentation for using the SoftFloat functions.\r
+ SoftFloat-source.txt Documentation for compiling SoftFloat.\r
+ SoftFloat-history.txt History of major changes to SoftFloat.\r
+ timesoftfloat.txt Documentation for using `timesoftfloat'.\r
+\r
+Other files in the package comprise the source code for SoftFloat.\r
+\r
+Please be aware that some work is involved in porting this software to other\r
+targets. It is not just a matter of getting `make' to complete without\r
+error messages. I would have written the code that way if I could, but\r
+there are fundamental differences between systems that can't be hidden.\r
+You should not attempt to compile SoftFloat without first reading both\r
+`SoftFloat.txt' and `SoftFloat-source.txt'.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Legal Notice\r
+\r
+SoftFloat was written by me, John R. Hauser. This work was made possible in\r
+part by the International Computer Science Institute, located at Suite 600,\r
+1947 Center Street, Berkeley, California 94704. Funding was partially\r
+provided by the National Science Foundation under grant MIP-9311980. The\r
+original version of this code was written as part of a project to build\r
+a fixed-point vector processor in collaboration with the University of\r
+California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort\r
+has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT\r
+TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO\r
+PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL\r
+LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO\r
+FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER\r
+SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE\r
+SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, provided\r
+that the minimal documentation requirements stated in the source code are\r
+satisfied.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Contact Information\r
+\r
+At the time of this writing, the most up-to-date information about\r
+SoftFloat and the latest release can be found at the Web page `http://\r
+www.cs.berkeley.edu/~jhauser/arithmetic/SoftFloat.html'.\r
+\r
+\r
--- /dev/null
+\r
+History of Major Changes to SoftFloat, up to Release 2b\r
+\r
+John R. Hauser\r
+2002 May 27\r
+\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Release 2b (2002 May)\r
+\r
+-- Made minor updates to the documentation, including improved wording of\r
+ the legal restrictions on using SoftFloat.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Release 2a (1998 December)\r
+\r
+-- Added functions to convert between 64-bit integers (int64) and all\r
+ supported floating-point formats.\r
+\r
+-- Fixed a bug in all 64-bit-version square root functions except\r
+ `float32_sqrt' that caused the result sometimes to be off by 1 unit in\r
+ the last place (1 ulp) from what it should be. (Bug discovered by Paul\r
+ Donahue.)\r
+\r
+-- Improved the makefiles.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Release 2 (1997 June)\r
+\r
+-- Created the 64-bit (bits64) version, adding the floatx80 and float128\r
+ formats.\r
+\r
+-- Changed the source directory structure, splitting the sources into a\r
+ `bits32' and a `bits64' version. Renamed `environment.h' to `milieu.h'\r
+ to avoid confusion with environment variables.\r
+\r
+-- Fixed a small error that caused `float64_round_to_int' often to round the\r
+ wrong way in nearest/even mode when the operand was between 2^20 and 2^21\r
+ and halfway between two integers.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Release 1a (1996 July)\r
+\r
+-- Corrected a mistake that caused borderline underflow cases not to raise\r
+ the underflow flag when they should have. (Problem reported by Doug\r
+ Priest.)\r
+\r
+-- Added the `float_detect_tininess' variable to control whether tininess is\r
+ detected before or after rounding.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Release 1 (1996 July)\r
+\r
+-- Original release.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+\r
--- /dev/null
+\r
+SoftFloat Release 2b Source Documentation\r
+\r
+John R. Hauser\r
+2002 May 27\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Introduction\r
+\r
+SoftFloat is a software implementation of floating-point that conforms to\r
+the IEC/IEEE Standard for Binary Floating-Point Arithmetic. SoftFloat can\r
+support four floating-point formats: single precision, double precision,\r
+extended double precision, and quadruple precision. All operations required\r
+by the IEEE Standard are implemented, except for conversions to and from\r
+decimal. SoftFloat is distributed in the form of C source code, so a\r
+C compiler is needed to compile the code. Support for the extended double-\r
+precision and quadruple-precision formats is dependent on the C compiler\r
+implementing a 64-bit integer type.\r
+\r
+This document gives information needed for compiling and/or porting\r
+SoftFloat.\r
+\r
+The source code for SoftFloat is intended to be relatively machine-\r
+independent and should be compilable using most any ISO/ANSI C compiler. At\r
+the time of this writing, SoftFloat has been successfully compiled with the\r
+GNU C Compiler (`gcc') for several platforms.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Limitations\r
+\r
+As supplied, SoftFloat requires an ISO/ANSI-style C compiler. No attempt\r
+has been made to accomodate compilers that are not ISO-conformant. Older\r
+``K&R-style'' compilers are not adequate for compiling SoftFloat. All\r
+testing I have done so far has been with the GNU C Compiler. Compilation\r
+with other compilers should be possible but has not been tested by me.\r
+\r
+The SoftFloat sources assume that source code file names can be longer than\r
+8 characters. In order to compile under an MS-DOS-type system, many of the\r
+source files will need to be renamed, and the source and makefiles edited\r
+appropriately. Once compiled, the SoftFloat binary does not depend on the\r
+existence of long file names.\r
+\r
+The underlying machine is assumed to be binary with a word size that is a\r
+power of 2. Bytes are 8 bits. Arithmetic on signed integers must modularly\r
+wrap around on overflows (as is already required for unsigned integers\r
+in C).\r
+\r
+Support for the extended double-precision and quadruple-precision formats\r
+depends on the C compiler implementing a 64-bit integer type. If the\r
+largest integer type supported by the C compiler is 32 bits, SoftFloat is\r
+limited to the single- and double-precision formats.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Contents\r
+\r
+ Introduction\r
+ Limitations\r
+ Contents\r
+ Legal Notice\r
+ SoftFloat Source Directory Structure\r
+ SoftFloat Source Files\r
+ processors/*.h\r
+ softfloat/bits*/*/softfloat.h\r
+ softfloat/bits*/*/milieu.h\r
+ softfloat/bits*/*/softfloat-specialize\r
+ softfloat/bits*/softfloat-macros\r
+ softfloat/bits*/softfloat.c\r
+ Steps to Creating a `softfloat.o'\r
+ Making `softfloat.o' a Library\r
+ Testing SoftFloat\r
+ Timing SoftFloat\r
+ Compiler Options and Efficiency\r
+ Processor-Specific Optimization of `softfloat.c' Using `softfloat-macros'\r
+ Contact Information\r
+\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Legal Notice\r
+\r
+SoftFloat was written by John R. Hauser. This work was made possible in\r
+part by the International Computer Science Institute, located at Suite 600,\r
+1947 Center Street, Berkeley, California 94704. Funding was partially\r
+provided by the National Science Foundation under grant MIP-9311980. The\r
+original version of this code was written as part of a project to build\r
+a fixed-point vector processor in collaboration with the University of\r
+California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort\r
+has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT\r
+TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO\r
+PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL\r
+LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO\r
+FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER\r
+SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE\r
+SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, provided\r
+that the minimal documentation requirements stated in the source code are\r
+satisfied.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+SoftFloat Source Directory Structure\r
+\r
+Because SoftFloat is targeted to multiple platforms, its source code\r
+is slightly scattered between target-specific and target-independent\r
+directories and files. The directory structure is as follows:\r
+\r
+ processors\r
+ softfloat\r
+ bits64\r
+ templates\r
+ 386-Win32-GCC\r
+ SPARC-Solaris-GCC\r
+ bits32\r
+ templates\r
+ 386-Win32-GCC\r
+ SPARC-Solaris-GCC\r
+\r
+The two topmost directories and their contents are:\r
+\r
+ softfloat - Most of the source code needed for SoftFloat.\r
+ processors - Target-specific header files that are not specific to\r
+ SoftFloat.\r
+\r
+The `softfloat' directory is further split into two parts:\r
+\r
+ bits64 - SoftFloat implementation using 64-bit integers.\r
+ bits32 - SoftFloat implementation using only 32-bit integers.\r
+\r
+Within these directories are subdirectories for each of the targeted\r
+platforms. The SoftFloat source code is distributed with targets\r
+`386-Win32-GCC' and `SPARC-Solaris-GCC' (and perhaps others) already\r
+prepared for both the 32-bit and 64-bit implementations. Source files that\r
+are not within these target-specific subdirectories are intended to be\r
+target-independent.\r
+\r
+The naming convention used for the target-specific directories is\r
+`<processor>-<executable-type>-<compiler>'. The names of the supplied\r
+target directories should be interpreted as follows:\r
+\r
+ <processor>:\r
+ 386 - Intel 386-compatible processor.\r
+ SPARC - SPARC processor (as used by Sun computers).\r
+ <executable-type>:\r
+ Win32 - Microsoft Win32 executable.\r
+ Solaris - Sun Solaris executable.\r
+ <compiler>:\r
+ GCC - GNU C Compiler.\r
+\r
+You do not need to maintain this convention if you do not want to.\r
+\r
+Alongside the supplied target-specific directories is a `templates'\r
+directory containing a set of ``generic'' target-specific source files. A\r
+new target directory can be created by copying the `templates' directory and\r
+editing the files inside. (Complete instructions for porting SoftFloat to a\r
+new target are in the section _Steps to Creating a `softfloat.o'_.) Note\r
+that the `templates' directory will not work as a target directory without\r
+some editing. To avoid confusion, it would be wise to refrain from editing\r
+the files inside `templates' directly.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+SoftFloat Source Files\r
+\r
+The purpose of each source file is described below. In the following,\r
+the `*' symbol is used in place of the name of a specific target, such as\r
+`386-Win32-GCC' or `SPARC-Solaris-GCC', or in place of some other text, as\r
+in `bits*' for either `bits32' or `bits64'.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+processors/*.h\r
+\r
+The target-specific `processors' header file defines integer types\r
+of various sizes, and also defines certain C preprocessor macros that\r
+characterize the target. The two examples supplied are `386-GCC.h' and\r
+`SPARC-GCC.h'. The naming convention used for processor header files is\r
+`<processor>-<compiler>.h'.\r
+\r
+If 64-bit integers are supported by the compiler, the macro name `BITS64'\r
+should be defined here along with the corresponding 64-bit integer\r
+types. In addition, the function-like macro `LIT64' must be defined for\r
+constructing 64-bit integer literals (constants). The `LIT64' macro is used\r
+consistently in the SoftFloat code to annotate 64-bit literals.\r
+\r
+If `BITS64' is not defined, only the 32-bit version of SoftFloat can be\r
+compiled. If `BITS64' _is_ defined, either can be compiled.\r
+\r
+If an inlining attribute (such as an `inline' keyword) is provided by the\r
+compiler, the macro `INLINE' should be defined to the appropriate keyword.\r
+If not, `INLINE' can be set to the keyword `static'. The `INLINE' macro\r
+appears in the SoftFloat source code before every function that should\r
+be inlined by the compiler. SoftFloat depends on inlining to obtain\r
+good speed. Even if inlining cannot be forced with a language keyword,\r
+the compiler may still be able to perform inlining on its own as an\r
+optimization. If a command-line option is needed to convince the compiler\r
+to perform this optimization, this should be assured in the makefile. (See\r
+the section _Compiler Options and Efficiency_ below.)\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+softfloat/bits*/*/softfloat.h\r
+\r
+The target-specific `softfloat.h' header file defines the SoftFloat\r
+interface as seen by clients.\r
+\r
+Unlike the actual function definitions in `softfloat.c', the declarations\r
+in `softfloat.h' do not use any of the types defined by the `processors'\r
+header file. This is done so that clients will not have to include the\r
+`processors' header file in order to use SoftFloat. Nevertheless, the\r
+target-specific declarations in `softfloat.h' must match what `softfloat.c'\r
+expects. For example, if `int32' is defined as `int' in the `processors'\r
+header file, then in `softfloat.h' the output of `float32_to_int32' should\r
+be stated as `int', although in `softfloat.c' it is given in target-\r
+independent form as `int32'.\r
+\r
+For the `bits64' implementation of SoftFloat, the macro names `FLOATX80' and\r
+`FLOAT128' must be defined in order for the extended double-precision and\r
+quadruple-precision formats to be enabled in the code. Conversely, either\r
+or both of the extended formats can be disabled by simply removing the\r
+`#define' of the respective macro. When an extended format is not enabled,\r
+none of the functions that either input or output the format are defined,\r
+and no space is taken up in `softfloat.o' by such functions. There is no\r
+provision for disabling the usual single- and double-precision formats.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+softfloat/bits*/*/milieu.h\r
+\r
+The target-specific `milieu.h' header file provides declarations that are\r
+needed to compile SoftFloat. In addition, deviations from ISO/ANSI C by\r
+the compiler (such as names not properly declared in system header files)\r
+are corrected in this header if possible.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+softfloat/bits*/*/softfloat-specialize\r
+\r
+This target-specific C source fragment defines:\r
+\r
+-- whether tininess for underflow is detected before or after rounding by\r
+ default;\r
+-- what (if anything) special happens when exceptions are raised;\r
+-- how signaling NaNs are distinguished from quiet NaNs;\r
+-- the default generated quiet NaNs; and\r
+-- how NaNs are propagated from function inputs to output.\r
+\r
+These details are not decided by the IEC/IEEE Standard. This fragment is\r
+included verbatim within `softfloat.c' when SoftFloat is compiled.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+softfloat/bits*/softfloat-macros\r
+\r
+This target-independent C source fragment defines a number of arithmetic\r
+functions used as primitives within the `softfloat.c' source. Most of\r
+the functions defined here are intended to be inlined for efficiency.\r
+This fragment is included verbatim within `softfloat.c' when SoftFloat is\r
+compiled.\r
+\r
+Target-specific variations on this file are possible. See the section\r
+_Processor-Specific Optimization of `softfloat.c' Using `softfloat-macros'_\r
+below.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+softfloat/bits*/softfloat.c\r
+\r
+The target-independent `softfloat.c' source file contains the body of the\r
+SoftFloat implementation.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+\r
+The inclusion of the files above within each other (using `#include') can be\r
+shown graphically as follows:\r
+\r
+ softfloat/bits*/softfloat.c\r
+ softfloat/bits*/*/milieu.h\r
+ processors/*.h\r
+ softfloat/bits*/*/softfloat.h\r
+ softfloat/bits*/*/softfloat-specialize\r
+ softfloat/bits*/softfloat-macros\r
+\r
+Note in particular that `softfloat.c' does not include the `processors'\r
+header file directly. Rather, `softfloat.c' includes the target-specific\r
+`milieu.h' header file, which in turn includes the appropriate processor\r
+header file.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Steps to Creating a `softfloat.o'\r
+\r
+Porting and/or compiling SoftFloat involves the following steps:\r
+\r
+1. If one does not already exist, create an appropriate `.h' file in the\r
+ `processors' directory.\r
+\r
+2. If `BITS64' is defined in the `processors' header file, choose whether\r
+ to compile the 32-bit or 64-bit implementation of SoftFloat. If\r
+ `BITS64' is not defined, your only choice is the 32-bit implementation.\r
+ The remaining steps occur within either the `bits32' or `bits64'\r
+ subdirectories.\r
+\r
+3. If one does not already exist, create an appropriate target-specific\r
+ subdirectory by copying the given `templates' directory.\r
+\r
+4. In the target-specific subdirectory, edit the files `softfloat-specialize'\r
+ and `softfloat.h' to define the desired exception handling functions\r
+ and mode control values. In the `softfloat.h' header file, ensure also\r
+ that all declarations give the proper target-specific type (such as\r
+ `int' or `long') corresponding to the target-independent type used in\r
+ `softfloat.c' (such as `int32'). None of the type names declared in the\r
+ `processors' header file should appear in `softfloat.h'.\r
+\r
+5. In the target-specific subdirectory, edit the files `milieu.h' and\r
+ `Makefile' to reflect the current environment.\r
+\r
+6. In the target-specific subdirectory, execute `make'.\r
+\r
+For the targets that are supplied, if the expected compiler is available\r
+(usually `gcc'), it should only be necessary to execute `make' in the\r
+target-specific subdirectory.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Making `softfloat.o' a Library\r
+\r
+SoftFloat is not made into a software library by the supplied makefile.\r
+If desired, `softfloat.o' can easily be put into its own library (in Unix,\r
+`softfloat.a') using the usual system tool (in Unix, `ar').\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Testing SoftFloat\r
+\r
+SoftFloat can be tested using the `testsoftfloat' program by the same\r
+author. The `testsoftfloat' program is part of the TestFloat package\r
+available at the Web page `http://www.cs.berkeley.edu/~jhauser/arithmetic/\r
+TestFloat.html'.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Timing SoftFloat\r
+\r
+A program called `timesoftfloat' for timing the SoftFloat functions is\r
+included with the SoftFloat source code. Compiling `timesoftfloat' should\r
+pose no difficulties once `softfloat.o' exists. The supplied makefile\r
+will create a `timesoftfloat' executable by default after generating\r
+`softfloat.o'. See `timesoftfloat.txt' for documentation about using\r
+`timesoftfloat'.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Compiler Options and Efficiency\r
+\r
+In order to get good speed with SoftFloat, it is important that the compiler\r
+inline the routines that have been marked `INLINE' in the code. Even if\r
+inlining cannot be forced by an appropriate definition of the `INLINE'\r
+macro, the compiler may still be able to perform inlining on its own as\r
+an optimization. In that case, the makefile should be edited to give the\r
+compiler whatever option is required to cause it to inline small functions.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Processor-Specific Optimization of `softfloat.c' Using `softfloat-macros'\r
+\r
+The `softfloat-macros' source fragment defines arithmetic functions used\r
+as primitives by `softfloat.c'. This file has been written in a target-\r
+independent form. For a given target, it may be possible to improve on\r
+these functions using target-specific and/or non-ISO-C features (such\r
+as `asm' statements). For example, one of the ``macro'' functions takes\r
+two word-size integers and returns their full product in two words.\r
+This operation can be done directly in hardware on many processors; but\r
+because it is not available through standard C, the function defined in\r
+`softfloat-macros' uses four multiplications to achieve the same result.\r
+\r
+To address these shortcomings, a customized version of `softfloat-macros'\r
+can be created in any of the target-specific subdirectories. A simple\r
+modification to the target's makefile should be sufficient to ensure that\r
+the custom version is used instead of the generic one.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Contact Information\r
+\r
+At the time of this writing, the most up-to-date information about\r
+SoftFloat and the latest release can be found at the Web page `http://\r
+www.cs.berkeley.edu/~jhauser/arithmetic/SoftFloat.html'.\r
+\r
+\r
--- /dev/null
+\r
+SoftFloat Release 2b General Documentation\r
+\r
+John R. Hauser\r
+2002 May 27\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Introduction\r
+\r
+SoftFloat is a software implementation of floating-point that conforms to\r
+the IEC/IEEE Standard for Binary Floating-Point Arithmetic. As many as four\r
+formats are supported: single precision, double precision, extended double\r
+precision, and quadruple precision. All operations required by the standard\r
+are implemented, except for conversions to and from decimal.\r
+\r
+This document gives information about the types defined and the routines\r
+implemented by SoftFloat. It does not attempt to define or explain the\r
+IEC/IEEE Floating-Point Standard. Details about the standard are available\r
+elsewhere.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Limitations\r
+\r
+SoftFloat is written in C and is designed to work with other C code. The\r
+SoftFloat header files assume an ISO/ANSI-style C compiler. No attempt\r
+has been made to accomodate compilers that are not ISO-conformant. In\r
+particular, the distributed header files will not be acceptable to any\r
+compiler that does not recognize function prototypes.\r
+\r
+Support for the extended double-precision and quadruple-precision formats\r
+depends on a C compiler that implements 64-bit integer arithmetic. If the\r
+largest integer format supported by the C compiler is 32 bits, SoftFloat\r
+is limited to only single and double precisions. When that is the case,\r
+all references in this document to extended double precision, quadruple\r
+precision, and 64-bit integers should be ignored.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Contents\r
+\r
+ Introduction\r
+ Limitations\r
+ Contents\r
+ Legal Notice\r
+ Types and Functions\r
+ Rounding Modes\r
+ Extended Double-Precision Rounding Precision\r
+ Exceptions and Exception Flags\r
+ Function Details\r
+ Conversion Functions\r
+ Standard Arithmetic Functions\r
+ Remainder Functions\r
+ Round-to-Integer Functions\r
+ Comparison Functions\r
+ Signaling NaN Test Functions\r
+ Raise-Exception Function\r
+ Contact Information\r
+\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Legal Notice\r
+\r
+SoftFloat was written by John R. Hauser. This work was made possible in\r
+part by the International Computer Science Institute, located at Suite 600,\r
+1947 Center Street, Berkeley, California 94704. Funding was partially\r
+provided by the National Science Foundation under grant MIP-9311980. The\r
+original version of this code was written as part of a project to build\r
+a fixed-point vector processor in collaboration with the University of\r
+California at Berkeley, overseen by Profs. Nelson Morgan and John Wawrzynek.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort\r
+has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT\r
+TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO\r
+PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL\r
+LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO\r
+FURTHERMORE EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER\r
+SCIENCE INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE\r
+SOFTWARE.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Types and Functions\r
+\r
+When 64-bit integers are supported by the compiler, the `softfloat.h'\r
+header file defines four types: `float32' (single precision), `float64'\r
+(double precision), `floatx80' (extended double precision), and `float128'\r
+(quadruple precision). The `float32' and `float64' types are defined in\r
+terms of 32-bit and 64-bit integer types, respectively, while the `float128'\r
+type is defined as a structure of two 64-bit integers, taking into account\r
+the byte order of the particular machine being used. The `floatx80' type\r
+is defined as a structure containing one 16-bit and one 64-bit integer, with\r
+the machine's byte order again determining the order within the structure.\r
+\r
+When 64-bit integers are _not_ supported by the compiler, the `softfloat.h'\r
+header file defines only two types: `float32' and `float64'. Because\r
+ISO/ANSI C guarantees at least one built-in integer type of 32 bits,\r
+the `float32' type is identified with an appropriate integer type. The\r
+`float64' type is defined as a structure of two 32-bit integers, with the\r
+machine's byte order determining the order of the fields.\r
+\r
+In either case, the types in `softfloat.h' are defined such that if a system\r
+implements the usual C `float' and `double' types according to the IEC/IEEE\r
+Standard, then the `float32' and `float64' types should be indistinguishable\r
+in memory from the native `float' and `double' types. (On the other hand,\r
+when `float32' or `float64' values are placed in processor registers by\r
+the compiler, the type of registers used may differ from those used for the\r
+native `float' and `double' types.)\r
+\r
+SoftFloat implements the following arithmetic operations:\r
+\r
+-- Conversions among all the floating-point formats, and also between\r
+ integers (32-bit and 64-bit) and any of the floating-point formats.\r
+\r
+-- The usual add, subtract, multiply, divide, and square root operations\r
+ for all floating-point formats.\r
+\r
+-- For each format, the floating-point remainder operation defined by the\r
+ IEC/IEEE Standard.\r
+\r
+-- For each floating-point format, a ``round to integer'' operation that\r
+ rounds to the nearest integer value in the same format. (The floating-\r
+ point formats can hold integer values, of course.)\r
+\r
+-- Comparisons between two values in the same floating-point format.\r
+\r
+The only functions required by the IEC/IEEE Standard that are not provided\r
+are conversions to and from decimal.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Rounding Modes\r
+\r
+All four rounding modes prescribed by the IEC/IEEE Standard are implemented\r
+for all operations that require rounding. The rounding mode is selected\r
+by the global variable `float_rounding_mode'. This variable may be set\r
+to one of the values `float_round_nearest_even', `float_round_to_zero',\r
+`float_round_down', or `float_round_up'. The rounding mode is initialized\r
+to nearest/even.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Extended Double-Precision Rounding Precision\r
+\r
+For extended double precision (`floatx80') only, the rounding precision\r
+of the standard arithmetic operations is controlled by the global variable\r
+`floatx80_rounding_precision'. The operations affected are:\r
+\r
+ floatx80_add floatx80_sub floatx80_mul floatx80_div floatx80_sqrt\r
+\r
+When `floatx80_rounding_precision' is set to its default value of 80, these\r
+operations are rounded (as usual) to the full precision of the extended\r
+double-precision format. Setting `floatx80_rounding_precision' to 32\r
+or to 64 causes the operations listed to be rounded to reduced precision\r
+equivalent to single precision (`float32') or to double precision\r
+(`float64'), respectively. When rounding to reduced precision, additional\r
+bits in the result significand beyond the rounding point are set to zero.\r
+The consequences of setting `floatx80_rounding_precision' to a value other\r
+than 32, 64, or 80 is not specified. Operations other than the ones listed\r
+above are not affected by `floatx80_rounding_precision'.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Exceptions and Exception Flags\r
+\r
+All five exception flags required by the IEC/IEEE Standard are\r
+implemented. Each flag is stored as a unique bit in the global variable\r
+`float_exception_flags'. The positions of the exception flag bits within\r
+this variable are determined by the bit masks `float_flag_inexact',\r
+`float_flag_underflow', `float_flag_overflow', `float_flag_divbyzero', and\r
+`float_flag_invalid'. The exception flags variable is initialized to all 0,\r
+meaning no exceptions.\r
+\r
+An individual exception flag can be cleared with the statement\r
+\r
+ float_exception_flags &= ~ float_flag_<exception>;\r
+\r
+where `<exception>' is the appropriate name. To raise a floating-point\r
+exception, the SoftFloat function `float_raise' should be used (see below).\r
+\r
+In the terminology of the IEC/IEEE Standard, SoftFloat can detect tininess\r
+for underflow either before or after rounding. The choice is made by\r
+the global variable `float_detect_tininess', which can be set to either\r
+`float_tininess_before_rounding' or `float_tininess_after_rounding'.\r
+Detecting tininess after rounding is better because it results in fewer\r
+spurious underflow signals. The other option is provided for compatibility\r
+with some systems. Like most systems, SoftFloat always detects loss of\r
+accuracy for underflow as an inexact result.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Function Details\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Conversion Functions\r
+\r
+All conversions among the floating-point formats are supported, as are all\r
+conversions between a floating-point format and 32-bit and 64-bit signed\r
+integers. The complete set of conversion functions is:\r
+\r
+ int32_to_float32 int64_to_float32\r
+ int32_to_float64 int64_to_float32\r
+ int32_to_floatx80 int64_to_floatx80\r
+ int32_to_float128 int64_to_float128\r
+\r
+ float32_to_int32 float32_to_int64\r
+ float32_to_int32 float64_to_int64\r
+ floatx80_to_int32 floatx80_to_int64\r
+ float128_to_int32 float128_to_int64\r
+\r
+ float32_to_float64 float32_to_floatx80 float32_to_float128\r
+ float64_to_float32 float64_to_floatx80 float64_to_float128\r
+ floatx80_to_float32 floatx80_to_float64 floatx80_to_float128\r
+ float128_to_float32 float128_to_float64 float128_to_floatx80\r
+\r
+Each conversion function takes one operand of the appropriate type and\r
+returns one result. Conversions from a smaller to a larger floating-point\r
+format are always exact and so require no rounding. Conversions from 32-bit\r
+integers to double precision and larger formats are also exact, and likewise\r
+for conversions from 64-bit integers to extended double and quadruple\r
+precisions.\r
+\r
+Conversions from floating-point to integer raise the invalid exception if\r
+the source value cannot be rounded to a representable integer of the desired\r
+size (32 or 64 bits). If the floating-point operand is a NaN, the largest\r
+positive integer is returned. Otherwise, if the conversion overflows, the\r
+largest integer with the same sign as the operand is returned.\r
+\r
+On conversions to integer, if the floating-point operand is not already\r
+an integer value, the operand is rounded according to the current rounding\r
+mode as specified by `float_rounding_mode'. Because C (and perhaps other\r
+languages) require that conversions to integers be rounded toward zero, the\r
+following functions are provided for improved speed and convenience:\r
+\r
+ float32_to_int32_round_to_zero float32_to_int64_round_to_zero\r
+ float64_to_int32_round_to_zero float64_to_int64_round_to_zero\r
+ floatx80_to_int32_round_to_zero floatx80_to_int64_round_to_zero\r
+ float128_to_int32_round_to_zero float128_to_int64_round_to_zero\r
+\r
+These variant functions ignore `float_rounding_mode' and always round toward\r
+zero.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Standard Arithmetic Functions\r
+\r
+The following standard arithmetic functions are provided:\r
+\r
+ float32_add float32_sub float32_mul float32_div float32_sqrt\r
+ float64_add float64_sub float64_mul float64_div float64_sqrt\r
+ floatx80_add floatx80_sub floatx80_mul floatx80_div floatx80_sqrt\r
+ float128_add float128_sub float128_mul float128_div float128_sqrt\r
+\r
+Each function takes two operands, except for `sqrt' which takes only one.\r
+The operands and result are all of the same type.\r
+\r
+Rounding of the extended double-precision (`floatx80') functions is affected\r
+by the `floatx80_rounding_precision' variable, as explained above in the\r
+section _Extended Double-Precision Rounding Precision_.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Remainder Functions\r
+\r
+For each format, SoftFloat implements the remainder function according to\r
+the IEC/IEEE Standard. The remainder functions are:\r
+\r
+ float32_rem\r
+ float64_rem\r
+ floatx80_rem\r
+ float128_rem\r
+\r
+Each remainder function takes two operands. The operands and result are all\r
+of the same type. Given operands x and y, the remainder functions return\r
+the value x - n*y, where n is the integer closest to x/y. If x/y is exactly\r
+halfway between two integers, n is the even integer closest to x/y. The\r
+remainder functions are always exact and so require no rounding.\r
+\r
+Depending on the relative magnitudes of the operands, the remainder\r
+functions can take considerably longer to execute than the other SoftFloat\r
+functions. This is inherent in the remainder operation itself and is not a\r
+flaw in the SoftFloat implementation.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Round-to-Integer Functions\r
+\r
+For each format, SoftFloat implements the round-to-integer function\r
+specified by the IEC/IEEE Standard. The functions are:\r
+\r
+ float32_round_to_int\r
+ float64_round_to_int\r
+ floatx80_round_to_int\r
+ float128_round_to_int\r
+\r
+Each function takes a single floating-point operand and returns a result of\r
+the same type. (Note that the result is not an integer type.) The operand\r
+is rounded to an exact integer according to the current rounding mode, and\r
+the resulting integer value is returned in the same floating-point format.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Comparison Functions\r
+\r
+The following floating-point comparison functions are provided:\r
+\r
+ float32_eq float32_le float32_lt\r
+ float64_eq float64_le float64_lt\r
+ floatx80_eq floatx80_le floatx80_lt\r
+ float128_eq float128_le float128_lt\r
+\r
+Each function takes two operands of the same type and returns a 1 or 0\r
+representing either _true_ or _false_. The abbreviation `eq' stands for\r
+``equal'' (=); `le' stands for ``less than or equal'' (<=); and `lt' stands\r
+for ``less than'' (<).\r
+\r
+The standard greater-than (>), greater-than-or-equal (>=), and not-equal\r
+(!=) functions are easily obtained using the functions provided. The\r
+not-equal function is just the logical complement of the equal function.\r
+The greater-than-or-equal function is identical to the less-than-or-equal\r
+function with the operands reversed, and the greater-than function is\r
+identical to the less-than function with the operands reversed.\r
+\r
+The IEC/IEEE Standard specifies that the less-than-or-equal and less-than\r
+functions raise the invalid exception if either input is any kind of NaN.\r
+The equal functions, on the other hand, are defined not to raise the invalid\r
+exception on quiet NaNs. For completeness, SoftFloat provides the following\r
+additional functions:\r
+\r
+ float32_eq_signaling float32_le_quiet float32_lt_quiet\r
+ float64_eq_signaling float64_le_quiet float64_lt_quiet\r
+ floatx80_eq_signaling floatx80_le_quiet floatx80_lt_quiet\r
+ float128_eq_signaling float128_le_quiet float128_lt_quiet\r
+\r
+The `signaling' equal functions are identical to the standard functions\r
+except that the invalid exception is raised for any NaN input. Likewise,\r
+the `quiet' comparison functions are identical to their counterparts except\r
+that the invalid exception is not raised for quiet NaNs.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Signaling NaN Test Functions\r
+\r
+The following functions test whether a floating-point value is a signaling\r
+NaN:\r
+\r
+ float32_is_signaling_nan\r
+ float64_is_signaling_nan\r
+ floatx80_is_signaling_nan\r
+ float128_is_signaling_nan\r
+\r
+The functions take one operand and return 1 if the operand is a signaling\r
+NaN and 0 otherwise.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+Raise-Exception Function\r
+\r
+SoftFloat provides a function for raising floating-point exceptions:\r
+\r
+ float_raise\r
+\r
+The function takes a mask indicating the set of exceptions to raise. No\r
+result is returned. In addition to setting the specified exception flags,\r
+this function may cause a trap or abort appropriate for the current system.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Contact Information\r
+\r
+At the time of this writing, the most up-to-date information about\r
+SoftFloat and the latest release can be found at the Web page `http://\r
+www.cs.berkeley.edu/~jhauser/arithmetic/SoftFloat.html'.\r
+\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Include common integer types and flags.\r
+*----------------------------------------------------------------------------*/\r
+#include "../../../processors/386-GCC.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Symbolic Boolean literals.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ FALSE = 0,\r
+ TRUE = 1\r
+};\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Underflow tininess-detection mode, statically initialized to default value.\r
+| (The declaration in `softfloat.h' must match the `int8' type here.)\r
+*----------------------------------------------------------------------------*/\r
+int8 float_detect_tininess = float_tininess_after_rounding;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Raises the exceptions specified by `flags'. Floating-point traps can be\r
+| defined here if desired. It is currently not possible for such a trap\r
+| to substitute a result value. If traps are not implemented, this routine\r
+| should be simply `float_exception_flags |= flags;'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+void float_raise( int8 flags )\r
+{\r
+\r
+ float_exception_flags |= flags;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Internal canonical NaN format.\r
+*----------------------------------------------------------------------------*/\r
+typedef struct {\r
+ flag sign;\r
+ bits32 high, low;\r
+} commonNaNT;\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ float32_default_nan = 0xFFC00000\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_nan( float32 a )\r
+{\r
+\r
+ return ( 0xFF000000 < (bits32) ( a<<1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_signaling_nan( float32 a )\r
+{\r
+\r
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float32ToCommonNaN( float32 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a>>31;\r
+ z.low = 0;\r
+ z.high = a<<9;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the single-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 commonNaNToFloat32( commonNaNT a )\r
+{\r
+\r
+ return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>9 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 propagateFloat32NaN( float32 a, float32 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float32_is_nan( a );\r
+ aIsSignalingNaN = float32_is_signaling_nan( a );\r
+ bIsNaN = float32_is_nan( b );\r
+ bIsSignalingNaN = float32_is_signaling_nan( b );\r
+ a |= 0x00400000;\r
+ b |= 0x00400000;\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsSignalingNaN ) {\r
+ if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+ return bIsNaN ? b : a;\r
+ }\r
+ else if ( aIsNaN ) {\r
+ if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+ if ( (bits32) ( a<<1 ) < (bits32) ( b<<1 ) ) return b;\r
+ if ( (bits32) ( b<<1 ) < (bits32) ( a<<1 ) ) return a;\r
+ return ( a < b ) ? a : b;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN. The `high' and\r
+| `low' values hold the most- and least-significant bits, respectively.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ float64_default_nan_high = 0xFFF80000,\r
+ float64_default_nan_low = 0x00000000\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_nan( float64 a )\r
+{\r
+\r
+ return\r
+ ( 0xFFE00000 <= (bits32) ( a.high<<1 ) )\r
+ && ( a.low || ( a.high & 0x000FFFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_signaling_nan( float64 a )\r
+{\r
+\r
+ return\r
+ ( ( ( a.high>>19 ) & 0xFFF ) == 0xFFE )\r
+ && ( a.low || ( a.high & 0x0007FFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float64ToCommonNaN( float64 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a.high>>31;\r
+ shortShift64Left( a.high, a.low, 12, &z.high, &z.low );\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the double-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 commonNaNToFloat64( commonNaNT a )\r
+{\r
+ float64 z;\r
+\r
+ shift64Right( a.high, a.low, 12, &z.high, &z.low );\r
+ z.high |= ( ( (bits32) a.sign )<<31 ) | 0x7FF80000;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 propagateFloat64NaN( float64 a, float64 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float64_is_nan( a );\r
+ aIsSignalingNaN = float64_is_signaling_nan( a );\r
+ bIsNaN = float64_is_nan( b );\r
+ bIsSignalingNaN = float64_is_signaling_nan( b );\r
+ a.high |= 0x00080000;\r
+ b.high |= 0x00080000;\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsSignalingNaN ) {\r
+ if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+ return bIsNaN ? b : a;\r
+ }\r
+ else if ( aIsNaN ) {\r
+ if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+ if ( lt64( a.high<<1, a.low, b.high<<1, b.low ) ) return b;\r
+ if ( lt64( b.high<<1, b.low, a.high<<1, a.low ) ) return a;\r
+ return ( a.high < b.high ) ? a : b;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point types.\r
+*----------------------------------------------------------------------------*/\r
+typedef unsigned int float32;\r
+typedef struct {\r
+ unsigned int low, high;\r
+} float64;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point underflow tininess-detection mode.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char float_detect_tininess;\r
+enum {\r
+ float_tininess_after_rounding = 0,\r
+ float_tininess_before_rounding = 1\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point rounding mode.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char float_rounding_mode;\r
+enum {\r
+ float_round_nearest_even = 0,\r
+ float_round_down = 1,\r
+ float_round_up = 2,\r
+ float_round_to_zero = 3\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point exception flags.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char float_exception_flags;\r
+enum {\r
+ float_flag_invalid = 1,\r
+ float_flag_divbyzero = 4,\r
+ float_flag_overflow = 8,\r
+ float_flag_underflow = 16,\r
+ float_flag_inexact = 32\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Routine to raise any or all of the software IEC/IEEE floating-point\r
+| exception flags.\r
+*----------------------------------------------------------------------------*/\r
+void float_raise( signed char );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE integer-to-floating-point conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+float32 int32_to_float32( int );\r
+float64 int32_to_float64( int );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+int float32_to_int32( float32 );\r
+int float32_to_int32_round_to_zero( float32 );\r
+float64 float32_to_float64( float32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float32 float32_round_to_int( float32 );\r
+float32 float32_add( float32, float32 );\r
+float32 float32_sub( float32, float32 );\r
+float32 float32_mul( float32, float32 );\r
+float32 float32_div( float32, float32 );\r
+float32 float32_rem( float32, float32 );\r
+float32 float32_sqrt( float32 );\r
+char float32_eq( float32, float32 );\r
+char float32_le( float32, float32 );\r
+char float32_lt( float32, float32 );\r
+char float32_eq_signaling( float32, float32 );\r
+char float32_le_quiet( float32, float32 );\r
+char float32_lt_quiet( float32, float32 );\r
+char float32_is_signaling_nan( float32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+int float64_to_int32( float64 );\r
+int float64_to_int32_round_to_zero( float64 );\r
+float32 float64_to_float32( float64 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float64 float64_round_to_int( float64 );\r
+float64 float64_add( float64, float64 );\r
+float64 float64_sub( float64, float64 );\r
+float64 float64_mul( float64, float64 );\r
+float64 float64_div( float64, float64 );\r
+float64 float64_rem( float64, float64 );\r
+float64 float64_sqrt( float64 );\r
+char float64_eq( float64, float64 );\r
+char float64_le( float64, float64 );\r
+char float64_lt( float64, float64 );\r
+char float64_eq_signaling( float64, float64 );\r
+char float64_le_quiet( float64, float64 );\r
+char float64_lt_quiet( float64, float64 );\r
+char float64_is_signaling_nan( float64 );\r
+\r
--- /dev/null
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
+Package, Release 2b.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+| Include common integer types and flags.
+*----------------------------------------------------------------------------*/
+#include "../../../processors/SPARC-GCC.h"
+
+/*----------------------------------------------------------------------------
+| Symbolic Boolean literals.
+*----------------------------------------------------------------------------*/
+enum {
+ FALSE = 0,
+ TRUE = 1
+};
+
--- /dev/null
+
+/*============================================================================
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2b.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+| Underflow tininess-detection mode, statically initialized to default value.
+| (The declaration in `softfloat.h' must match the `int8' type here.)
+*----------------------------------------------------------------------------*/
+int8 float_detect_tininess = float_tininess_before_rounding;
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'. Floating-point traps can be
+| defined here if desired. It is currently not possible for such a trap
+| to substitute a result value. If traps are not implemented, this routine
+| should be simply `float_exception_flags |= flags;'.
+*----------------------------------------------------------------------------*/
+
+void float_raise( int8 flags )
+{
+
+ float_exception_flags |= flags;
+
+}
+
+/*----------------------------------------------------------------------------
+| Internal canonical NaN format.
+*----------------------------------------------------------------------------*/
+typedef struct {
+ flag sign;
+ bits32 high, low;
+} commonNaNT;
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated single-precision NaN.
+*----------------------------------------------------------------------------*/
+enum {
+ float32_default_nan = 0x7FFFFFFF
+};
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point value `a' is a NaN;
+| otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float32_is_nan( float32 a )
+{
+
+ return ( 0xFF000000 < (bits32) ( a<<1 ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float32_is_signaling_nan( float32 a )
+{
+
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the single-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float32ToCommonNaN( float32 a )
+{
+ commonNaNT z;
+
+ if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
+ z.sign = a>>31;
+ z.low = 0;
+ z.high = a<<9;
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the single-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float32 commonNaNToFloat32( commonNaNT a )
+{
+
+ return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>9 );
+
+}
+
+/*----------------------------------------------------------------------------
+| Takes two single-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float32 propagateFloat32NaN( float32 a, float32 b )
+{
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+
+ aIsNaN = float32_is_nan( a );
+ aIsSignalingNaN = float32_is_signaling_nan( a );
+ bIsNaN = float32_is_nan( b );
+ bIsSignalingNaN = float32_is_signaling_nan( b );
+ a |= 0x00400000;
+ b |= 0x00400000;
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
+ return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
+
+}
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated double-precision NaN. The `high' and
+| `low' values hold the most- and least-significant bits, respectively.
+*----------------------------------------------------------------------------*/
+enum {
+ float64_default_nan_high = 0x7FFFFFFF,
+ float64_default_nan_low = 0xFFFFFFFF
+};
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point value `a' is a NaN;
+| otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float64_is_nan( float64 a )
+{
+
+ return
+ ( 0xFFE00000 <= (bits32) ( a.high<<1 ) )
+ && ( a.low || ( a.high & 0x000FFFFF ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float64_is_signaling_nan( float64 a )
+{
+
+ return
+ ( ( ( a.high>>19 ) & 0xFFF ) == 0xFFE )
+ && ( a.low || ( a.high & 0x0007FFFF ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the double-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float64ToCommonNaN( float64 a )
+{
+ commonNaNT z;
+
+ if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
+ z.sign = a.high>>31;
+ shortShift64Left( a.high, a.low, 12, &z.high, &z.low );
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the double-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float64 commonNaNToFloat64( commonNaNT a )
+{
+ float64 z;
+
+ shift64Right( a.high, a.low, 12, &z.high, &z.low );
+ z.high |= ( ( (bits32) a.sign )<<31 ) | 0x7FF80000;
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Takes two double-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float64 propagateFloat64NaN( float64 a, float64 b )
+{
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+
+ aIsNaN = float64_is_nan( a );
+ aIsSignalingNaN = float64_is_signaling_nan( a );
+ bIsNaN = float64_is_nan( b );
+ bIsSignalingNaN = float64_is_signaling_nan( b );
+ a.high |= 0x00080000;
+ b.high |= 0x00080000;
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
+ return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
+
+}
+
--- /dev/null
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
+Package, Release 2b.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point types.
+*----------------------------------------------------------------------------*/
+typedef unsigned int float32;
+typedef struct {
+ unsigned int high, low;
+} float64;
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point underflow tininess-detection mode.
+*----------------------------------------------------------------------------*/
+extern int float_detect_tininess;
+enum {
+ float_tininess_after_rounding = 0,
+ float_tininess_before_rounding = 1
+};
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point rounding mode.
+*----------------------------------------------------------------------------*/
+extern int float_rounding_mode;
+enum {
+ float_round_nearest_even = 0,
+ float_round_to_zero = 1,
+ float_round_up = 2,
+ float_round_down = 3
+};
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point exception flags.
+*----------------------------------------------------------------------------*/
+extern int float_exception_flags;
+enum {
+ float_flag_inexact = 1,
+ float_flag_divbyzero = 2,
+ float_flag_underflow = 4,
+ float_flag_overflow = 8,
+ float_flag_invalid = 16
+};
+
+/*----------------------------------------------------------------------------
+| Routine to raise any or all of the software IEC/IEEE floating-point
+| exception flags.
+*----------------------------------------------------------------------------*/
+void float_raise( int );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE integer-to-floating-point conversion routines.
+*----------------------------------------------------------------------------*/
+float32 int32_to_float32( int );
+float64 int32_to_float64( int );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE single-precision conversion routines.
+*----------------------------------------------------------------------------*/
+int float32_to_int32( float32 );
+int float32_to_int32_round_to_zero( float32 );
+float64 float32_to_float64( float32 );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE single-precision operations.
+*----------------------------------------------------------------------------*/
+float32 float32_round_to_int( float32 );
+float32 float32_add( float32, float32 );
+float32 float32_sub( float32, float32 );
+float32 float32_mul( float32, float32 );
+float32 float32_div( float32, float32 );
+float32 float32_rem( float32, float32 );
+float32 float32_sqrt( float32 );
+int float32_eq( float32, float32 );
+int float32_le( float32, float32 );
+int float32_lt( float32, float32 );
+int float32_eq_signaling( float32, float32 );
+int float32_le_quiet( float32, float32 );
+int float32_lt_quiet( float32, float32 );
+int float32_is_signaling_nan( float32 );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE double-precision conversion routines.
+*----------------------------------------------------------------------------*/
+int float64_to_int32( float64 );
+int float64_to_int32_round_to_zero( float64 );
+float32 float64_to_float32( float64 );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE double-precision operations.
+*----------------------------------------------------------------------------*/
+float64 float64_round_to_int( float64 );
+float64 float64_add( float64, float64 );
+float64 float64_sub( float64, float64 );
+float64 float64_mul( float64, float64 );
+float64 float64_div( float64, float64 );
+float64 float64_rem( float64, float64 );
+float64 float64_sqrt( float64 );
+int float64_eq( float64, float64 );
+int float64_le( float64, float64 );
+int float64_lt( float64, float64 );
+int float64_eq_signaling( float64, float64 );
+int float64_le_quiet( float64, float64 );
+int float64_lt_quiet( float64, float64 );
+int float64_is_signaling_nan( float64 );
+
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts `a' right by the number of bits given in `count'. If any nonzero\r
+| bits are shifted off, they are ``jammed'' into the least significant bit of\r
+| the result by setting the least significant bit to 1. The value of `count'\r
+| can be arbitrarily large; in particular, if `count' is greater than 32, the\r
+| result will be either 0 or 1, depending on whether `a' is zero or nonzero.\r
+| The result is stored in the location pointed to by `zPtr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )\r
+{\r
+ bits32 z;\r
+\r
+ if ( count == 0 ) {\r
+ z = a;\r
+ }\r
+ else if ( count < 32 ) {\r
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );\r
+ }\r
+ else {\r
+ z = ( a != 0 );\r
+ }\r
+ *zPtr = z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the\r
+| number of bits given in `count'. Any bits shifted off are lost. The value\r
+| of `count' can be arbitrarily large; in particular, if `count' is greater\r
+| than 64, the result will be 0. The result is broken into two 32-bit pieces\r
+| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift64Right(\r
+ bits32 a0, bits32 a1, int16 count, bits32 *z0Ptr, bits32 *z1Ptr )\r
+{\r
+ bits32 z0, z1;\r
+ int8 negCount = ( - count ) & 31;\r
+\r
+ if ( count == 0 ) {\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else if ( count < 32 ) {\r
+ z1 = ( a0<<negCount ) | ( a1>>count );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ z1 = ( count < 64 ) ? ( a0>>( count & 31 ) ) : 0;\r
+ z0 = 0;\r
+ }\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the\r
+| number of bits given in `count'. If any nonzero bits are shifted off, they\r
+| are ``jammed'' into the least significant bit of the result by setting the\r
+| least significant bit to 1. The value of `count' can be arbitrarily large;\r
+| in particular, if `count' is greater than 64, the result will be either 0\r
+| or 1, depending on whether the concatenation of `a0' and `a1' is zero or\r
+| nonzero. The result is broken into two 32-bit pieces which are stored at\r
+| the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift64RightJamming(\r
+ bits32 a0, bits32 a1, int16 count, bits32 *z0Ptr, bits32 *z1Ptr )\r
+{\r
+ bits32 z0, z1;\r
+ int8 negCount = ( - count ) & 31;\r
+\r
+ if ( count == 0 ) {\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else if ( count < 32 ) {\r
+ z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ if ( count == 32 ) {\r
+ z1 = a0 | ( a1 != 0 );\r
+ }\r
+ else if ( count < 64 ) {\r
+ z1 = ( a0>>( count & 31 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );\r
+ }\r
+ else {\r
+ z1 = ( ( a0 | a1 ) != 0 );\r
+ }\r
+ z0 = 0;\r
+ }\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 96-bit value formed by concatenating `a0', `a1', and `a2' right\r
+| by 32 _plus_ the number of bits given in `count'. The shifted result is\r
+| at most 64 nonzero bits; these are broken into two 32-bit pieces which are\r
+| stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted\r
+| off form a third 32-bit result as follows: The _last_ bit shifted off is\r
+| the most-significant bit of the extra result, and the other 31 bits of the\r
+| extra result are all zero if and only if _all_but_the_last_ bits shifted off\r
+| were all zero. This extra result is stored in the location pointed to by\r
+| `z2Ptr'. The value of `count' can be arbitrarily large.\r
+| (This routine makes more sense if `a0', `a1', and `a2' are considered\r
+| to form a fixed-point value with binary point between `a1' and `a2'. This\r
+| fixed-point value is shifted right by the number of bits given in `count',\r
+| and the integer part of the result is returned at the locations pointed to\r
+| by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly\r
+| corrupted as described above, and is returned at the location pointed to by\r
+| `z2Ptr'.)\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift64ExtraRightJamming(\r
+ bits32 a0,\r
+ bits32 a1,\r
+ bits32 a2,\r
+ int16 count,\r
+ bits32 *z0Ptr,\r
+ bits32 *z1Ptr,\r
+ bits32 *z2Ptr\r
+ )\r
+{\r
+ bits32 z0, z1, z2;\r
+ int8 negCount = ( - count ) & 31;\r
+\r
+ if ( count == 0 ) {\r
+ z2 = a2;\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else {\r
+ if ( count < 32 ) {\r
+ z2 = a1<<negCount;\r
+ z1 = ( a0<<negCount ) | ( a1>>count );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ if ( count == 32 ) {\r
+ z2 = a1;\r
+ z1 = a0;\r
+ }\r
+ else {\r
+ a2 |= a1;\r
+ if ( count < 64 ) {\r
+ z2 = a0<<negCount;\r
+ z1 = a0>>( count & 31 );\r
+ }\r
+ else {\r
+ z2 = ( count == 64 ) ? a0 : ( a0 != 0 );\r
+ z1 = 0;\r
+ }\r
+ }\r
+ z0 = 0;\r
+ }\r
+ z2 |= ( a2 != 0 );\r
+ }\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 64-bit value formed by concatenating `a0' and `a1' left by the\r
+| number of bits given in `count'. Any bits shifted off are lost. The value\r
+| of `count' must be less than 32. The result is broken into two 32-bit\r
+| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shortShift64Left(\r
+ bits32 a0, bits32 a1, int16 count, bits32 *z0Ptr, bits32 *z1Ptr )\r
+{\r
+\r
+ *z1Ptr = a1<<count;\r
+ *z0Ptr =\r
+ ( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 31 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 96-bit value formed by concatenating `a0', `a1', and `a2' left\r
+| by the number of bits given in `count'. Any bits shifted off are lost.\r
+| The value of `count' must be less than 32. The result is broken into three\r
+| 32-bit pieces which are stored at the locations pointed to by `z0Ptr',\r
+| `z1Ptr', and `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shortShift96Left(\r
+ bits32 a0,\r
+ bits32 a1,\r
+ bits32 a2,\r
+ int16 count,\r
+ bits32 *z0Ptr,\r
+ bits32 *z1Ptr,\r
+ bits32 *z2Ptr\r
+ )\r
+{\r
+ bits32 z0, z1, z2;\r
+ int8 negCount;\r
+\r
+ z2 = a2<<count;\r
+ z1 = a1<<count;\r
+ z0 = a0<<count;\r
+ if ( 0 < count ) {\r
+ negCount = ( ( - count ) & 31 );\r
+ z1 |= a2>>negCount;\r
+ z0 |= a1>>negCount;\r
+ }\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Adds the 64-bit value formed by concatenating `a0' and `a1' to the 64-bit\r
+| value formed by concatenating `b0' and `b1'. Addition is modulo 2^64, so\r
+| any carry out is lost. The result is broken into two 32-bit pieces which\r
+| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ add64(\r
+ bits32 a0, bits32 a1, bits32 b0, bits32 b1, bits32 *z0Ptr, bits32 *z1Ptr )\r
+{\r
+ bits32 z1;\r
+\r
+ z1 = a1 + b1;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = a0 + b0 + ( z1 < a1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Adds the 96-bit value formed by concatenating `a0', `a1', and `a2' to the\r
+| 96-bit value formed by concatenating `b0', `b1', and `b2'. Addition is\r
+| modulo 2^96, so any carry out is lost. The result is broken into three\r
+| 32-bit pieces which are stored at the locations pointed to by `z0Ptr',\r
+| `z1Ptr', and `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ add96(\r
+ bits32 a0,\r
+ bits32 a1,\r
+ bits32 a2,\r
+ bits32 b0,\r
+ bits32 b1,\r
+ bits32 b2,\r
+ bits32 *z0Ptr,\r
+ bits32 *z1Ptr,\r
+ bits32 *z2Ptr\r
+ )\r
+{\r
+ bits32 z0, z1, z2;\r
+ int8 carry0, carry1;\r
+\r
+ z2 = a2 + b2;\r
+ carry1 = ( z2 < a2 );\r
+ z1 = a1 + b1;\r
+ carry0 = ( z1 < a1 );\r
+ z0 = a0 + b0;\r
+ z1 += carry1;\r
+ z0 += ( z1 < carry1 );\r
+ z0 += carry0;\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Subtracts the 64-bit value formed by concatenating `b0' and `b1' from the\r
+| 64-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo\r
+| 2^64, so any borrow out (carry out) is lost. The result is broken into two\r
+| 32-bit pieces which are stored at the locations pointed to by `z0Ptr' and\r
+| `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ sub64(\r
+ bits32 a0, bits32 a1, bits32 b0, bits32 b1, bits32 *z0Ptr, bits32 *z1Ptr )\r
+{\r
+\r
+ *z1Ptr = a1 - b1;\r
+ *z0Ptr = a0 - b0 - ( a1 < b1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Subtracts the 96-bit value formed by concatenating `b0', `b1', and `b2' from\r
+| the 96-bit value formed by concatenating `a0', `a1', and `a2'. Subtraction\r
+| is modulo 2^96, so any borrow out (carry out) is lost. The result is broken\r
+| into three 32-bit pieces which are stored at the locations pointed to by\r
+| `z0Ptr', `z1Ptr', and `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ sub96(\r
+ bits32 a0,\r
+ bits32 a1,\r
+ bits32 a2,\r
+ bits32 b0,\r
+ bits32 b1,\r
+ bits32 b2,\r
+ bits32 *z0Ptr,\r
+ bits32 *z1Ptr,\r
+ bits32 *z2Ptr\r
+ )\r
+{\r
+ bits32 z0, z1, z2;\r
+ int8 borrow0, borrow1;\r
+\r
+ z2 = a2 - b2;\r
+ borrow1 = ( a2 < b2 );\r
+ z1 = a1 - b1;\r
+ borrow0 = ( a1 < b1 );\r
+ z0 = a0 - b0;\r
+ z0 -= ( z1 < borrow1 );\r
+ z1 -= borrow1;\r
+ z0 -= borrow0;\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Multiplies `a' by `b' to obtain a 64-bit product. The product is broken\r
+| into two 32-bit pieces which are stored at the locations pointed to by\r
+| `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void mul32To64( bits32 a, bits32 b, bits32 *z0Ptr, bits32 *z1Ptr )\r
+{\r
+ bits16 aHigh, aLow, bHigh, bLow;\r
+ bits32 z0, zMiddleA, zMiddleB, z1;\r
+\r
+ aLow = a;\r
+ aHigh = a>>16;\r
+ bLow = b;\r
+ bHigh = b>>16;\r
+ z1 = ( (bits32) aLow ) * bLow;\r
+ zMiddleA = ( (bits32) aLow ) * bHigh;\r
+ zMiddleB = ( (bits32) aHigh ) * bLow;\r
+ z0 = ( (bits32) aHigh ) * bHigh;\r
+ zMiddleA += zMiddleB;\r
+ z0 += ( ( (bits32) ( zMiddleA < zMiddleB ) )<<16 ) + ( zMiddleA>>16 );\r
+ zMiddleA <<= 16;\r
+ z1 += zMiddleA;\r
+ z0 += ( z1 < zMiddleA );\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Multiplies the 64-bit value formed by concatenating `a0' and `a1' by `b'\r
+| to obtain a 96-bit product. The product is broken into three 32-bit pieces\r
+| which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and\r
+| `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ mul64By32To96(\r
+ bits32 a0,\r
+ bits32 a1,\r
+ bits32 b,\r
+ bits32 *z0Ptr,\r
+ bits32 *z1Ptr,\r
+ bits32 *z2Ptr\r
+ )\r
+{\r
+ bits32 z0, z1, z2, more1;\r
+\r
+ mul32To64( a1, b, &z1, &z2 );\r
+ mul32To64( a0, b, &z0, &more1 );\r
+ add64( z0, more1, 0, z1, &z0, &z1 );\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Multiplies the 64-bit value formed by concatenating `a0' and `a1' to the\r
+| 64-bit value formed by concatenating `b0' and `b1' to obtain a 128-bit\r
+| product. The product is broken into four 32-bit pieces which are stored at\r
+| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ mul64To128(\r
+ bits32 a0,\r
+ bits32 a1,\r
+ bits32 b0,\r
+ bits32 b1,\r
+ bits32 *z0Ptr,\r
+ bits32 *z1Ptr,\r
+ bits32 *z2Ptr,\r
+ bits32 *z3Ptr\r
+ )\r
+{\r
+ bits32 z0, z1, z2, z3;\r
+ bits32 more1, more2;\r
+\r
+ mul32To64( a1, b1, &z2, &z3 );\r
+ mul32To64( a1, b0, &z1, &more2 );\r
+ add64( z1, more2, 0, z2, &z1, &z2 );\r
+ mul32To64( a0, b0, &z0, &more1 );\r
+ add64( z0, more1, 0, z1, &z0, &z1 );\r
+ mul32To64( a0, b1, &more1, &more2 );\r
+ add64( more1, more2, 0, z2, &more1, &z2 );\r
+ add64( z0, z1, 0, more1, &z0, &z1 );\r
+ *z3Ptr = z3;\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns an approximation to the 32-bit integer quotient obtained by dividing\r
+| `b' into the 64-bit value formed by concatenating `a0' and `a1'. The\r
+| divisor `b' must be at least 2^31. If q is the exact quotient truncated\r
+| toward zero, the approximation returned lies between q and q + 2 inclusive.\r
+| If the exact quotient q is larger than 32 bits, the maximum positive 32-bit\r
+| unsigned integer is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static bits32 estimateDiv64To32( bits32 a0, bits32 a1, bits32 b )\r
+{\r
+ bits32 b0, b1;\r
+ bits32 rem0, rem1, term0, term1;\r
+ bits32 z;\r
+\r
+ if ( b <= a0 ) return 0xFFFFFFFF;\r
+ b0 = b>>16;\r
+ z = ( b0<<16 <= a0 ) ? 0xFFFF0000 : ( a0 / b0 )<<16;\r
+ mul32To64( b, z, &term0, &term1 );\r
+ sub64( a0, a1, term0, term1, &rem0, &rem1 );\r
+ while ( ( (sbits32) rem0 ) < 0 ) {\r
+ z -= 0x10000;\r
+ b1 = b<<16;\r
+ add64( rem0, rem1, b0, b1, &rem0, &rem1 );\r
+ }\r
+ rem0 = ( rem0<<16 ) | ( rem1>>16 );\r
+ z |= ( b0<<16 <= rem0 ) ? 0xFFFF : rem0 / b0;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns an approximation to the square root of the 32-bit significand given\r
+| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of\r
+| `aExp' (the least significant bit) is 1, the integer returned approximates\r
+| 2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'\r
+| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either\r
+| case, the approximation returned lies strictly within +/-2 of the exact\r
+| value.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static bits32 estimateSqrt32( int16 aExp, bits32 a )\r
+{\r
+ static const bits16 sqrtOddAdjustments[] = {\r
+ 0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,\r
+ 0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67\r
+ };\r
+ static const bits16 sqrtEvenAdjustments[] = {\r
+ 0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,\r
+ 0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002\r
+ };\r
+ int8 index;\r
+ bits32 z;\r
+\r
+ index = ( a>>27 ) & 15;\r
+ if ( aExp & 1 ) {\r
+ z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];\r
+ z = ( ( a / z )<<14 ) + ( z<<15 );\r
+ a >>= 1;\r
+ }\r
+ else {\r
+ z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];\r
+ z = a / z + z;\r
+ z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );\r
+ if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );\r
+ }\r
+ return ( ( estimateDiv64To32( a, 0, z ) )>>1 ) + ( z>>1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the number of leading 0 bits before the most-significant 1 bit of\r
+| `a'. If `a' is zero, 32 is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static int8 countLeadingZeros32( bits32 a )\r
+{\r
+ static const int8 countLeadingZerosHigh[] = {\r
+ 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,\r
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\r
+ };\r
+ int8 shiftCount;\r
+\r
+ shiftCount = 0;\r
+ if ( a < 0x10000 ) {\r
+ shiftCount += 16;\r
+ a <<= 16;\r
+ }\r
+ if ( a < 0x1000000 ) {\r
+ shiftCount += 8;\r
+ a <<= 8;\r
+ }\r
+ shiftCount += countLeadingZerosHigh[ a>>24 ];\r
+ return shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 64-bit value formed by concatenating `a0' and `a1' is\r
+| equal to the 64-bit value formed by concatenating `b0' and `b1'. Otherwise,\r
+| returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag eq64( bits32 a0, bits32 a1, bits32 b0, bits32 b1 )\r
+{\r
+\r
+ return ( a0 == b0 ) && ( a1 == b1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 64-bit value formed by concatenating `a0' and `a1' is less\r
+| than or equal to the 64-bit value formed by concatenating `b0' and `b1'.\r
+| Otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag le64( bits32 a0, bits32 a1, bits32 b0, bits32 b1 )\r
+{\r
+\r
+ return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 64-bit value formed by concatenating `a0' and `a1' is less\r
+| than the 64-bit value formed by concatenating `b0' and `b1'. Otherwise,\r
+| returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag lt64( bits32 a0, bits32 a1, bits32 b0, bits32 b1 )\r
+{\r
+\r
+ return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 64-bit value formed by concatenating `a0' and `a1' is not\r
+| equal to the 64-bit value formed by concatenating `b0' and `b1'. Otherwise,\r
+| returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag ne64( bits32 a0, bits32 a1, bits32 b0, bits32 b1 )\r
+{\r
+\r
+ return ( a0 != b0 ) || ( a1 != b1 );\r
+\r
+}\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include "milieu.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Floating-point rounding mode and exception flags.\r
+*----------------------------------------------------------------------------*/\r
+int8 float_rounding_mode = float_round_nearest_even;\r
+int8 float_exception_flags = 0;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Primitive arithmetic functions, including multi-word arithmetic, and\r
+| division and square root approximations. (Can be specialized to target if\r
+| desired.)\r
+*----------------------------------------------------------------------------*/\r
+#include "softfloat-macros"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Functions and definitions to determine: (1) whether tininess for underflow\r
+| is detected before or after rounding by default, (2) what (if anything)\r
+| happens when exceptions are raised, (3) how signaling NaNs are distinguished\r
+| from quiet NaNs, (4) the default generated quiet NaNs, and (4) how NaNs\r
+| are propagated from function inputs to output. These details are target-\r
+| specific.\r
+*----------------------------------------------------------------------------*/\r
+#include "softfloat-specialize"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the fraction bits of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits32 extractFloat32Frac( float32 a )\r
+{\r
+\r
+ return a & 0x007FFFFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE int16 extractFloat32Exp( float32 a )\r
+{\r
+\r
+ return ( a>>23 ) & 0xFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag extractFloat32Sign( float32 a )\r
+{\r
+\r
+ return a>>31;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal single-precision floating-point value represented\r
+| by the denormalized significand `aSig'. The normalized exponent and\r
+| significand are stored at the locations pointed to by `zExpPtr' and\r
+| `zSigPtr', respectively.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static void\r
+ normalizeFloat32Subnormal( bits32 aSig, int16 *zExpPtr, bits32 *zSigPtr )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros32( aSig ) - 8;\r
+ *zSigPtr = aSig<<shiftCount;\r
+ *zExpPtr = 1 - shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
+| single-precision floating-point value, returning the result. After being\r
+| shifted into the proper positions, the three fields are simply added\r
+| together to form the result. This means that any integer portion of `zSig'\r
+| will be added into the exponent. Since a properly normalized significand\r
+| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
+| than the desired result exponent whenever `zSig' is a complete, normalized\r
+| significand.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE float32 packFloat32( flag zSign, int16 zExp, bits32 zSig )\r
+{\r
+\r
+ return ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper single-precision floating-\r
+| point value corresponding to the abstract input. Ordinarily, the abstract\r
+| value is simply rounded and packed into the single-precision format, with\r
+| the inexact exception raised if the abstract input cannot be represented\r
+| exactly. However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned. If the abstract value is too small, the input value is rounded to\r
+| a subnormal number, and the underflow and inexact exceptions are raised if\r
+| the abstract input cannot be represented exactly as a subnormal single-\r
+| precision floating-point number.\r
+| The input significand `zSig' has its binary point between bits 30\r
+| and 29, which is 7 bits to the left of the usual location. This shifted\r
+| significand must be normalized or smaller. If `zSig' is not normalized,\r
+| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
+| and it must not require rounding. In the usual case that `zSig' is\r
+| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
+| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven;\r
+ int8 roundIncrement, roundBits;\r
+ flag isTiny;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = roundingMode == float_round_nearest_even;\r
+ roundIncrement = 0x40;\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ roundIncrement = 0;\r
+ }\r
+ else {\r
+ roundIncrement = 0x7F;\r
+ if ( zSign ) {\r
+ if ( roundingMode == float_round_up ) roundIncrement = 0;\r
+ }\r
+ else {\r
+ if ( roundingMode == float_round_down ) roundIncrement = 0;\r
+ }\r
+ }\r
+ }\r
+ roundBits = zSig & 0x7F;\r
+ if ( 0xFD <= (bits16) zExp ) {\r
+ if ( ( 0xFD < zExp )\r
+ || ( ( zExp == 0xFD )\r
+ && ( (sbits32) ( zSig + roundIncrement ) < 0 ) )\r
+ ) {\r
+ float_raise( float_flag_overflow | float_flag_inexact );\r
+ return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );\r
+ }\r
+ if ( zExp < 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < -1 )\r
+ || ( zSig + roundIncrement < 0x80000000 );\r
+ shift32RightJamming( zSig, - zExp, &zSig );\r
+ zExp = 0;\r
+ roundBits = zSig & 0x7F;\r
+ if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
+ }\r
+ }\r
+ if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
+ zSig = ( zSig + roundIncrement )>>7;\r
+ zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );\r
+ if ( zSig == 0 ) zExp = 0;\r
+ return packFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper single-precision floating-\r
+| point value corresponding to the abstract input. This routine is just like\r
+| `roundAndPackFloat32' except that `zSig' does not have to be normalized.\r
+| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
+| floating-point exponent.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32\r
+ normalizeRoundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros32( zSig ) - 1;\r
+ return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the least-significant 32 fraction bits of the double-precision\r
+| floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits32 extractFloat64Frac1( float64 a )\r
+{\r
+\r
+ return a.low;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the most-significant 20 fraction bits of the double-precision\r
+| floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits32 extractFloat64Frac0( float64 a )\r
+{\r
+\r
+ return a.high & 0x000FFFFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE int16 extractFloat64Exp( float64 a )\r
+{\r
+\r
+ return ( a.high>>20 ) & 0x7FF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag extractFloat64Sign( float64 a )\r
+{\r
+\r
+ return a.high>>31;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal double-precision floating-point value represented\r
+| by the denormalized significand formed by the concatenation of `aSig0' and\r
+| `aSig1'. The normalized exponent is stored at the location pointed to by\r
+| `zExpPtr'. The most significant 21 bits of the normalized significand are\r
+| stored at the location pointed to by `zSig0Ptr', and the least significant\r
+| 32 bits of the normalized significand are stored at the location pointed to\r
+| by `zSig1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static void\r
+ normalizeFloat64Subnormal(\r
+ bits32 aSig0,\r
+ bits32 aSig1,\r
+ int16 *zExpPtr,\r
+ bits32 *zSig0Ptr,\r
+ bits32 *zSig1Ptr\r
+ )\r
+{\r
+ int8 shiftCount;\r
+\r
+ if ( aSig0 == 0 ) {\r
+ shiftCount = countLeadingZeros32( aSig1 ) - 11;\r
+ if ( shiftCount < 0 ) {\r
+ *zSig0Ptr = aSig1>>( - shiftCount );\r
+ *zSig1Ptr = aSig1<<( shiftCount & 31 );\r
+ }\r
+ else {\r
+ *zSig0Ptr = aSig1<<shiftCount;\r
+ *zSig1Ptr = 0;\r
+ }\r
+ *zExpPtr = - shiftCount - 31;\r
+ }\r
+ else {\r
+ shiftCount = countLeadingZeros32( aSig0 ) - 11;\r
+ shortShift64Left( aSig0, aSig1, shiftCount, zSig0Ptr, zSig1Ptr );\r
+ *zExpPtr = 1 - shiftCount;\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', the exponent `zExp', and the significand formed by\r
+| the concatenation of `zSig0' and `zSig1' into a double-precision floating-\r
+| point value, returning the result. After being shifted into the proper\r
+| positions, the three fields `zSign', `zExp', and `zSig0' are simply added\r
+| together to form the most significant 32 bits of the result. This means\r
+| that any integer portion of `zSig0' will be added into the exponent. Since\r
+| a properly normalized significand will have an integer portion equal to 1,\r
+| the `zExp' input should be 1 less than the desired result exponent whenever\r
+| `zSig0' and `zSig1' concatenated form a complete, normalized significand.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE float64\r
+ packFloat64( flag zSign, int16 zExp, bits32 zSig0, bits32 zSig1 )\r
+{\r
+ float64 z;\r
+\r
+ z.low = zSig1;\r
+ z.high = ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<20 ) + zSig0;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and extended significand formed by the concatenation of `zSig0', `zSig1',\r
+| and `zSig2', and returns the proper double-precision floating-point value\r
+| corresponding to the abstract input. Ordinarily, the abstract value is\r
+| simply rounded and packed into the double-precision format, with the inexact\r
+| exception raised if the abstract input cannot be represented exactly.\r
+| However, if the abstract value is too large, the overflow and inexact\r
+| exceptions are raised and an infinity or maximal finite value is returned.\r
+| If the abstract value is too small, the input value is rounded to a\r
+| subnormal number, and the underflow and inexact exceptions are raised if the\r
+| abstract input cannot be represented exactly as a subnormal double-precision\r
+| floating-point number.\r
+| The input significand must be normalized or smaller. If the input\r
+| significand is not normalized, `zExp' must be 0; in that case, the result\r
+| returned is a subnormal number, and it must not require rounding. In the\r
+| usual case that the input significand is normalized, `zExp' must be 1 less\r
+| than the ``true'' floating-point exponent. The handling of underflow and\r
+| overflow follows the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64\r
+ roundAndPackFloat64(\r
+ flag zSign, int16 zExp, bits32 zSig0, bits32 zSig1, bits32 zSig2 )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven, increment, isTiny;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ increment = ( (sbits32) zSig2 < 0 );\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ increment = 0;\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && zSig2;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && zSig2;\r
+ }\r
+ }\r
+ }\r
+ if ( 0x7FD <= (bits16) zExp ) {\r
+ if ( ( 0x7FD < zExp )\r
+ || ( ( zExp == 0x7FD )\r
+ && eq64( 0x001FFFFF, 0xFFFFFFFF, zSig0, zSig1 )\r
+ && increment\r
+ )\r
+ ) {\r
+ float_raise( float_flag_overflow | float_flag_inexact );\r
+ if ( ( roundingMode == float_round_to_zero )\r
+ || ( zSign && ( roundingMode == float_round_up ) )\r
+ || ( ! zSign && ( roundingMode == float_round_down ) )\r
+ ) {\r
+ return packFloat64( zSign, 0x7FE, 0x000FFFFF, 0xFFFFFFFF );\r
+ }\r
+ return packFloat64( zSign, 0x7FF, 0, 0 );\r
+ }\r
+ if ( zExp < 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < -1 )\r
+ || ! increment\r
+ || lt64( zSig0, zSig1, 0x001FFFFF, 0xFFFFFFFF );\r
+ shift64ExtraRightJamming(\r
+ zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 );\r
+ zExp = 0;\r
+ if ( isTiny && zSig2 ) float_raise( float_flag_underflow );\r
+ if ( roundNearestEven ) {\r
+ increment = ( (sbits32) zSig2 < 0 );\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && zSig2;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && zSig2;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ if ( zSig2 ) float_exception_flags |= float_flag_inexact;\r
+ if ( increment ) {\r
+ add64( zSig0, zSig1, 0, 1, &zSig0, &zSig1 );\r
+ zSig1 &= ~ ( ( zSig2 + zSig2 == 0 ) & roundNearestEven );\r
+ }\r
+ else {\r
+ if ( ( zSig0 | zSig1 ) == 0 ) zExp = 0;\r
+ }\r
+ return packFloat64( zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand formed by the concatenation of `zSig0' and `zSig1', and\r
+| returns the proper double-precision floating-point value corresponding\r
+| to the abstract input. This routine is just like `roundAndPackFloat64'\r
+| except that the input significand has fewer bits and does not have to be\r
+| normalized. In all cases, `zExp' must be 1 less than the ``true'' floating-\r
+| point exponent.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64\r
+ normalizeRoundAndPackFloat64(\r
+ flag zSign, int16 zExp, bits32 zSig0, bits32 zSig1 )\r
+{\r
+ int8 shiftCount;\r
+ bits32 zSig2;\r
+\r
+ if ( zSig0 == 0 ) {\r
+ zSig0 = zSig1;\r
+ zSig1 = 0;\r
+ zExp -= 32;\r
+ }\r
+ shiftCount = countLeadingZeros32( zSig0 ) - 11;\r
+ if ( 0 <= shiftCount ) {\r
+ zSig2 = 0;\r
+ shortShift64Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
+ }\r
+ else {\r
+ shift64ExtraRightJamming(\r
+ zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 );\r
+ }\r
+ zExp -= shiftCount;\r
+ return roundAndPackFloat64( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 32-bit two's complement integer `a' to\r
+| the single-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 int32_to_float32( int32 a )\r
+{\r
+ flag zSign;\r
+\r
+ if ( a == 0 ) return 0;\r
+ if ( a == (sbits32) 0x80000000 ) return packFloat32( 1, 0x9E, 0 );\r
+ zSign = ( a < 0 );\r
+ return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 32-bit two's complement integer `a' to\r
+| the double-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 int32_to_float64( int32 a )\r
+{\r
+ flag zSign;\r
+ bits32 absA;\r
+ int8 shiftCount;\r
+ bits32 zSig0, zSig1;\r
+\r
+ if ( a == 0 ) return packFloat64( 0, 0, 0, 0 );\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros32( absA ) - 11;\r
+ if ( 0 <= shiftCount ) {\r
+ zSig0 = absA<<shiftCount;\r
+ zSig1 = 0;\r
+ }\r
+ else {\r
+ shift64Right( absA, 0, - shiftCount, &zSig0, &zSig1 );\r
+ }\r
+ return packFloat64( zSign, 0x412 - shiftCount, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float32_to_int32( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig, aSigExtra;\r
+ int32 z;\r
+ int8 roundingMode;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ shiftCount = aExp - 0x96;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( 0x9E <= aExp ) {\r
+ if ( a != 0xCF000000 ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) {\r
+ return 0x7FFFFFFF;\r
+ }\r
+ }\r
+ return (sbits32) 0x80000000;\r
+ }\r
+ z = ( aSig | 0x00800000 )<<shiftCount;\r
+ if ( aSign ) z = - z;\r
+ }\r
+ else {\r
+ if ( aExp < 0x7E ) {\r
+ aSigExtra = aExp | aSig;\r
+ z = 0;\r
+ }\r
+ else {\r
+ aSig |= 0x00800000;\r
+ aSigExtra = aSig<<( shiftCount & 31 );\r
+ z = aSig>>( - shiftCount );\r
+ }\r
+ if ( aSigExtra ) float_exception_flags |= float_flag_inexact;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ if ( (sbits32) aSigExtra < 0 ) {\r
+ ++z;\r
+ if ( (bits32) ( aSigExtra<<1 ) == 0 ) z &= ~1;\r
+ }\r
+ if ( aSign ) z = - z;\r
+ }\r
+ else {\r
+ aSigExtra = ( aSigExtra != 0 );\r
+ if ( aSign ) {\r
+ z += ( roundingMode == float_round_down ) & aSigExtra;\r
+ z = - z;\r
+ }\r
+ else {\r
+ z += ( roundingMode == float_round_up ) & aSigExtra;\r
+ }\r
+ }\r
+ }\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero.\r
+| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\r
+| the conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float32_to_int32_round_to_zero( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig;\r
+ int32 z;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ shiftCount = aExp - 0x9E;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( a != 0xCF000000 ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF;\r
+ }\r
+ return (sbits32) 0x80000000;\r
+ }\r
+ else if ( aExp <= 0x7E ) {\r
+ if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ aSig = ( aSig | 0x00800000 )<<8;\r
+ z = aSig>>( - shiftCount );\r
+ if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ if ( aSign ) z = - z;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the double-precision floating-point format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float32_to_float64( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 aSig, zSig0, zSig1;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return commonNaNToFloat64( float32ToCommonNaN( a ) );\r
+ return packFloat64( aSign, 0x7FF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat64( aSign, 0, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ --aExp;\r
+ }\r
+ shift64Right( aSig, 0, 3, &zSig0, &zSig1 );\r
+ return packFloat64( aSign, aExp + 0x380, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Rounds the single-precision floating-point value `a' to an integer,\r
+| and returns the result as a single-precision floating-point value. The\r
+| operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_round_to_int( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 lastBitMask, roundBitsMask;\r
+ int8 roundingMode;\r
+ float32 z;\r
+\r
+ aExp = extractFloat32Exp( a );\r
+ if ( 0x96 <= aExp ) {\r
+ if ( ( aExp == 0xFF ) && extractFloat32Frac( a ) ) {\r
+ return propagateFloat32NaN( a, a );\r
+ }\r
+ return a;\r
+ }\r
+ if ( aExp <= 0x7E ) {\r
+ if ( (bits32) ( a<<1 ) == 0 ) return a;\r
+ float_exception_flags |= float_flag_inexact;\r
+ aSign = extractFloat32Sign( a );\r
+ switch ( float_rounding_mode ) {\r
+ case float_round_nearest_even:\r
+ if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) {\r
+ return packFloat32( aSign, 0x7F, 0 );\r
+ }\r
+ break;\r
+ case float_round_down:\r
+ return aSign ? 0xBF800000 : 0;\r
+ case float_round_up:\r
+ return aSign ? 0x80000000 : 0x3F800000;\r
+ }\r
+ return packFloat32( aSign, 0, 0 );\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask <<= 0x96 - aExp;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z = a;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ z += lastBitMask>>1;\r
+ if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
+ z += roundBitsMask;\r
+ }\r
+ }\r
+ z &= ~ roundBitsMask;\r
+ if ( z != a ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the single-precision\r
+| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated\r
+| before being returned. `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig;\r
+ int16 expDiff;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ expDiff = aExp - bExp;\r
+ aSig <<= 6;\r
+ bSig <<= 6;\r
+ if ( 0 < expDiff ) {\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig |= 0x20000000;\r
+ }\r
+ shift32RightJamming( bSig, expDiff, &bSig );\r
+ zExp = aExp;\r
+ }\r
+ else if ( expDiff < 0 ) {\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig |= 0x20000000;\r
+ }\r
+ shift32RightJamming( aSig, - expDiff, &aSig );\r
+ zExp = bExp;\r
+ }\r
+ else {\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig | bSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( aExp == 0 ) return packFloat32( zSign, 0, ( aSig + bSig )>>6 );\r
+ zSig = 0x40000000 + aSig + bSig;\r
+ zExp = aExp;\r
+ goto roundAndPack;\r
+ }\r
+ aSig |= 0x20000000;\r
+ zSig = ( aSig + bSig )<<1;\r
+ --zExp;\r
+ if ( (sbits32) zSig < 0 ) {\r
+ zSig = aSig + bSig;\r
+ ++zExp;\r
+ }\r
+ roundAndPack:\r
+ return roundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the single-\r
+| precision floating-point values `a' and `b'. If `zSign' is 1, the\r
+| difference is negated before being returned. `zSign' is ignored if the\r
+| result is a NaN. The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig;\r
+ int16 expDiff;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ expDiff = aExp - bExp;\r
+ aSig <<= 7;\r
+ bSig <<= 7;\r
+ if ( 0 < expDiff ) goto aExpBigger;\r
+ if ( expDiff < 0 ) goto bExpBigger;\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig | bSig ) return propagateFloat32NaN( a, b );\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ aExp = 1;\r
+ bExp = 1;\r
+ }\r
+ if ( bSig < aSig ) goto aBigger;\r
+ if ( aSig < bSig ) goto bBigger;\r
+ return packFloat32( float_rounding_mode == float_round_down, 0, 0 );\r
+ bExpBigger:\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return packFloat32( zSign ^ 1, 0xFF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig |= 0x40000000;\r
+ }\r
+ shift32RightJamming( aSig, - expDiff, &aSig );\r
+ bSig |= 0x40000000;\r
+ bBigger:\r
+ zSig = bSig - aSig;\r
+ zExp = bExp;\r
+ zSign ^= 1;\r
+ goto normalizeRoundAndPack;\r
+ aExpBigger:\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig |= 0x40000000;\r
+ }\r
+ shift32RightJamming( bSig, expDiff, &bSig );\r
+ aSig |= 0x40000000;\r
+ aBigger:\r
+ zSig = aSig - bSig;\r
+ zExp = aExp;\r
+ normalizeRoundAndPack:\r
+ --zExp;\r
+ return normalizeRoundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the single-precision floating-point values `a'\r
+| and `b'. The operation is performed according to the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_add( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return addFloat32Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return subFloat32Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the single-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_sub( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return subFloat32Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return addFloat32Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of multiplying the single-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_mul( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig0, zSig1;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ bSign = extractFloat32Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {\r
+ return propagateFloat32NaN( a, b );\r
+ }\r
+ if ( ( bExp | bSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );\r
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ zExp = aExp + bExp - 0x7F;\r
+ aSig = ( aSig | 0x00800000 )<<7;\r
+ bSig = ( bSig | 0x00800000 )<<8;\r
+ mul32To64( aSig, bSig, &zSig0, &zSig1 );\r
+ zSig0 |= ( zSig1 != 0 );\r
+ if ( 0 <= (sbits32) ( zSig0<<1 ) ) {\r
+ zSig0 <<= 1;\r
+ --zExp;\r
+ }\r
+ return roundAndPackFloat32( zSign, zExp, zSig0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of dividing the single-precision floating-point value `a'\r
+| by the corresponding value `b'. The operation is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_div( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig, rem0, rem1, term0, term1;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ bSign = extractFloat32Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, b );\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return packFloat32( zSign, 0, 0 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ float_raise( float_flag_divbyzero );\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = aExp - bExp + 0x7D;\r
+ aSig = ( aSig | 0x00800000 )<<7;\r
+ bSig = ( bSig | 0x00800000 )<<8;\r
+ if ( bSig <= ( aSig + aSig ) ) {\r
+ aSig >>= 1;\r
+ ++zExp;\r
+ }\r
+ zSig = estimateDiv64To32( aSig, 0, bSig );\r
+ if ( ( zSig & 0x3F ) <= 2 ) {\r
+ mul32To64( bSig, zSig, &term0, &term1 );\r
+ sub64( aSig, 0, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits32) rem0 < 0 ) {\r
+ --zSig;\r
+ add64( rem0, rem1, 0, bSig, &rem0, &rem1 );\r
+ }\r
+ zSig |= ( rem1 != 0 );\r
+ }\r
+ return roundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the remainder of the single-precision floating-point value `a'\r
+| with respect to the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_rem( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, expDiff;\r
+ bits32 aSig, bSig, q, allZero, alternateASig;\r
+ sbits32 sigMean;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {\r
+ return propagateFloat32NaN( a, b );\r
+ }\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return a;\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ expDiff = aExp - bExp;\r
+ aSig = ( aSig | 0x00800000 )<<8;\r
+ bSig = ( bSig | 0x00800000 )<<8;\r
+ if ( expDiff < 0 ) {\r
+ if ( expDiff < -1 ) return a;\r
+ aSig >>= 1;\r
+ }\r
+ q = ( bSig <= aSig );\r
+ if ( q ) aSig -= bSig;\r
+ expDiff -= 32;\r
+ while ( 0 < expDiff ) {\r
+ q = estimateDiv64To32( aSig, 0, bSig );\r
+ q = ( 2 < q ) ? q - 2 : 0;\r
+ aSig = - ( ( bSig>>2 ) * q );\r
+ expDiff -= 30;\r
+ }\r
+ expDiff += 32;\r
+ if ( 0 < expDiff ) {\r
+ q = estimateDiv64To32( aSig, 0, bSig );\r
+ q = ( 2 < q ) ? q - 2 : 0;\r
+ q >>= 32 - expDiff;\r
+ bSig >>= 2;\r
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;\r
+ }\r
+ else {\r
+ aSig >>= 2;\r
+ bSig >>= 2;\r
+ }\r
+ do {\r
+ alternateASig = aSig;\r
+ ++q;\r
+ aSig -= bSig;\r
+ } while ( 0 <= (sbits32) aSig );\r
+ sigMean = aSig + alternateASig;\r
+ if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {\r
+ aSig = alternateASig;\r
+ }\r
+ zSign = ( (sbits32) aSig < 0 );\r
+ if ( zSign ) aSig = - aSig;\r
+ return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the square root of the single-precision floating-point value `a'.\r
+| The operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_sqrt( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, zExp;\r
+ bits32 aSig, zSig, rem0, rem1, term0, term1;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, 0 );\r
+ if ( ! aSign ) return a;\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( aSign ) {\r
+ if ( ( aExp | aSig ) == 0 ) return a;\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return 0;\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;\r
+ aSig = ( aSig | 0x00800000 )<<8;\r
+ zSig = estimateSqrt32( aExp, aSig ) + 2;\r
+ if ( ( zSig & 0x7F ) <= 5 ) {\r
+ if ( zSig < 2 ) {\r
+ zSig = 0x7FFFFFFF;\r
+ goto roundAndPack;\r
+ }\r
+ else {\r
+ aSig >>= aExp & 1;\r
+ mul32To64( zSig, zSig, &term0, &term1 );\r
+ sub64( aSig, 0, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits32) rem0 < 0 ) {\r
+ --zSig;\r
+ shortShift64Left( 0, zSig, 1, &term0, &term1 );\r
+ term1 |= 1;\r
+ add64( rem0, rem1, term0, term1, &rem0, &rem1 );\r
+ }\r
+ zSig |= ( ( rem0 | rem1 ) != 0 );\r
+ }\r
+ }\r
+ shift32RightJamming( zSig, 1, &zSig );\r
+ roundAndPack:\r
+ return roundAndPackFloat32( 0, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_eq( float32 a, float32 b )\r
+{\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than\r
+| or equal to the corresponding value `b', and 0 otherwise. The comparison\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_le( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+ return ( a == b ) || ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_lt( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );\r
+ return ( a != b ) && ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The invalid exception is\r
+| raised if either operand is a NaN. Otherwise, the comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_eq_signaling( float32 a, float32 b )\r
+{\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than or\r
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not\r
+| cause an exception. Otherwise, the comparison is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_le_quiet( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+ int16 aExp, bExp;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+ return ( a == b ) || ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an\r
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_lt_quiet( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );\r
+ return ( a != b ) && ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float64_to_int32( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig0, aSig1, absZ, aSigExtra;\r
+ int32 z;\r
+ int8 roundingMode;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ shiftCount = aExp - 0x413;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( 0x41E < aExp ) {\r
+ if ( ( aExp == 0x7FF ) && ( aSig0 | aSig1 ) ) aSign = 0;\r
+ goto invalid;\r
+ }\r
+ shortShift64Left(\r
+ aSig0 | 0x00100000, aSig1, shiftCount, &absZ, &aSigExtra );\r
+ if ( 0x80000000 < absZ ) goto invalid;\r
+ }\r
+ else {\r
+ aSig1 = ( aSig1 != 0 );\r
+ if ( aExp < 0x3FE ) {\r
+ aSigExtra = aExp | aSig0 | aSig1;\r
+ absZ = 0;\r
+ }\r
+ else {\r
+ aSig0 |= 0x00100000;\r
+ aSigExtra = ( aSig0<<( shiftCount & 31 ) ) | aSig1;\r
+ absZ = aSig0>>( - shiftCount );\r
+ }\r
+ }\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ if ( (sbits32) aSigExtra < 0 ) {\r
+ ++absZ;\r
+ if ( (bits32) ( aSigExtra<<1 ) == 0 ) absZ &= ~1;\r
+ }\r
+ z = aSign ? - absZ : absZ;\r
+ }\r
+ else {\r
+ aSigExtra = ( aSigExtra != 0 );\r
+ if ( aSign ) {\r
+ z = - ( absZ\r
+ + ( ( roundingMode == float_round_down ) & aSigExtra ) );\r
+ }\r
+ else {\r
+ z = absZ + ( ( roundingMode == float_round_up ) & aSigExtra );\r
+ }\r
+ }\r
+ if ( ( aSign ^ ( z < 0 ) ) && z ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
+ }\r
+ if ( aSigExtra ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero.\r
+| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\r
+| the conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float64_to_int32_round_to_zero( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig0, aSig1, absZ, aSigExtra;\r
+ int32 z;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ shiftCount = aExp - 0x413;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( 0x41E < aExp ) {\r
+ if ( ( aExp == 0x7FF ) && ( aSig0 | aSig1 ) ) aSign = 0;\r
+ goto invalid;\r
+ }\r
+ shortShift64Left(\r
+ aSig0 | 0x00100000, aSig1, shiftCount, &absZ, &aSigExtra );\r
+ }\r
+ else {\r
+ if ( aExp < 0x3FF ) {\r
+ if ( aExp | aSig0 | aSig1 ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return 0;\r
+ }\r
+ aSig0 |= 0x00100000;\r
+ aSigExtra = ( aSig0<<( shiftCount & 31 ) ) | aSig1;\r
+ absZ = aSig0>>( - shiftCount );\r
+ }\r
+ z = aSign ? - absZ : absZ;\r
+ if ( ( aSign ^ ( z < 0 ) ) && z ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
+ }\r
+ if ( aSigExtra ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the single-precision floating-point format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float64_to_float32( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 aSig0, aSig1, zSig;\r
+ bits32 allZero;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 ) {\r
+ return commonNaNToFloat32( float64ToCommonNaN( a ) );\r
+ }\r
+ return packFloat32( aSign, 0xFF, 0 );\r
+ }\r
+ shift64RightJamming( aSig0, aSig1, 22, &allZero, &zSig );\r
+ if ( aExp ) zSig |= 0x40000000;\r
+ return roundAndPackFloat32( aSign, aExp - 0x381, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Rounds the double-precision floating-point value `a' to an integer,\r
+| and returns the result as a double-precision floating-point value. The\r
+| operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_round_to_int( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 lastBitMask, roundBitsMask;\r
+ int8 roundingMode;\r
+ float64 z;\r
+\r
+ aExp = extractFloat64Exp( a );\r
+ if ( 0x413 <= aExp ) {\r
+ if ( 0x433 <= aExp ) {\r
+ if ( ( aExp == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) ) {\r
+ return propagateFloat64NaN( a, a );\r
+ }\r
+ return a;\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask = ( lastBitMask<<( 0x432 - aExp ) )<<1;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z = a;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ if ( lastBitMask ) {\r
+ add64( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low );\r
+ if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;\r
+ }\r
+ else {\r
+ if ( (sbits32) z.low < 0 ) {\r
+ ++z.high;\r
+ if ( (bits32) ( z.low<<1 ) == 0 ) z.high &= ~1;\r
+ }\r
+ }\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat64Sign( z )\r
+ ^ ( roundingMode == float_round_up ) ) {\r
+ add64( z.high, z.low, 0, roundBitsMask, &z.high, &z.low );\r
+ }\r
+ }\r
+ z.low &= ~ roundBitsMask;\r
+ }\r
+ else {\r
+ if ( aExp <= 0x3FE ) {\r
+ if ( ( ( (bits32) ( a.high<<1 ) ) | a.low ) == 0 ) return a;\r
+ float_exception_flags |= float_flag_inexact;\r
+ aSign = extractFloat64Sign( a );\r
+ switch ( float_rounding_mode ) {\r
+ case float_round_nearest_even:\r
+ if ( ( aExp == 0x3FE )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) )\r
+ ) {\r
+ return packFloat64( aSign, 0x3FF, 0, 0 );\r
+ }\r
+ break;\r
+ case float_round_down:\r
+ return\r
+ aSign ? packFloat64( 1, 0x3FF, 0, 0 )\r
+ : packFloat64( 0, 0, 0, 0 );\r
+ case float_round_up:\r
+ return\r
+ aSign ? packFloat64( 1, 0, 0, 0 )\r
+ : packFloat64( 0, 0x3FF, 0, 0 );\r
+ }\r
+ return packFloat64( aSign, 0, 0, 0 );\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask <<= 0x413 - aExp;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z.low = 0;\r
+ z.high = a.high;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ z.high += lastBitMask>>1;\r
+ if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) {\r
+ z.high &= ~ lastBitMask;\r
+ }\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat64Sign( z )\r
+ ^ ( roundingMode == float_round_up ) ) {\r
+ z.high |= ( a.low != 0 );\r
+ z.high += roundBitsMask;\r
+ }\r
+ }\r
+ z.high &= ~ roundBitsMask;\r
+ }\r
+ if ( ( z.low != a.low ) || ( z.high != a.high ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the double-precision\r
+| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated\r
+| before being returned. `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\r
+ int16 expDiff;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ bSig1 = extractFloat64Frac1( b );\r
+ bSig0 = extractFloat64Frac0( b );\r
+ bExp = extractFloat64Exp( b );\r
+ expDiff = aExp - bExp;\r
+ if ( 0 < expDiff ) {\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig0 |= 0x00100000;\r
+ }\r
+ shift64ExtraRightJamming(\r
+ bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 );\r
+ zExp = aExp;\r
+ }\r
+ else if ( expDiff < 0 ) {\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat64NaN( a, b );\r
+ return packFloat64( zSign, 0x7FF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig0 |= 0x00100000;\r
+ }\r
+ shift64ExtraRightJamming(\r
+ aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 );\r
+ zExp = bExp;\r
+ }\r
+ else {\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 | bSig0 | bSig1 ) {\r
+ return propagateFloat64NaN( a, b );\r
+ }\r
+ return a;\r
+ }\r
+ add64( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
+ if ( aExp == 0 ) return packFloat64( zSign, 0, zSig0, zSig1 );\r
+ zSig2 = 0;\r
+ zSig0 |= 0x00200000;\r
+ zExp = aExp;\r
+ goto shiftRight1;\r
+ }\r
+ aSig0 |= 0x00100000;\r
+ add64( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
+ --zExp;\r
+ if ( zSig0 < 0x00200000 ) goto roundAndPack;\r
+ ++zExp;\r
+ shiftRight1:\r
+ shift64ExtraRightJamming( zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\r
+ roundAndPack:\r
+ return roundAndPackFloat64( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the double-\r
+| precision floating-point values `a' and `b'. If `zSign' is 1, the\r
+| difference is negated before being returned. `zSign' is ignored if the\r
+| result is a NaN. The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;\r
+ int16 expDiff;\r
+ float64 z;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ bSig1 = extractFloat64Frac1( b );\r
+ bSig0 = extractFloat64Frac0( b );\r
+ bExp = extractFloat64Exp( b );\r
+ expDiff = aExp - bExp;\r
+ shortShift64Left( aSig0, aSig1, 10, &aSig0, &aSig1 );\r
+ shortShift64Left( bSig0, bSig1, 10, &bSig0, &bSig1 );\r
+ if ( 0 < expDiff ) goto aExpBigger;\r
+ if ( expDiff < 0 ) goto bExpBigger;\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 | bSig0 | bSig1 ) {\r
+ return propagateFloat64NaN( a, b );\r
+ }\r
+ float_raise( float_flag_invalid );\r
+ z.low = float64_default_nan_low;\r
+ z.high = float64_default_nan_high;\r
+ return z;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ aExp = 1;\r
+ bExp = 1;\r
+ }\r
+ if ( bSig0 < aSig0 ) goto aBigger;\r
+ if ( aSig0 < bSig0 ) goto bBigger;\r
+ if ( bSig1 < aSig1 ) goto aBigger;\r
+ if ( aSig1 < bSig1 ) goto bBigger;\r
+ return packFloat64( float_rounding_mode == float_round_down, 0, 0, 0 );\r
+ bExpBigger:\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat64NaN( a, b );\r
+ return packFloat64( zSign ^ 1, 0x7FF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig0 |= 0x40000000;\r
+ }\r
+ shift64RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );\r
+ bSig0 |= 0x40000000;\r
+ bBigger:\r
+ sub64( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 );\r
+ zExp = bExp;\r
+ zSign ^= 1;\r
+ goto normalizeRoundAndPack;\r
+ aExpBigger:\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig0 |= 0x40000000;\r
+ }\r
+ shift64RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 );\r
+ aSig0 |= 0x40000000;\r
+ aBigger:\r
+ sub64( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
+ zExp = aExp;\r
+ normalizeRoundAndPack:\r
+ --zExp;\r
+ return normalizeRoundAndPackFloat64( zSign, zExp - 10, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the double-precision floating-point values `a'\r
+| and `b'. The operation is performed according to the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_add( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return addFloat64Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return subFloat64Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the double-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_sub( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return subFloat64Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return addFloat64Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of multiplying the double-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_mul( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;\r
+ float64 z;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ bSig1 = extractFloat64Frac1( b );\r
+ bSig0 = extractFloat64Frac0( b );\r
+ bExp = extractFloat64Exp( b );\r
+ bSign = extractFloat64Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FF ) {\r
+ if ( ( aSig0 | aSig1 )\r
+ || ( ( bExp == 0x7FF ) && ( bSig0 | bSig1 ) ) ) {\r
+ return propagateFloat64NaN( a, b );\r
+ }\r
+ if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid;\r
+ return packFloat64( zSign, 0x7FF, 0, 0 );\r
+ }\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat64NaN( a, b );\r
+ if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float64_default_nan_low;\r
+ z.high = float64_default_nan_high;\r
+ return z;\r
+ }\r
+ return packFloat64( zSign, 0x7FF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloat64( zSign, 0, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( ( bSig0 | bSig1 ) == 0 ) return packFloat64( zSign, 0, 0, 0 );\r
+ normalizeFloat64Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
+ }\r
+ zExp = aExp + bExp - 0x400;\r
+ aSig0 |= 0x00100000;\r
+ shortShift64Left( bSig0, bSig1, 12, &bSig0, &bSig1 );\r
+ mul64To128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 );\r
+ add64( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 );\r
+ zSig2 |= ( zSig3 != 0 );\r
+ if ( 0x00200000 <= zSig0 ) {\r
+ shift64ExtraRightJamming(\r
+ zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\r
+ ++zExp;\r
+ }\r
+ return roundAndPackFloat64( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of dividing the double-precision floating-point value `a'\r
+| by the corresponding value `b'. The operation is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_div( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\r
+ bits32 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
+ float64 z;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ bSig1 = extractFloat64Frac1( b );\r
+ bSig0 = extractFloat64Frac0( b );\r
+ bExp = extractFloat64Exp( b );\r
+ bSign = extractFloat64Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat64NaN( a, b );\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat64NaN( a, b );\r
+ goto invalid;\r
+ }\r
+ return packFloat64( zSign, 0x7FF, 0, 0 );\r
+ }\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat64NaN( a, b );\r
+ return packFloat64( zSign, 0, 0, 0 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( ( bSig0 | bSig1 ) == 0 ) {\r
+ if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float64_default_nan_low;\r
+ z.high = float64_default_nan_high;\r
+ return z;\r
+ }\r
+ float_raise( float_flag_divbyzero );\r
+ return packFloat64( zSign, 0x7FF, 0, 0 );\r
+ }\r
+ normalizeFloat64Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloat64( zSign, 0, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ zExp = aExp - bExp + 0x3FD;\r
+ shortShift64Left( aSig0 | 0x00100000, aSig1, 11, &aSig0, &aSig1 );\r
+ shortShift64Left( bSig0 | 0x00100000, bSig1, 11, &bSig0, &bSig1 );\r
+ if ( le64( bSig0, bSig1, aSig0, aSig1 ) ) {\r
+ shift64Right( aSig0, aSig1, 1, &aSig0, &aSig1 );\r
+ ++zExp;\r
+ }\r
+ zSig0 = estimateDiv64To32( aSig0, aSig1, bSig0 );\r
+ mul64By32To96( bSig0, bSig1, zSig0, &term0, &term1, &term2 );\r
+ sub96( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 );\r
+ while ( (sbits32) rem0 < 0 ) {\r
+ --zSig0;\r
+ add96( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 );\r
+ }\r
+ zSig1 = estimateDiv64To32( rem1, rem2, bSig0 );\r
+ if ( ( zSig1 & 0x3FF ) <= 4 ) {\r
+ mul64By32To96( bSig0, bSig1, zSig1, &term1, &term2, &term3 );\r
+ sub96( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 );\r
+ while ( (sbits32) rem1 < 0 ) {\r
+ --zSig1;\r
+ add96( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 );\r
+ }\r
+ zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
+ }\r
+ shift64ExtraRightJamming( zSig0, zSig1, 0, 11, &zSig0, &zSig1, &zSig2 );\r
+ return roundAndPackFloat64( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the remainder of the double-precision floating-point value `a'\r
+| with respect to the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_rem( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, expDiff;\r
+ bits32 aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2;\r
+ bits32 allZero, alternateASig0, alternateASig1, sigMean1;\r
+ sbits32 sigMean0;\r
+ float64 z;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ bSig1 = extractFloat64Frac1( b );\r
+ bSig0 = extractFloat64Frac0( b );\r
+ bExp = extractFloat64Exp( b );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( ( aSig0 | aSig1 )\r
+ || ( ( bExp == 0x7FF ) && ( bSig0 | bSig1 ) ) ) {\r
+ return propagateFloat64NaN( a, b );\r
+ }\r
+ goto invalid;\r
+ }\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( ( bSig0 | bSig1 ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float64_default_nan_low;\r
+ z.high = float64_default_nan_high;\r
+ return z;\r
+ }\r
+ normalizeFloat64Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return a;\r
+ normalizeFloat64Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ expDiff = aExp - bExp;\r
+ if ( expDiff < -1 ) return a;\r
+ shortShift64Left(\r
+ aSig0 | 0x00100000, aSig1, 11 - ( expDiff < 0 ), &aSig0, &aSig1 );\r
+ shortShift64Left( bSig0 | 0x00100000, bSig1, 11, &bSig0, &bSig1 );\r
+ q = le64( bSig0, bSig1, aSig0, aSig1 );\r
+ if ( q ) sub64( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );\r
+ expDiff -= 32;\r
+ while ( 0 < expDiff ) {\r
+ q = estimateDiv64To32( aSig0, aSig1, bSig0 );\r
+ q = ( 4 < q ) ? q - 4 : 0;\r
+ mul64By32To96( bSig0, bSig1, q, &term0, &term1, &term2 );\r
+ shortShift96Left( term0, term1, term2, 29, &term1, &term2, &allZero );\r
+ shortShift64Left( aSig0, aSig1, 29, &aSig0, &allZero );\r
+ sub64( aSig0, 0, term1, term2, &aSig0, &aSig1 );\r
+ expDiff -= 29;\r
+ }\r
+ if ( -32 < expDiff ) {\r
+ q = estimateDiv64To32( aSig0, aSig1, bSig0 );\r
+ q = ( 4 < q ) ? q - 4 : 0;\r
+ q >>= - expDiff;\r
+ shift64Right( bSig0, bSig1, 8, &bSig0, &bSig1 );\r
+ expDiff += 24;\r
+ if ( expDiff < 0 ) {\r
+ shift64Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );\r
+ }\r
+ else {\r
+ shortShift64Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 );\r
+ }\r
+ mul64By32To96( bSig0, bSig1, q, &term0, &term1, &term2 );\r
+ sub64( aSig0, aSig1, term1, term2, &aSig0, &aSig1 );\r
+ }\r
+ else {\r
+ shift64Right( aSig0, aSig1, 8, &aSig0, &aSig1 );\r
+ shift64Right( bSig0, bSig1, 8, &bSig0, &bSig1 );\r
+ }\r
+ do {\r
+ alternateASig0 = aSig0;\r
+ alternateASig1 = aSig1;\r
+ ++q;\r
+ sub64( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );\r
+ } while ( 0 <= (sbits32) aSig0 );\r
+ add64(\r
+ aSig0, aSig1, alternateASig0, alternateASig1, &sigMean0, &sigMean1 );\r
+ if ( ( sigMean0 < 0 )\r
+ || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) {\r
+ aSig0 = alternateASig0;\r
+ aSig1 = alternateASig1;\r
+ }\r
+ zSign = ( (sbits32) aSig0 < 0 );\r
+ if ( zSign ) sub64( 0, 0, aSig0, aSig1, &aSig0, &aSig1 );\r
+ return\r
+ normalizeRoundAndPackFloat64( aSign ^ zSign, bExp - 4, aSig0, aSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the square root of the double-precision floating-point value `a'.\r
+| The operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_sqrt( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, zExp;\r
+ bits32 aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0;\r
+ bits32 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
+ float64 z;\r
+\r
+ aSig1 = extractFloat64Frac1( a );\r
+ aSig0 = extractFloat64Frac0( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat64NaN( a, a );\r
+ if ( ! aSign ) return a;\r
+ goto invalid;\r
+ }\r
+ if ( aSign ) {\r
+ if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float64_default_nan_low;\r
+ z.high = float64_default_nan_high;\r
+ return z;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloat64( 0, 0, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;\r
+ aSig0 |= 0x00100000;\r
+ shortShift64Left( aSig0, aSig1, 11, &term0, &term1 );\r
+ zSig0 = ( estimateSqrt32( aExp, term0 )>>1 ) + 1;\r
+ if ( zSig0 == 0 ) zSig0 = 0x7FFFFFFF;\r
+ doubleZSig0 = zSig0 + zSig0;\r
+ shortShift64Left( aSig0, aSig1, 9 - ( aExp & 1 ), &aSig0, &aSig1 );\r
+ mul32To64( zSig0, zSig0, &term0, &term1 );\r
+ sub64( aSig0, aSig1, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits32) rem0 < 0 ) {\r
+ --zSig0;\r
+ doubleZSig0 -= 2;\r
+ add64( rem0, rem1, 0, doubleZSig0 | 1, &rem0, &rem1 );\r
+ }\r
+ zSig1 = estimateDiv64To32( rem1, 0, doubleZSig0 );\r
+ if ( ( zSig1 & 0x1FF ) <= 5 ) {\r
+ if ( zSig1 == 0 ) zSig1 = 1;\r
+ mul32To64( doubleZSig0, zSig1, &term1, &term2 );\r
+ sub64( rem1, 0, term1, term2, &rem1, &rem2 );\r
+ mul32To64( zSig1, zSig1, &term2, &term3 );\r
+ sub96( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );\r
+ while ( (sbits32) rem1 < 0 ) {\r
+ --zSig1;\r
+ shortShift64Left( 0, zSig1, 1, &term2, &term3 );\r
+ term3 |= 1;\r
+ term2 |= doubleZSig0;\r
+ add96( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );\r
+ }\r
+ zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
+ }\r
+ shift64ExtraRightJamming( zSig0, zSig1, 0, 10, &zSig0, &zSig1, &zSig2 );\r
+ return roundAndPackFloat64( 0, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_eq( float64 a, float64 b )\r
+{\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF )\r
+ && ( extractFloat64Frac0( b ) | extractFloat64Frac1( b ) ) )\r
+ ) {\r
+ if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ return\r
+ ( a.low == b.low )\r
+ && ( ( a.high == b.high )\r
+ || ( ( a.low == 0 )\r
+ && ( (bits32) ( ( a.high | b.high )<<1 ) == 0 ) )\r
+ );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than\r
+| or equal to the corresponding value `b', and 0 otherwise. The comparison\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_le( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF )\r
+ && ( extractFloat64Frac0( b ) | extractFloat64Frac1( b ) ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ || ( ( ( (bits32) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ == 0 );\r
+ }\r
+ return\r
+ aSign ? le64( b.high, b.low, a.high, a.low )\r
+ : le64( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_lt( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF )\r
+ && ( extractFloat64Frac0( b ) | extractFloat64Frac1( b ) ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ && ( ( ( (bits32) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ != 0 );\r
+ }\r
+ return\r
+ aSign ? lt64( b.high, b.low, a.high, a.low )\r
+ : lt64( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The invalid exception is\r
+| raised if either operand is a NaN. Otherwise, the comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_eq_signaling( float64 a, float64 b )\r
+{\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF )\r
+ && ( extractFloat64Frac0( b ) | extractFloat64Frac1( b ) ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ return\r
+ ( a.low == b.low )\r
+ && ( ( a.high == b.high )\r
+ || ( ( a.low == 0 )\r
+ && ( (bits32) ( ( a.high | b.high )<<1 ) == 0 ) )\r
+ );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than or\r
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not\r
+| cause an exception. Otherwise, the comparison is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_le_quiet( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF )\r
+ && ( extractFloat64Frac0( b ) | extractFloat64Frac1( b ) ) )\r
+ ) {\r
+ if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ || ( ( ( (bits32) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ == 0 );\r
+ }\r
+ return\r
+ aSign ? le64( b.high, b.low, a.high, a.low )\r
+ : le64( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an\r
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_lt_quiet( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF )\r
+ && ( extractFloat64Frac0( a ) | extractFloat64Frac1( a ) ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF )\r
+ && ( extractFloat64Frac0( b ) | extractFloat64Frac1( b ) ) )\r
+ ) {\r
+ if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ && ( ( ( (bits32) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ != 0 );\r
+ }\r
+ return\r
+ aSign ? lt64( b.high, b.low, a.high, a.low )\r
+ : lt64( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Include common integer types and flags.\r
+*----------------------------------------------------------------------------*/\r
+#include "../../../processors/!!!processor.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Symbolic Boolean literals.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ FALSE = 0,\r
+ TRUE = 1\r
+};\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Underflow tininess-detection mode, statically initialized to default value.\r
+| (The declaration in `softfloat.h' must match the `int8' type here.)\r
+*----------------------------------------------------------------------------*/\r
+int8 float_detect_tininess = float_tininess_after_rounding;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Raises the exceptions specified by `flags'. Floating-point traps can be\r
+| defined here if desired. It is currently not possible for such a trap\r
+| to substitute a result value. If traps are not implemented, this routine\r
+| should be simply `float_exception_flags |= flags;'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+void float_raise( int8 flags )\r
+{\r
+\r
+ float_exception_flags |= flags;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Internal canonical NaN format.\r
+*----------------------------------------------------------------------------*/\r
+typedef struct {\r
+ flag sign;\r
+ bits32 high, low;\r
+} commonNaNT;\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ float32_default_nan = 0xFFFFFFFF\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_nan( float32 a )\r
+{\r
+\r
+ return ( 0xFF000000 < (bits32) ( a<<1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_signaling_nan( float32 a )\r
+{\r
+\r
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float32ToCommonNaN( float32 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a>>31;\r
+ z.low = 0;\r
+ z.high = a<<9;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the single-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 commonNaNToFloat32( commonNaNT a )\r
+{\r
+\r
+ return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>9 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 propagateFloat32NaN( float32 a, float32 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float32_is_nan( a );\r
+ aIsSignalingNaN = float32_is_signaling_nan( a );\r
+ bIsNaN = float32_is_nan( b );\r
+ bIsSignalingNaN = float32_is_signaling_nan( b );\r
+ a |= 0x00400000;\r
+ b |= 0x00400000;\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsNaN ) {\r
+ return ( aIsSignalingNaN & bIsNaN ) ? b : a;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN. The `high' and\r
+| `low' values hold the most- and least-significant bits, respectively.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ float64_default_nan_high = 0xFFFFFFFF,\r
+ float64_default_nan_low = 0xFFFFFFFF\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_nan( float64 a )\r
+{\r
+\r
+ return\r
+ ( 0xFFE00000 <= (bits32) ( a.high<<1 ) )\r
+ && ( a.low || ( a.high & 0x000FFFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_signaling_nan( float64 a )\r
+{\r
+\r
+ return\r
+ ( ( ( a.high>>19 ) & 0xFFF ) == 0xFFE )\r
+ && ( a.low || ( a.high & 0x0007FFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float64ToCommonNaN( float64 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a.high>>31;\r
+ shortShift64Left( a.high, a.low, 12, &z.high, &z.low );\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the double-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 commonNaNToFloat64( commonNaNT a )\r
+{\r
+ float64 z;\r
+\r
+ shift64Right( a.high, a.low, 12, &z.high, &z.low );\r
+ z.high |= ( ( (bits32) a.sign )<<31 ) | 0x7FF80000;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 propagateFloat64NaN( float64 a, float64 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float64_is_nan( a );\r
+ aIsSignalingNaN = float64_is_signaling_nan( a );\r
+ bIsNaN = float64_is_nan( b );\r
+ bIsSignalingNaN = float64_is_signaling_nan( b );\r
+ a.high |= 0x00080000;\r
+ b.high |= 0x00080000;\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsNaN ) {\r
+ return ( aIsSignalingNaN & bIsNaN ) ? b : a;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point types.\r
+*----------------------------------------------------------------------------*/\r
+typedef !!!bits32 float32;\r
+typedef struct {\r
+ !!!bits32 high, low;\r
+} float64;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point underflow tininess-detection mode.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 float_detect_tininess;\r
+enum {\r
+ float_tininess_after_rounding = 0,\r
+ float_tininess_before_rounding = 1\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point rounding mode.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 float_rounding_mode;\r
+enum {\r
+ float_round_nearest_even = 0,\r
+ float_round_to_zero = 1,\r
+ float_round_down = 2,\r
+ float_round_up = 3\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point exception flags.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 float_exception_flags;\r
+enum {\r
+ float_flag_inexact = 1,\r
+ float_flag_underflow = 2,\r
+ float_flag_overflow = 4,\r
+ float_flag_divbyzero = 8,\r
+ float_flag_invalid = 16\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Routine to raise any or all of the software IEC/IEEE floating-point\r
+| exception flags.\r
+*----------------------------------------------------------------------------*/\r
+void float_raise( !!!int8 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE integer-to-floating-point conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+float32 int32_to_float32( !!!int32 );\r
+float64 int32_to_float64( !!!int32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+!!!int32 float32_to_int32( float32 );\r
+!!!int32 float32_to_int32_round_to_zero( float32 );\r
+float64 float32_to_float64( float32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float32 float32_round_to_int( float32 );\r
+float32 float32_add( float32, float32 );\r
+float32 float32_sub( float32, float32 );\r
+float32 float32_mul( float32, float32 );\r
+float32 float32_div( float32, float32 );\r
+float32 float32_rem( float32, float32 );\r
+float32 float32_sqrt( float32 );\r
+!!!flag float32_eq( float32, float32 );\r
+!!!flag float32_le( float32, float32 );\r
+!!!flag float32_lt( float32, float32 );\r
+!!!flag float32_eq_signaling( float32, float32 );\r
+!!!flag float32_le_quiet( float32, float32 );\r
+!!!flag float32_lt_quiet( float32, float32 );\r
+!!!flag float32_is_signaling_nan( float32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+!!!int32 float64_to_int32( float64 );\r
+!!!int32 float64_to_int32_round_to_zero( float64 );\r
+float32 float64_to_float32( float64 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float64 float64_round_to_int( float64 );\r
+float64 float64_add( float64, float64 );\r
+float64 float64_sub( float64, float64 );\r
+float64 float64_mul( float64, float64 );\r
+float64 float64_div( float64, float64 );\r
+float64 float64_rem( float64, float64 );\r
+float64 float64_sqrt( float64 );\r
+!!!flag float64_eq( float64, float64 );\r
+!!!flag float64_le( float64, float64 );\r
+!!!flag float64_lt( float64, float64 );\r
+!!!flag float64_eq_signaling( float64, float64 );\r
+!!!flag float64_le_quiet( float64, float64 );\r
+!!!flag float64_lt_quiet( float64, float64 );\r
+!!!flag float64_is_signaling_nan( float64 );\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include <stdlib.h>\r
+#include <stdarg.h>\r
+#include <string.h>\r
+#include <stdio.h>\r
+#include <time.h>\r
+#include "milieu.h"\r
+#include "softfloat.h"\r
+\r
+enum {\r
+ minIterations = 1000\r
+};\r
+\r
+void fail( const char *message, ... )\r
+{\r
+ va_list varArgs;\r
+\r
+ fputs( "timesoftfloat: ", stderr );\r
+ va_start( varArgs, message );\r
+ vfprintf( stderr, message, varArgs );\r
+ va_end( varArgs );\r
+ fputs( ".\n", stderr );\r
+ exit( EXIT_FAILURE );\r
+\r
+}\r
+\r
+static char *functionName, *roundingModeName, *tininessModeName;\r
+\r
+static void reportTime( int32 count, long clocks )\r
+{\r
+\r
+ printf(\r
+ "%8.1f kops/s: %s",\r
+ ( count / ( ( (float) clocks ) / CLOCKS_PER_SEC ) ) / 1000,\r
+ functionName\r
+ );\r
+ if ( roundingModeName ) {\r
+ fputs( ", rounding ", stdout );\r
+ fputs( roundingModeName, stdout );\r
+ if ( tininessModeName ) {\r
+ fputs( ", tininess ", stdout );\r
+ fputs( tininessModeName, stdout );\r
+ fputs( " rounding", stdout );\r
+ }\r
+ }\r
+ fputc( '\n', stdout );\r
+\r
+}\r
+\r
+enum {\r
+ numInputs_int32 = 32\r
+};\r
+\r
+static const int32 inputs_int32[ numInputs_int32 ] = {\r
+ 0xFFFFBB79, 0x405CF80F, 0x00000000, 0xFFFFFD04,\r
+ 0xFFF20002, 0x0C8EF795, 0xF00011FF, 0x000006CA,\r
+ 0x00009BFE, 0xFF4862E3, 0x9FFFEFFE, 0xFFFFFFB7,\r
+ 0x0BFF7FFF, 0x0000F37A, 0x0011DFFE, 0x00000006,\r
+ 0xFFF02006, 0xFFFFF7D1, 0x10200003, 0xDE8DF765,\r
+ 0x00003E02, 0x000019E8, 0x0008FFFE, 0xFFFFFB5C,\r
+ 0xFFDF7FFE, 0x07C42FBF, 0x0FFFE3FF, 0x040B9F13,\r
+ 0xBFFFFFF8, 0x0001BF56, 0x000017F6, 0x000A908A\r
+};\r
+\r
+static void time_a_int32_z_float32( float32 function( int32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_int32_z_float64( float64 function( int32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+enum {\r
+ numInputs_float32 = 32\r
+};\r
+\r
+static const float32 inputs_float32[ numInputs_float32 ] = {\r
+ 0x4EFA0000, 0xC1D0B328, 0x80000000, 0x3E69A31E,\r
+ 0xAF803EFF, 0x3F800000, 0x17BF8000, 0xE74A301A,\r
+ 0x4E010003, 0x7EE3C75D, 0xBD803FE0, 0xBFFEFF00,\r
+ 0x7981F800, 0x431FFFFC, 0xC100C000, 0x3D87EFFF,\r
+ 0x4103FEFE, 0xBC000007, 0xBF01F7FF, 0x4E6C6B5C,\r
+ 0xC187FFFE, 0xC58B9F13, 0x4F88007F, 0xDF004007,\r
+ 0xB7FFD7FE, 0x7E8001FB, 0x46EFFBFF, 0x31C10000,\r
+ 0xDB428661, 0x33F89B1F, 0xA3BFEFFF, 0x537BFFBE\r
+};\r
+\r
+static void time_a_float32_z_int32( int32 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float32_z_float64( float64 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_az_float32( float32 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_ab_float32_z_flag( flag function( float32, float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_abz_float32( float32 function( float32, float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static const float32 inputs_float32_pos[ numInputs_float32 ] = {\r
+ 0x4EFA0000, 0x41D0B328, 0x00000000, 0x3E69A31E,\r
+ 0x2F803EFF, 0x3F800000, 0x17BF8000, 0x674A301A,\r
+ 0x4E010003, 0x7EE3C75D, 0x3D803FE0, 0x3FFEFF00,\r
+ 0x7981F800, 0x431FFFFC, 0x4100C000, 0x3D87EFFF,\r
+ 0x4103FEFE, 0x3C000007, 0x3F01F7FF, 0x4E6C6B5C,\r
+ 0x4187FFFE, 0x458B9F13, 0x4F88007F, 0x5F004007,\r
+ 0x37FFD7FE, 0x7E8001FB, 0x46EFFBFF, 0x31C10000,\r
+ 0x5B428661, 0x33F89B1F, 0x23BFEFFF, 0x537BFFBE\r
+};\r
+\r
+static void time_az_float32_pos( float32 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32_pos[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32_pos[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+enum {\r
+ numInputs_float64 = 32\r
+};\r
+\r
+static const struct {\r
+ bits32 high, low;\r
+} inputs_float64[ numInputs_float64 ] = {\r
+ { 0x422FFFC0, 0x08000000 },\r
+ { 0xB7E00004, 0x80000000 },\r
+ { 0xF3FD2546, 0x120B7935 },\r
+ { 0x3FF00000, 0x00000000 },\r
+ { 0xCE07F766, 0xF09588D6 },\r
+ { 0x80000000, 0x00000000 },\r
+ { 0x3FCE0004, 0x00000000 },\r
+ { 0x8313B60F, 0x0032BED8 },\r
+ { 0xC1EFFFFF, 0xC0002000 },\r
+ { 0x3FB3C75D, 0x224F2B0F },\r
+ { 0x7FD00000, 0x004000FF },\r
+ { 0xA12FFF80, 0x00001FFF },\r
+ { 0x3EE00000, 0x00FE0000 },\r
+ { 0x00100000, 0x80000004 },\r
+ { 0x41CFFFFE, 0x00000020 },\r
+ { 0x40303FFF, 0xFFFFFFFD },\r
+ { 0x3FD00000, 0x3FEFFFFF },\r
+ { 0xBFD00000, 0x10000000 },\r
+ { 0xB7FC6B5C, 0x16CA55CF },\r
+ { 0x413EEB94, 0x0B9D1301 },\r
+ { 0xC7E00200, 0x001FFFFF },\r
+ { 0x47F00021, 0xFFFFFFFE },\r
+ { 0xBFFFFFFF, 0xF80000FF },\r
+ { 0xC07FFFFF, 0xE00FFFFF },\r
+ { 0x001497A6, 0x3740C5E8 },\r
+ { 0xC4BFFFE0, 0x001FFFFF },\r
+ { 0x96FFDFFE, 0xFFFFFFFF },\r
+ { 0x403FC000, 0x000001FE },\r
+ { 0xFFD00000, 0x000001F6 },\r
+ { 0x06404000, 0x02000000 },\r
+ { 0x479CEE1E, 0x4F789FE0 },\r
+ { 0xC237FFFF, 0xFFFFFDFE }\r
+};\r
+\r
+static void time_a_float64_z_int32( int32 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float64 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float64[ inputNum ].low;\r
+ a.high = inputs_float64[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float64[ inputNum ].low;\r
+ a.high = inputs_float64[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float64_z_float32( float32 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float64 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float64[ inputNum ].low;\r
+ a.high = inputs_float64[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float64[ inputNum ].low;\r
+ a.high = inputs_float64[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_az_float64( float64 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float64 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float64[ inputNum ].low;\r
+ a.high = inputs_float64[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float64[ inputNum ].low;\r
+ a.high = inputs_float64[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_ab_float64_z_flag( flag function( float64, float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+ float64 a, b;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float64[ inputNumA ].low;\r
+ a.high = inputs_float64[ inputNumA ].high;\r
+ b.low = inputs_float64[ inputNumB ].low;\r
+ b.high = inputs_float64[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float64[ inputNumA ].low;\r
+ a.high = inputs_float64[ inputNumA ].high;\r
+ b.low = inputs_float64[ inputNumB ].low;\r
+ b.high = inputs_float64[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_abz_float64( float64 function( float64, float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+ float64 a, b;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float64[ inputNumA ].low;\r
+ a.high = inputs_float64[ inputNumA ].high;\r
+ b.low = inputs_float64[ inputNumB ].low;\r
+ b.high = inputs_float64[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float64[ inputNumA ].low;\r
+ a.high = inputs_float64[ inputNumA ].high;\r
+ b.low = inputs_float64[ inputNumB ].low;\r
+ b.high = inputs_float64[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static const struct {\r
+ bits32 high, low;\r
+} inputs_float64_pos[ numInputs_float64 ] = {\r
+ { 0x422FFFC0, 0x08000000 },\r
+ { 0x37E00004, 0x80000000 },\r
+ { 0x73FD2546, 0x120B7935 },\r
+ { 0x3FF00000, 0x00000000 },\r
+ { 0x4E07F766, 0xF09588D6 },\r
+ { 0x00000000, 0x00000000 },\r
+ { 0x3FCE0004, 0x00000000 },\r
+ { 0x0313B60F, 0x0032BED8 },\r
+ { 0x41EFFFFF, 0xC0002000 },\r
+ { 0x3FB3C75D, 0x224F2B0F },\r
+ { 0x7FD00000, 0x004000FF },\r
+ { 0x212FFF80, 0x00001FFF },\r
+ { 0x3EE00000, 0x00FE0000 },\r
+ { 0x00100000, 0x80000004 },\r
+ { 0x41CFFFFE, 0x00000020 },\r
+ { 0x40303FFF, 0xFFFFFFFD },\r
+ { 0x3FD00000, 0x3FEFFFFF },\r
+ { 0x3FD00000, 0x10000000 },\r
+ { 0x37FC6B5C, 0x16CA55CF },\r
+ { 0x413EEB94, 0x0B9D1301 },\r
+ { 0x47E00200, 0x001FFFFF },\r
+ { 0x47F00021, 0xFFFFFFFE },\r
+ { 0x3FFFFFFF, 0xF80000FF },\r
+ { 0x407FFFFF, 0xE00FFFFF },\r
+ { 0x001497A6, 0x3740C5E8 },\r
+ { 0x44BFFFE0, 0x001FFFFF },\r
+ { 0x16FFDFFE, 0xFFFFFFFF },\r
+ { 0x403FC000, 0x000001FE },\r
+ { 0x7FD00000, 0x000001F6 },\r
+ { 0x06404000, 0x02000000 },\r
+ { 0x479CEE1E, 0x4F789FE0 },\r
+ { 0x4237FFFF, 0xFFFFFDFE }\r
+};\r
+\r
+static void time_az_float64_pos( float64 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float64 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float64_pos[ inputNum ].low;\r
+ a.high = inputs_float64_pos[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float64_pos[ inputNum ].low;\r
+ a.high = inputs_float64_pos[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+enum {\r
+ INT32_TO_FLOAT32 = 1,\r
+ INT32_TO_FLOAT64,\r
+ FLOAT32_TO_INT32,\r
+ FLOAT32_TO_INT32_ROUND_TO_ZERO,\r
+ FLOAT32_TO_FLOAT64,\r
+ FLOAT32_ROUND_TO_INT,\r
+ FLOAT32_ADD,\r
+ FLOAT32_SUB,\r
+ FLOAT32_MUL,\r
+ FLOAT32_DIV,\r
+ FLOAT32_REM,\r
+ FLOAT32_SQRT,\r
+ FLOAT32_EQ,\r
+ FLOAT32_LE,\r
+ FLOAT32_LT,\r
+ FLOAT32_EQ_SIGNALING,\r
+ FLOAT32_LE_QUIET,\r
+ FLOAT32_LT_QUIET,\r
+ FLOAT64_TO_INT32,\r
+ FLOAT64_TO_INT32_ROUND_TO_ZERO,\r
+ FLOAT64_TO_FLOAT32,\r
+ FLOAT64_ROUND_TO_INT,\r
+ FLOAT64_ADD,\r
+ FLOAT64_SUB,\r
+ FLOAT64_MUL,\r
+ FLOAT64_DIV,\r
+ FLOAT64_REM,\r
+ FLOAT64_SQRT,\r
+ FLOAT64_EQ,\r
+ FLOAT64_LE,\r
+ FLOAT64_LT,\r
+ FLOAT64_EQ_SIGNALING,\r
+ FLOAT64_LE_QUIET,\r
+ FLOAT64_LT_QUIET,\r
+ NUM_FUNCTIONS\r
+};\r
+\r
+static struct {\r
+ char *name;\r
+ int8 numInputs;\r
+ flag roundingMode, tininessMode;\r
+} functions[ NUM_FUNCTIONS ] = {\r
+ { 0, 0, 0, 0 },\r
+ { "int32_to_float32", 1, TRUE, FALSE },\r
+ { "int32_to_float64", 1, FALSE, FALSE },\r
+ { "float32_to_int32", 1, TRUE, FALSE },\r
+ { "float32_to_int32_round_to_zero", 1, FALSE, FALSE },\r
+ { "float32_to_float64", 1, FALSE, FALSE },\r
+ { "float32_round_to_int", 1, TRUE, FALSE },\r
+ { "float32_add", 2, TRUE, FALSE },\r
+ { "float32_sub", 2, TRUE, FALSE },\r
+ { "float32_mul", 2, TRUE, TRUE, },\r
+ { "float32_div", 2, TRUE, FALSE },\r
+ { "float32_rem", 2, FALSE, FALSE },\r
+ { "float32_sqrt", 1, TRUE, FALSE },\r
+ { "float32_eq", 2, FALSE, FALSE },\r
+ { "float32_le", 2, FALSE, FALSE },\r
+ { "float32_lt", 2, FALSE, FALSE },\r
+ { "float32_eq_signaling", 2, FALSE, FALSE },\r
+ { "float32_le_quiet", 2, FALSE, FALSE },\r
+ { "float32_lt_quiet", 2, FALSE, FALSE },\r
+ { "float64_to_int32", 1, TRUE, FALSE },\r
+ { "float64_to_int32_round_to_zero", 1, FALSE, FALSE },\r
+ { "float64_to_float32", 1, TRUE, TRUE, },\r
+ { "float64_round_to_int", 1, TRUE, FALSE },\r
+ { "float64_add", 2, TRUE, FALSE },\r
+ { "float64_sub", 2, TRUE, FALSE },\r
+ { "float64_mul", 2, TRUE, TRUE, },\r
+ { "float64_div", 2, TRUE, FALSE },\r
+ { "float64_rem", 2, FALSE, FALSE },\r
+ { "float64_sqrt", 1, TRUE, FALSE },\r
+ { "float64_eq", 2, FALSE, FALSE },\r
+ { "float64_le", 2, FALSE, FALSE },\r
+ { "float64_lt", 2, FALSE, FALSE },\r
+ { "float64_eq_signaling", 2, FALSE, FALSE },\r
+ { "float64_le_quiet", 2, FALSE, FALSE },\r
+ { "float64_lt_quiet", 2, FALSE, FALSE }\r
+};\r
+\r
+enum {\r
+ ROUND_NEAREST_EVEN = 1,\r
+ ROUND_TO_ZERO,\r
+ ROUND_DOWN,\r
+ ROUND_UP,\r
+ NUM_ROUNDINGMODES\r
+};\r
+enum {\r
+ TININESS_BEFORE_ROUNDING = 1,\r
+ TININESS_AFTER_ROUNDING,\r
+ NUM_TININESSMODES\r
+};\r
+\r
+static void\r
+ timeFunctionVariety(\r
+ uint8 functionCode, int8 roundingMode, int8 tininessMode )\r
+{\r
+ uint8 roundingCode;\r
+ int8 tininessCode;\r
+\r
+ functionName = functions[ functionCode ].name;\r
+ switch ( roundingMode ) {\r
+ case 0:\r
+ roundingModeName = 0;\r
+ roundingCode = float_round_nearest_even;\r
+ break;\r
+ case ROUND_NEAREST_EVEN:\r
+ roundingModeName = "nearest_even";\r
+ roundingCode = float_round_nearest_even;\r
+ break;\r
+ case ROUND_TO_ZERO:\r
+ roundingModeName = "to_zero";\r
+ roundingCode = float_round_to_zero;\r
+ break;\r
+ case ROUND_DOWN:\r
+ roundingModeName = "down";\r
+ roundingCode = float_round_down;\r
+ break;\r
+ case ROUND_UP:\r
+ roundingModeName = "up";\r
+ roundingCode = float_round_up;\r
+ break;\r
+ }\r
+ float_rounding_mode = roundingCode;\r
+ switch ( tininessMode ) {\r
+ case 0:\r
+ tininessModeName = 0;\r
+ tininessCode = float_tininess_after_rounding;\r
+ break;\r
+ case TININESS_BEFORE_ROUNDING:\r
+ tininessModeName = "before";\r
+ tininessCode = float_tininess_before_rounding;\r
+ break;\r
+ case TININESS_AFTER_ROUNDING:\r
+ tininessModeName = "after";\r
+ tininessCode = float_tininess_after_rounding;\r
+ break;\r
+ }\r
+ float_detect_tininess = tininessCode;\r
+ switch ( functionCode ) {\r
+ case INT32_TO_FLOAT32:\r
+ time_a_int32_z_float32( int32_to_float32 );\r
+ break;\r
+ case INT32_TO_FLOAT64:\r
+ time_a_int32_z_float64( int32_to_float64 );\r
+ break;\r
+ case FLOAT32_TO_INT32:\r
+ time_a_float32_z_int32( float32_to_int32 );\r
+ break;\r
+ case FLOAT32_TO_INT32_ROUND_TO_ZERO:\r
+ time_a_float32_z_int32( float32_to_int32_round_to_zero );\r
+ break;\r
+ case FLOAT32_TO_FLOAT64:\r
+ time_a_float32_z_float64( float32_to_float64 );\r
+ break;\r
+ case FLOAT32_ROUND_TO_INT:\r
+ time_az_float32( float32_round_to_int );\r
+ break;\r
+ case FLOAT32_ADD:\r
+ time_abz_float32( float32_add );\r
+ break;\r
+ case FLOAT32_SUB:\r
+ time_abz_float32( float32_sub );\r
+ break;\r
+ case FLOAT32_MUL:\r
+ time_abz_float32( float32_mul );\r
+ break;\r
+ case FLOAT32_DIV:\r
+ time_abz_float32( float32_div );\r
+ break;\r
+ case FLOAT32_REM:\r
+ time_abz_float32( float32_rem );\r
+ break;\r
+ case FLOAT32_SQRT:\r
+ time_az_float32_pos( float32_sqrt );\r
+ break;\r
+ case FLOAT32_EQ:\r
+ time_ab_float32_z_flag( float32_eq );\r
+ break;\r
+ case FLOAT32_LE:\r
+ time_ab_float32_z_flag( float32_le );\r
+ break;\r
+ case FLOAT32_LT:\r
+ time_ab_float32_z_flag( float32_lt );\r
+ break;\r
+ case FLOAT32_EQ_SIGNALING:\r
+ time_ab_float32_z_flag( float32_eq_signaling );\r
+ break;\r
+ case FLOAT32_LE_QUIET:\r
+ time_ab_float32_z_flag( float32_le_quiet );\r
+ break;\r
+ case FLOAT32_LT_QUIET:\r
+ time_ab_float32_z_flag( float32_lt_quiet );\r
+ break;\r
+ case FLOAT64_TO_INT32:\r
+ time_a_float64_z_int32( float64_to_int32 );\r
+ break;\r
+ case FLOAT64_TO_INT32_ROUND_TO_ZERO:\r
+ time_a_float64_z_int32( float64_to_int32_round_to_zero );\r
+ break;\r
+ case FLOAT64_TO_FLOAT32:\r
+ time_a_float64_z_float32( float64_to_float32 );\r
+ break;\r
+ case FLOAT64_ROUND_TO_INT:\r
+ time_az_float64( float64_round_to_int );\r
+ break;\r
+ case FLOAT64_ADD:\r
+ time_abz_float64( float64_add );\r
+ break;\r
+ case FLOAT64_SUB:\r
+ time_abz_float64( float64_sub );\r
+ break;\r
+ case FLOAT64_MUL:\r
+ time_abz_float64( float64_mul );\r
+ break;\r
+ case FLOAT64_DIV:\r
+ time_abz_float64( float64_div );\r
+ break;\r
+ case FLOAT64_REM:\r
+ time_abz_float64( float64_rem );\r
+ break;\r
+ case FLOAT64_SQRT:\r
+ time_az_float64_pos( float64_sqrt );\r
+ break;\r
+ case FLOAT64_EQ:\r
+ time_ab_float64_z_flag( float64_eq );\r
+ break;\r
+ case FLOAT64_LE:\r
+ time_ab_float64_z_flag( float64_le );\r
+ break;\r
+ case FLOAT64_LT:\r
+ time_ab_float64_z_flag( float64_lt );\r
+ break;\r
+ case FLOAT64_EQ_SIGNALING:\r
+ time_ab_float64_z_flag( float64_eq_signaling );\r
+ break;\r
+ case FLOAT64_LE_QUIET:\r
+ time_ab_float64_z_flag( float64_le_quiet );\r
+ break;\r
+ case FLOAT64_LT_QUIET:\r
+ time_ab_float64_z_flag( float64_lt_quiet );\r
+ break;\r
+ }\r
+\r
+}\r
+\r
+static void\r
+ timeFunction( uint8 functionCode, int8 roundingModeIn, int8 tininessModeIn )\r
+{\r
+ int8 roundingMode, tininessMode;\r
+\r
+ for ( roundingMode = 1;\r
+ roundingMode < NUM_ROUNDINGMODES;\r
+ ++roundingMode\r
+ ) {\r
+ if ( ! functions[ functionCode ].roundingMode ) {\r
+ roundingMode = 0;\r
+ }\r
+ else if ( roundingModeIn ) {\r
+ roundingMode = roundingModeIn;\r
+ }\r
+ for ( tininessMode = 1;\r
+ tininessMode < NUM_TININESSMODES;\r
+ ++tininessMode\r
+ ) {\r
+ if ( ! functions[ functionCode ].tininessMode ) {\r
+ tininessMode = 0;\r
+ }\r
+ else if ( tininessModeIn ) {\r
+ tininessMode = tininessModeIn;\r
+ }\r
+ timeFunctionVariety( functionCode, roundingMode, tininessMode );\r
+ if ( tininessModeIn || ! tininessMode ) break;\r
+ }\r
+ if ( roundingModeIn || ! roundingMode ) break;\r
+ }\r
+\r
+}\r
+\r
+main( int argc, char **argv )\r
+{\r
+ char *argPtr;\r
+ flag functionArgument;\r
+ uint8 functionCode;\r
+ int8 operands, roundingMode, tininessMode;\r
+\r
+ if ( argc <= 1 ) goto writeHelpMessage;\r
+ functionArgument = FALSE;\r
+ functionCode = 0;\r
+ operands = 0;\r
+ roundingMode = 0;\r
+ tininessMode = 0;\r
+ --argc;\r
+ ++argv;\r
+ while ( argc && ( argPtr = argv[ 0 ] ) ) {\r
+ if ( argPtr[ 0 ] == '-' ) ++argPtr;\r
+ if ( strcmp( argPtr, "help" ) == 0 ) {\r
+ writeHelpMessage:\r
+ fputs(\r
+"timesoftfloat [<option>...] <function>\n"\r
+" <option>: (* is default)\n"\r
+" -help --Write this message and exit.\n"\r
+" -nearesteven --Only time rounding to nearest/even.\n"\r
+" -tozero --Only time rounding to zero.\n"\r
+" -down --Only time rounding down.\n"\r
+" -up --Only time rounding up.\n"\r
+" -tininessbefore --Only time underflow tininess before rounding.\n"\r
+" -tininessafter --Only time underflow tininess after rounding.\n"\r
+" <function>:\n"\r
+" int32_to_<float> <float>_add <float>_eq\n"\r
+" <float>_to_int32 <float>_sub <float>_le\n"\r
+" <float>_to_int32_round_to_zero <float>_mul <float>_lt\n"\r
+" <float>_to_<float> <float>_div <float>_eq_signaling\n"\r
+" <float>_round_to_int <float>_rem <float>_le_quiet\n"\r
+" <float>_sqrt <float>_lt_quiet\n"\r
+" -all1 --All 1-operand functions.\n"\r
+" -all2 --All 2-operand functions.\n"\r
+" -all --All functions.\n"\r
+" <float>:\n"\r
+" float32 --Single precision.\n"\r
+" float64 --Double precision.\n",\r
+ stdout\r
+ );\r
+ return EXIT_SUCCESS;\r
+ }\r
+ else if ( ( strcmp( argPtr, "nearesteven" ) == 0 )\r
+ || ( strcmp( argPtr, "nearest_even" ) == 0 ) ) {\r
+ roundingMode = ROUND_NEAREST_EVEN;\r
+ }\r
+ else if ( ( strcmp( argPtr, "tozero" ) == 0 )\r
+ || ( strcmp( argPtr, "to_zero" ) == 0 ) ) {\r
+ roundingMode = ROUND_TO_ZERO;\r
+ }\r
+ else if ( strcmp( argPtr, "down" ) == 0 ) {\r
+ roundingMode = ROUND_DOWN;\r
+ }\r
+ else if ( strcmp( argPtr, "up" ) == 0 ) {\r
+ roundingMode = ROUND_UP;\r
+ }\r
+ else if ( strcmp( argPtr, "tininessbefore" ) == 0 ) {\r
+ tininessMode = TININESS_BEFORE_ROUNDING;\r
+ }\r
+ else if ( strcmp( argPtr, "tininessafter" ) == 0 ) {\r
+ tininessMode = TININESS_AFTER_ROUNDING;\r
+ }\r
+ else if ( strcmp( argPtr, "all1" ) == 0 ) {\r
+ functionArgument = TRUE;\r
+ functionCode = 0;\r
+ operands = 1;\r
+ }\r
+ else if ( strcmp( argPtr, "all2" ) == 0 ) {\r
+ functionArgument = TRUE;\r
+ functionCode = 0;\r
+ operands = 2;\r
+ }\r
+ else if ( strcmp( argPtr, "all" ) == 0 ) {\r
+ functionArgument = TRUE;\r
+ functionCode = 0;\r
+ operands = 0;\r
+ }\r
+ else {\r
+ for ( functionCode = 1;\r
+ functionCode < NUM_FUNCTIONS;\r
+ ++functionCode \r
+ ) {\r
+ if ( strcmp( argPtr, functions[ functionCode ].name ) == 0 ) {\r
+ break;\r
+ }\r
+ }\r
+ if ( functionCode == NUM_FUNCTIONS ) {\r
+ fail( "Invalid option or function `%s'", argv[ 0 ] );\r
+ }\r
+ functionArgument = TRUE;\r
+ }\r
+ --argc;\r
+ ++argv;\r
+ }\r
+ if ( ! functionArgument ) fail( "Function argument required" );\r
+ if ( functionCode ) {\r
+ timeFunction( functionCode, roundingMode, tininessMode );\r
+ }\r
+ else if ( operands == 1 ) {\r
+ for ( functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode\r
+ ) {\r
+ if ( functions[ functionCode ].numInputs == 1 ) {\r
+ timeFunction( functionCode, roundingMode, tininessMode );\r
+ }\r
+ }\r
+ }\r
+ else if ( operands == 2 ) {\r
+ for ( functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode\r
+ ) {\r
+ if ( functions[ functionCode ].numInputs == 2 ) {\r
+ timeFunction( functionCode, roundingMode, tininessMode );\r
+ }\r
+ }\r
+ }\r
+ else {\r
+ for ( functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode\r
+ ) {\r
+ timeFunction( functionCode, roundingMode, tininessMode );\r
+ }\r
+ }\r
+ return EXIT_SUCCESS;\r
+\r
+}\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Include common integer types and flags.\r
+*----------------------------------------------------------------------------*/\r
+#include "../../../processors/386-GCC.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Symbolic Boolean literals.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ FALSE = 0,\r
+ TRUE = 1\r
+};\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Underflow tininess-detection mode, statically initialized to default value.\r
+| (The declaration in `softfloat.h' must match the `int8' type here.)\r
+*----------------------------------------------------------------------------*/\r
+int8 float_detect_tininess = float_tininess_after_rounding;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Raises the exceptions specified by `flags'. Floating-point traps can be\r
+| defined here if desired. It is currently not possible for such a trap\r
+| to substitute a result value. If traps are not implemented, this routine\r
+| should be simply `float_exception_flags |= flags;'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+void float_raise( int8 flags )\r
+{\r
+\r
+ float_exception_flags |= flags;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Internal canonical NaN format.\r
+*----------------------------------------------------------------------------*/\r
+typedef struct {\r
+ flag sign;\r
+ bits64 high, low;\r
+} commonNaNT;\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define float32_default_nan 0xFFC00000\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_nan( float32 a )\r
+{\r
+\r
+ return ( 0xFF000000 < (bits32) ( a<<1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_signaling_nan( float32 a )\r
+{\r
+\r
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float32ToCommonNaN( float32 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a>>31;\r
+ z.low = 0;\r
+ z.high = ( (bits64) a )<<41;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the single-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 commonNaNToFloat32( commonNaNT a )\r
+{\r
+\r
+ return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 propagateFloat32NaN( float32 a, float32 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float32_is_nan( a );\r
+ aIsSignalingNaN = float32_is_signaling_nan( a );\r
+ bIsNaN = float32_is_nan( b );\r
+ bIsSignalingNaN = float32_is_signaling_nan( b );\r
+ a |= 0x00400000;\r
+ b |= 0x00400000;\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsSignalingNaN ) {\r
+ if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+ return bIsNaN ? b : a;\r
+ }\r
+ else if ( aIsNaN ) {\r
+ if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+ if ( (bits32) ( a<<1 ) < (bits32) ( b<<1 ) ) return b;\r
+ if ( (bits32) ( b<<1 ) < (bits32) ( a<<1 ) ) return a;\r
+ return ( a < b ) ? a : b;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define float64_default_nan LIT64( 0xFFF8000000000000 )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_nan( float64 a )\r
+{\r
+\r
+ return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_signaling_nan( float64 a )\r
+{\r
+\r
+ return\r
+ ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )\r
+ && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float64ToCommonNaN( float64 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a>>63;\r
+ z.low = 0;\r
+ z.high = a<<12;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the double-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 commonNaNToFloat64( commonNaNT a )\r
+{\r
+\r
+ return\r
+ ( ( (bits64) a.sign )<<63 )\r
+ | LIT64( 0x7FF8000000000000 )\r
+ | ( a.high>>12 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 propagateFloat64NaN( float64 a, float64 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float64_is_nan( a );\r
+ aIsSignalingNaN = float64_is_signaling_nan( a );\r
+ bIsNaN = float64_is_nan( b );\r
+ bIsSignalingNaN = float64_is_signaling_nan( b );\r
+ a |= LIT64( 0x0008000000000000 );\r
+ b |= LIT64( 0x0008000000000000 );\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsSignalingNaN ) {\r
+ if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+ return bIsNaN ? b : a;\r
+ }\r
+ else if ( aIsNaN ) {\r
+ if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+ if ( (bits64) ( a<<1 ) < (bits64) ( b<<1 ) ) return b;\r
+ if ( (bits64) ( b<<1 ) < (bits64) ( a<<1 ) ) return a;\r
+ return ( a < b ) ? a : b;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated extended double-precision NaN. The\r
+| `high' and `low' values hold the most- and least-significant bits,\r
+| respectively.\r
+*----------------------------------------------------------------------------*/\r
+#define floatx80_default_nan_high 0xFFFF\r
+#define floatx80_default_nan_low LIT64( 0xC000000000000000 )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is a\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_is_nan( floatx80 a )\r
+{\r
+\r
+ return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is a\r
+| signaling NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_is_signaling_nan( floatx80 a )\r
+{\r
+ bits64 aLow;\r
+\r
+ aLow = a.low & ~ LIT64( 0x4000000000000000 );\r
+ return\r
+ ( ( a.high & 0x7FFF ) == 0x7FFF )\r
+ && (bits64) ( aLow<<1 )\r
+ && ( a.low == aLow );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the\r
+| invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT floatx80ToCommonNaN( floatx80 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a.high>>15;\r
+ z.low = 0;\r
+ z.high = a.low<<1;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the extended\r
+| double-precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 commonNaNToFloatx80( commonNaNT a )\r
+{\r
+ floatx80 z;\r
+\r
+ z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );\r
+ z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two extended double-precision floating-point values `a' and `b', one\r
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or\r
+| `b' is a signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = floatx80_is_nan( a );\r
+ aIsSignalingNaN = floatx80_is_signaling_nan( a );\r
+ bIsNaN = floatx80_is_nan( b );\r
+ bIsSignalingNaN = floatx80_is_signaling_nan( b );\r
+ a.low |= LIT64( 0xC000000000000000 );\r
+ b.low |= LIT64( 0xC000000000000000 );\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsSignalingNaN ) {\r
+ if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+ return bIsNaN ? b : a;\r
+ }\r
+ else if ( aIsNaN ) {\r
+ if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+ if ( a.low < b.low ) return b;\r
+ if ( b.low < a.low ) return a;\r
+ return ( a.high < b.high ) ? a : b;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated quadruple-precision NaN. The `high' and\r
+| `low' values hold the most- and least-significant bits, respectively.\r
+*----------------------------------------------------------------------------*/\r
+#define float128_default_nan_high LIT64( 0xFFFF800000000000 )\r
+#define float128_default_nan_low LIT64( 0x0000000000000000 )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_is_nan( float128 a )\r
+{\r
+\r
+ return\r
+ ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )\r
+ && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is a\r
+| signaling NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_is_signaling_nan( float128 a )\r
+{\r
+\r
+ return\r
+ ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )\r
+ && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float128ToCommonNaN( float128 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a.high>>63;\r
+ shortShift128Left( a.high, a.low, 16, &z.high, &z.low );\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the quadruple-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 commonNaNToFloat128( commonNaNT a )\r
+{\r
+ float128 z;\r
+\r
+ shift128Right( a.high, a.low, 16, &z.high, &z.low );\r
+ z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two quadruple-precision floating-point values `a' and `b', one of\r
+| which is a NaN, and returns the appropriate NaN result. If either `a' or\r
+| `b' is a signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 propagateFloat128NaN( float128 a, float128 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float128_is_nan( a );\r
+ aIsSignalingNaN = float128_is_signaling_nan( a );\r
+ bIsNaN = float128_is_nan( b );\r
+ bIsSignalingNaN = float128_is_signaling_nan( b );\r
+ a.high |= LIT64( 0x0000800000000000 );\r
+ b.high |= LIT64( 0x0000800000000000 );\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsSignalingNaN ) {\r
+ if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+ return bIsNaN ? b : a;\r
+ }\r
+ else if ( aIsNaN ) {\r
+ if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+ if ( lt128( a.high<<1, a.low, b.high<<1, b.low ) ) return b;\r
+ if ( lt128( b.high<<1, b.low, a.high<<1, a.low ) ) return a;\r
+ return ( a.high < b.high ) ? a : b;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| The macro `FLOATX80' must be defined to enable the extended double-precision\r
+| floating-point format `floatx80'. If this macro is not defined, the\r
+| `floatx80' type will not be defined, and none of the functions that either\r
+| input or output the `floatx80' type will be defined. The same applies to\r
+| the `FLOAT128' macro and the quadruple-precision format `float128'.\r
+*----------------------------------------------------------------------------*/\r
+#define FLOATX80\r
+#define FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point types.\r
+*----------------------------------------------------------------------------*/\r
+typedef unsigned int float32;\r
+typedef unsigned long long float64;\r
+#ifdef FLOATX80\r
+typedef struct {\r
+ unsigned long long low;\r
+ unsigned short high;\r
+} floatx80;\r
+#endif\r
+#ifdef FLOAT128\r
+typedef struct {\r
+ unsigned long long low, high;\r
+} float128;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point underflow tininess-detection mode.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char float_detect_tininess;\r
+enum {\r
+ float_tininess_after_rounding = 0,\r
+ float_tininess_before_rounding = 1\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point rounding mode.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char float_rounding_mode;\r
+enum {\r
+ float_round_nearest_even = 0,\r
+ float_round_down = 1,\r
+ float_round_up = 2,\r
+ float_round_to_zero = 3\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point exception flags.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char float_exception_flags;\r
+enum {\r
+ float_flag_invalid = 1,\r
+ float_flag_divbyzero = 4,\r
+ float_flag_overflow = 8,\r
+ float_flag_underflow = 16,\r
+ float_flag_inexact = 32\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Routine to raise any or all of the software IEC/IEEE floating-point\r
+| exception flags.\r
+*----------------------------------------------------------------------------*/\r
+void float_raise( signed char );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE integer-to-floating-point conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+float32 int32_to_float32( int );\r
+float64 int32_to_float64( int );\r
+#ifdef FLOATX80\r
+floatx80 int32_to_floatx80( int );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 int32_to_float128( int );\r
+#endif\r
+float32 int64_to_float32( long long );\r
+float64 int64_to_float64( long long );\r
+#ifdef FLOATX80\r
+floatx80 int64_to_floatx80( long long );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 int64_to_float128( long long );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+int float32_to_int32( float32 );\r
+int float32_to_int32_round_to_zero( float32 );\r
+long long float32_to_int64( float32 );\r
+long long float32_to_int64_round_to_zero( float32 );\r
+float64 float32_to_float64( float32 );\r
+#ifdef FLOATX80\r
+floatx80 float32_to_floatx80( float32 );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 float32_to_float128( float32 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float32 float32_round_to_int( float32 );\r
+float32 float32_add( float32, float32 );\r
+float32 float32_sub( float32, float32 );\r
+float32 float32_mul( float32, float32 );\r
+float32 float32_div( float32, float32 );\r
+float32 float32_rem( float32, float32 );\r
+float32 float32_sqrt( float32 );\r
+char float32_eq( float32, float32 );\r
+char float32_le( float32, float32 );\r
+char float32_lt( float32, float32 );\r
+char float32_eq_signaling( float32, float32 );\r
+char float32_le_quiet( float32, float32 );\r
+char float32_lt_quiet( float32, float32 );\r
+char float32_is_signaling_nan( float32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+int float64_to_int32( float64 );\r
+int float64_to_int32_round_to_zero( float64 );\r
+long long float64_to_int64( float64 );\r
+long long float64_to_int64_round_to_zero( float64 );\r
+float32 float64_to_float32( float64 );\r
+#ifdef FLOATX80\r
+floatx80 float64_to_floatx80( float64 );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 float64_to_float128( float64 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float64 float64_round_to_int( float64 );\r
+float64 float64_add( float64, float64 );\r
+float64 float64_sub( float64, float64 );\r
+float64 float64_mul( float64, float64 );\r
+float64 float64_div( float64, float64 );\r
+float64 float64_rem( float64, float64 );\r
+float64 float64_sqrt( float64 );\r
+char float64_eq( float64, float64 );\r
+char float64_le( float64, float64 );\r
+char float64_lt( float64, float64 );\r
+char float64_eq_signaling( float64, float64 );\r
+char float64_le_quiet( float64, float64 );\r
+char float64_lt_quiet( float64, float64 );\r
+char float64_is_signaling_nan( float64 );\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE extended double-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+int floatx80_to_int32( floatx80 );\r
+int floatx80_to_int32_round_to_zero( floatx80 );\r
+long long floatx80_to_int64( floatx80 );\r
+long long floatx80_to_int64_round_to_zero( floatx80 );\r
+float32 floatx80_to_float32( floatx80 );\r
+float64 floatx80_to_float64( floatx80 );\r
+#ifdef FLOAT128\r
+float128 floatx80_to_float128( floatx80 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE extended double-precision rounding precision. Valid\r
+| values are 32, 64, and 80.\r
+*----------------------------------------------------------------------------*/\r
+extern signed char floatx80_rounding_precision;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE extended double-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+floatx80 floatx80_round_to_int( floatx80 );\r
+floatx80 floatx80_add( floatx80, floatx80 );\r
+floatx80 floatx80_sub( floatx80, floatx80 );\r
+floatx80 floatx80_mul( floatx80, floatx80 );\r
+floatx80 floatx80_div( floatx80, floatx80 );\r
+floatx80 floatx80_rem( floatx80, floatx80 );\r
+floatx80 floatx80_sqrt( floatx80 );\r
+char floatx80_eq( floatx80, floatx80 );\r
+char floatx80_le( floatx80, floatx80 );\r
+char floatx80_lt( floatx80, floatx80 );\r
+char floatx80_eq_signaling( floatx80, floatx80 );\r
+char floatx80_le_quiet( floatx80, floatx80 );\r
+char floatx80_lt_quiet( floatx80, floatx80 );\r
+char floatx80_is_signaling_nan( floatx80 );\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE quadruple-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+int float128_to_int32( float128 );\r
+int float128_to_int32_round_to_zero( float128 );\r
+long long float128_to_int64( float128 );\r
+long long float128_to_int64_round_to_zero( float128 );\r
+float32 float128_to_float32( float128 );\r
+float64 float128_to_float64( float128 );\r
+#ifdef FLOATX80\r
+floatx80 float128_to_floatx80( float128 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE quadruple-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float128 float128_round_to_int( float128 );\r
+float128 float128_add( float128, float128 );\r
+float128 float128_sub( float128, float128 );\r
+float128 float128_mul( float128, float128 );\r
+float128 float128_div( float128, float128 );\r
+float128 float128_rem( float128, float128 );\r
+float128 float128_sqrt( float128 );\r
+char float128_eq( float128, float128 );\r
+char float128_le( float128, float128 );\r
+char float128_lt( float128, float128 );\r
+char float128_eq_signaling( float128, float128 );\r
+char float128_le_quiet( float128, float128 );\r
+char float128_lt_quiet( float128, float128 );\r
+char float128_is_signaling_nan( float128 );\r
+\r
+#endif\r
+\r
--- /dev/null
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
+Package, Release 2b.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+| Include common integer types and flags.
+*----------------------------------------------------------------------------*/
+#include "../../../processors/SPARC-GCC.h"
+
+/*----------------------------------------------------------------------------
+| Symbolic Boolean literals.
+*----------------------------------------------------------------------------*/
+enum {
+ FALSE = 0,
+ TRUE = 1
+};
+
--- /dev/null
+
+/*============================================================================
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2b.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+| Underflow tininess-detection mode, statically initialized to default value.
+| (The declaration in `softfloat.h' must match the `int8' type here.)
+*----------------------------------------------------------------------------*/
+int8 float_detect_tininess = float_tininess_before_rounding;
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'. Floating-point traps can be
+| defined here if desired. It is currently not possible for such a trap
+| to substitute a result value. If traps are not implemented, this routine
+| should be simply `float_exception_flags |= flags;'.
+*----------------------------------------------------------------------------*/
+
+void float_raise( int8 flags )
+{
+
+ float_exception_flags |= flags;
+
+}
+
+/*----------------------------------------------------------------------------
+| Internal canonical NaN format.
+*----------------------------------------------------------------------------*/
+typedef struct {
+ flag sign;
+ bits64 high, low;
+} commonNaNT;
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated single-precision NaN.
+*----------------------------------------------------------------------------*/
+#define float32_default_nan 0x7FFFFFFF
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point value `a' is a NaN;
+| otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float32_is_nan( float32 a )
+{
+
+ return ( 0xFF000000 < (bits32) ( a<<1 ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the single-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float32_is_signaling_nan( float32 a )
+{
+
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the single-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float32ToCommonNaN( float32 a )
+{
+ commonNaNT z;
+
+ if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
+ z.sign = a>>31;
+ z.low = 0;
+ z.high = ( (bits64) a )<<41;
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the single-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float32 commonNaNToFloat32( commonNaNT a )
+{
+
+ return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
+
+}
+
+/*----------------------------------------------------------------------------
+| Takes two single-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float32 propagateFloat32NaN( float32 a, float32 b )
+{
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+
+ aIsNaN = float32_is_nan( a );
+ aIsSignalingNaN = float32_is_signaling_nan( a );
+ bIsNaN = float32_is_nan( b );
+ bIsSignalingNaN = float32_is_signaling_nan( b );
+ a |= 0x00400000;
+ b |= 0x00400000;
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
+ return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
+
+}
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated double-precision NaN.
+*----------------------------------------------------------------------------*/
+#define float64_default_nan LIT64( 0x7FFFFFFFFFFFFFFF )
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point value `a' is a NaN;
+| otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float64_is_nan( float64 a )
+{
+
+ return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the double-precision floating-point value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float64_is_signaling_nan( float64 a )
+{
+
+ return
+ ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
+ && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the double-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float64ToCommonNaN( float64 a )
+{
+ commonNaNT z;
+
+ if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
+ z.sign = a>>63;
+ z.low = 0;
+ z.high = a<<12;
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the double-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float64 commonNaNToFloat64( commonNaNT a )
+{
+
+ return
+ ( ( (bits64) a.sign )<<63 )
+ | LIT64( 0x7FF8000000000000 )
+ | ( a.high>>12 );
+
+}
+
+/*----------------------------------------------------------------------------
+| Takes two double-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float64 propagateFloat64NaN( float64 a, float64 b )
+{
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+
+ aIsNaN = float64_is_nan( a );
+ aIsSignalingNaN = float64_is_signaling_nan( a );
+ bIsNaN = float64_is_nan( b );
+ bIsSignalingNaN = float64_is_signaling_nan( b );
+ a |= LIT64( 0x0008000000000000 );
+ b |= LIT64( 0x0008000000000000 );
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
+ return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
+
+}
+
+#ifdef FLOATX80
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated extended double-precision NaN. The
+| `high' and `low' values hold the most- and least-significant bits,
+| respectively.
+*----------------------------------------------------------------------------*/
+#define floatx80_default_nan_high 0x7FFF
+#define floatx80_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the extended double-precision floating-point value `a' is a
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag floatx80_is_nan( floatx80 a )
+{
+
+ return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the extended double-precision floating-point value `a' is a
+| signaling NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag floatx80_is_signaling_nan( floatx80 a )
+{
+ bits64 aLow;
+
+ aLow = a.low & ~ LIT64( 0x4000000000000000 );
+ return
+ ( ( a.high & 0x7FFF ) == 0x7FFF )
+ && (bits64) ( aLow<<1 )
+ && ( a.low == aLow );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the extended double-precision floating-
+| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the
+| invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT floatx80ToCommonNaN( floatx80 a )
+{
+ commonNaNT z;
+
+ if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
+ z.sign = a.high>>15;
+ z.low = 0;
+ z.high = a.low<<1;
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the extended
+| double-precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static floatx80 commonNaNToFloatx80( commonNaNT a )
+{
+ floatx80 z;
+
+ z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
+ z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Takes two extended double-precision floating-point values `a' and `b', one
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
+| `b' is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )
+{
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+
+ aIsNaN = floatx80_is_nan( a );
+ aIsSignalingNaN = floatx80_is_signaling_nan( a );
+ bIsNaN = floatx80_is_nan( b );
+ bIsSignalingNaN = floatx80_is_signaling_nan( b );
+ a.low |= LIT64( 0xC000000000000000 );
+ b.low |= LIT64( 0xC000000000000000 );
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
+ return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
+
+}
+
+#endif
+
+#ifdef FLOAT128
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated quadruple-precision NaN. The `high' and
+| `low' values hold the most- and least-significant bits, respectively.
+*----------------------------------------------------------------------------*/
+#define float128_default_nan_high LIT64( 0x7FFFFFFFFFFFFFFF )
+#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;
+| otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float128_is_nan( float128 a )
+{
+
+ return
+ ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
+ && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the quadruple-precision floating-point value `a' is a
+| signaling NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+flag float128_is_signaling_nan( float128 a )
+{
+
+ return
+ ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
+ && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the quadruple-precision floating-point NaN
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid
+| exception is raised.
+*----------------------------------------------------------------------------*/
+
+static commonNaNT float128ToCommonNaN( float128 a )
+{
+ commonNaNT z;
+
+ if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
+ z.sign = a.high>>63;
+ shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the quadruple-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+static float128 commonNaNToFloat128( commonNaNT a )
+{
+ float128 z;
+
+ shift128Right( a.high, a.low, 16, &z.high, &z.low );
+ z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );
+ return z;
+
+}
+
+/*----------------------------------------------------------------------------
+| Takes two quadruple-precision floating-point values `a' and `b', one of
+| which is a NaN, and returns the appropriate NaN result. If either `a' or
+| `b' is a signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float128 propagateFloat128NaN( float128 a, float128 b )
+{
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
+
+ aIsNaN = float128_is_nan( a );
+ aIsSignalingNaN = float128_is_signaling_nan( a );
+ bIsNaN = float128_is_nan( b );
+ bIsSignalingNaN = float128_is_signaling_nan( b );
+ a.high |= LIT64( 0x0000800000000000 );
+ b.high |= LIT64( 0x0000800000000000 );
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
+ return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
+
+}
+
+#endif
+
--- /dev/null
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
+Package, Release 2b.
+
+Written by John R. Hauser. This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704. Funding was partially provided by the
+National Science Foundation under grant MIP-9311980. The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+| The macro `FLOATX80' must be defined to enable the extended double-precision
+| floating-point format `floatx80'. If this macro is not defined, the
+| `floatx80' type will not be defined, and none of the functions that either
+| input or output the `floatx80' type will be defined. The same applies to
+| the `FLOAT128' macro and the quadruple-precision format `float128'.
+*----------------------------------------------------------------------------*/
+#define FLOATX80
+#define FLOAT128
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point types.
+*----------------------------------------------------------------------------*/
+typedef unsigned int float32;
+typedef unsigned long long float64;
+#ifdef FLOATX80
+typedef struct {
+ unsigned short high;
+ unsigned long long low;
+} floatx80;
+#endif
+#ifdef FLOAT128
+typedef struct {
+ unsigned long long high, low;
+} float128;
+#endif
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point underflow tininess-detection mode.
+*----------------------------------------------------------------------------*/
+extern int float_detect_tininess;
+enum {
+ float_tininess_after_rounding = 0,
+ float_tininess_before_rounding = 1
+};
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point rounding mode.
+*----------------------------------------------------------------------------*/
+extern int float_rounding_mode;
+enum {
+ float_round_nearest_even = 0,
+ float_round_to_zero = 1,
+ float_round_up = 2,
+ float_round_down = 3
+};
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE floating-point exception flags.
+*----------------------------------------------------------------------------*/
+extern int float_exception_flags;
+enum {
+ float_flag_inexact = 1,
+ float_flag_divbyzero = 2,
+ float_flag_underflow = 4,
+ float_flag_overflow = 8,
+ float_flag_invalid = 16
+};
+
+/*----------------------------------------------------------------------------
+| Routine to raise any or all of the software IEC/IEEE floating-point
+| exception flags.
+*----------------------------------------------------------------------------*/
+void float_raise( int );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE integer-to-floating-point conversion routines.
+*----------------------------------------------------------------------------*/
+float32 int32_to_float32( int );
+float64 int32_to_float64( int );
+#ifdef FLOATX80
+floatx80 int32_to_floatx80( int );
+#endif
+#ifdef FLOAT128
+float128 int32_to_float128( int );
+#endif
+float32 int64_to_float32( long long );
+float64 int64_to_float64( long long );
+#ifdef FLOATX80
+floatx80 int64_to_floatx80( long long );
+#endif
+#ifdef FLOAT128
+float128 int64_to_float128( long long );
+#endif
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE single-precision conversion routines.
+*----------------------------------------------------------------------------*/
+int float32_to_int32( float32 );
+int float32_to_int32_round_to_zero( float32 );
+long long float32_to_int64( float32 );
+long long float32_to_int64_round_to_zero( float32 );
+float64 float32_to_float64( float32 );
+#ifdef FLOATX80
+floatx80 float32_to_floatx80( float32 );
+#endif
+#ifdef FLOAT128
+float128 float32_to_float128( float32 );
+#endif
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE single-precision operations.
+*----------------------------------------------------------------------------*/
+float32 float32_round_to_int( float32 );
+float32 float32_add( float32, float32 );
+float32 float32_sub( float32, float32 );
+float32 float32_mul( float32, float32 );
+float32 float32_div( float32, float32 );
+float32 float32_rem( float32, float32 );
+float32 float32_sqrt( float32 );
+int float32_eq( float32, float32 );
+int float32_le( float32, float32 );
+int float32_lt( float32, float32 );
+int float32_eq_signaling( float32, float32 );
+int float32_le_quiet( float32, float32 );
+int float32_lt_quiet( float32, float32 );
+int float32_is_signaling_nan( float32 );
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE double-precision conversion routines.
+*----------------------------------------------------------------------------*/
+int float64_to_int32( float64 );
+int float64_to_int32_round_to_zero( float64 );
+long long float64_to_int64( float64 );
+long long float64_to_int64_round_to_zero( float64 );
+float32 float64_to_float32( float64 );
+#ifdef FLOATX80
+floatx80 float64_to_floatx80( float64 );
+#endif
+#ifdef FLOAT128
+float128 float64_to_float128( float64 );
+#endif
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE double-precision operations.
+*----------------------------------------------------------------------------*/
+float64 float64_round_to_int( float64 );
+float64 float64_add( float64, float64 );
+float64 float64_sub( float64, float64 );
+float64 float64_mul( float64, float64 );
+float64 float64_div( float64, float64 );
+float64 float64_rem( float64, float64 );
+float64 float64_sqrt( float64 );
+int float64_eq( float64, float64 );
+int float64_le( float64, float64 );
+int float64_lt( float64, float64 );
+int float64_eq_signaling( float64, float64 );
+int float64_le_quiet( float64, float64 );
+int float64_lt_quiet( float64, float64 );
+int float64_is_signaling_nan( float64 );
+
+#ifdef FLOATX80
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE extended double-precision conversion routines.
+*----------------------------------------------------------------------------*/
+int floatx80_to_int32( floatx80 );
+int floatx80_to_int32_round_to_zero( floatx80 );
+long long floatx80_to_int64( floatx80 );
+long long floatx80_to_int64_round_to_zero( floatx80 );
+float32 floatx80_to_float32( floatx80 );
+float64 floatx80_to_float64( floatx80 );
+#ifdef FLOAT128
+float128 floatx80_to_float128( floatx80 );
+#endif
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE extended double-precision rounding precision. Valid
+| values are 32, 64, and 80.
+*----------------------------------------------------------------------------*/
+extern int floatx80_rounding_precision;
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE extended double-precision operations.
+*----------------------------------------------------------------------------*/
+floatx80 floatx80_round_to_int( floatx80 );
+floatx80 floatx80_add( floatx80, floatx80 );
+floatx80 floatx80_sub( floatx80, floatx80 );
+floatx80 floatx80_mul( floatx80, floatx80 );
+floatx80 floatx80_div( floatx80, floatx80 );
+floatx80 floatx80_rem( floatx80, floatx80 );
+floatx80 floatx80_sqrt( floatx80 );
+int floatx80_eq( floatx80, floatx80 );
+int floatx80_le( floatx80, floatx80 );
+int floatx80_lt( floatx80, floatx80 );
+int floatx80_eq_signaling( floatx80, floatx80 );
+int floatx80_le_quiet( floatx80, floatx80 );
+int floatx80_lt_quiet( floatx80, floatx80 );
+int floatx80_is_signaling_nan( floatx80 );
+
+#endif
+
+#ifdef FLOAT128
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE quadruple-precision conversion routines.
+*----------------------------------------------------------------------------*/
+int float128_to_int32( float128 );
+int float128_to_int32_round_to_zero( float128 );
+long long float128_to_int64( float128 );
+long long float128_to_int64_round_to_zero( float128 );
+float32 float128_to_float32( float128 );
+float64 float128_to_float64( float128 );
+#ifdef FLOATX80
+floatx80 float128_to_floatx80( float128 );
+#endif
+
+/*----------------------------------------------------------------------------
+| Software IEC/IEEE quadruple-precision operations.
+*----------------------------------------------------------------------------*/
+float128 float128_round_to_int( float128 );
+float128 float128_add( float128, float128 );
+float128 float128_sub( float128, float128 );
+float128 float128_mul( float128, float128 );
+float128 float128_div( float128, float128 );
+float128 float128_rem( float128, float128 );
+float128 float128_sqrt( float128 );
+int float128_eq( float128, float128 );
+int float128_le( float128, float128 );
+int float128_lt( float128, float128 );
+int float128_eq_signaling( float128, float128 );
+int float128_le_quiet( float128, float128 );
+int float128_lt_quiet( float128, float128 );
+int float128_is_signaling_nan( float128 );
+
+#endif
+
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal notice) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts `a' right by the number of bits given in `count'. If any nonzero\r
+| bits are shifted off, they are ``jammed'' into the least significant bit of\r
+| the result by setting the least significant bit to 1. The value of `count'\r
+| can be arbitrarily large; in particular, if `count' is greater than 32, the\r
+| result will be either 0 or 1, depending on whether `a' is zero or nonzero.\r
+| The result is stored in the location pointed to by `zPtr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )\r
+{\r
+ bits32 z;\r
+\r
+ if ( count == 0 ) {\r
+ z = a;\r
+ }\r
+ else if ( count < 32 ) {\r
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );\r
+ }\r
+ else {\r
+ z = ( a != 0 );\r
+ }\r
+ *zPtr = z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts `a' right by the number of bits given in `count'. If any nonzero\r
+| bits are shifted off, they are ``jammed'' into the least significant bit of\r
+| the result by setting the least significant bit to 1. The value of `count'\r
+| can be arbitrarily large; in particular, if `count' is greater than 64, the\r
+| result will be either 0 or 1, depending on whether `a' is zero or nonzero.\r
+| The result is stored in the location pointed to by `zPtr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )\r
+{\r
+ bits64 z;\r
+\r
+ if ( count == 0 ) {\r
+ z = a;\r
+ }\r
+ else if ( count < 64 ) {\r
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 );\r
+ }\r
+ else {\r
+ z = ( a != 0 );\r
+ }\r
+ *zPtr = z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64\r
+| _plus_ the number of bits given in `count'. The shifted result is at most\r
+| 64 nonzero bits; this is stored at the location pointed to by `z0Ptr'. The\r
+| bits shifted off form a second 64-bit result as follows: The _last_ bit\r
+| shifted off is the most-significant bit of the extra result, and the other\r
+| 63 bits of the extra result are all zero if and only if _all_but_the_last_\r
+| bits shifted off were all zero. This extra result is stored in the location\r
+| pointed to by `z1Ptr'. The value of `count' can be arbitrarily large.\r
+| (This routine makes more sense if `a0' and `a1' are considered to form\r
+| a fixed-point value with binary point between `a0' and `a1'. This fixed-\r
+| point value is shifted right by the number of bits given in `count', and\r
+| the integer part of the result is returned at the location pointed to by\r
+| `z0Ptr'. The fractional part of the result may be slightly corrupted as\r
+| described above, and is returned at the location pointed to by `z1Ptr'.)\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift64ExtraRightJamming(\r
+ bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+ bits64 z0, z1;\r
+ int8 negCount = ( - count ) & 63;\r
+\r
+ if ( count == 0 ) {\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else if ( count < 64 ) {\r
+ z1 = ( a0<<negCount ) | ( a1 != 0 );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ if ( count == 64 ) {\r
+ z1 = a0 | ( a1 != 0 );\r
+ }\r
+ else {\r
+ z1 = ( ( a0 | a1 ) != 0 );\r
+ }\r
+ z0 = 0;\r
+ }\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the\r
+| number of bits given in `count'. Any bits shifted off are lost. The value\r
+| of `count' can be arbitrarily large; in particular, if `count' is greater\r
+| than 128, the result will be 0. The result is broken into two 64-bit pieces\r
+| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift128Right(\r
+ bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+ bits64 z0, z1;\r
+ int8 negCount = ( - count ) & 63;\r
+\r
+ if ( count == 0 ) {\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else if ( count < 64 ) {\r
+ z1 = ( a0<<negCount ) | ( a1>>count );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0;\r
+ z0 = 0;\r
+ }\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the\r
+| number of bits given in `count'. If any nonzero bits are shifted off, they\r
+| are ``jammed'' into the least significant bit of the result by setting the\r
+| least significant bit to 1. The value of `count' can be arbitrarily large;\r
+| in particular, if `count' is greater than 128, the result will be either\r
+| 0 or 1, depending on whether the concatenation of `a0' and `a1' is zero or\r
+| nonzero. The result is broken into two 64-bit pieces which are stored at\r
+| the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift128RightJamming(\r
+ bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+ bits64 z0, z1;\r
+ int8 negCount = ( - count ) & 63;\r
+\r
+ if ( count == 0 ) {\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else if ( count < 64 ) {\r
+ z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ if ( count == 64 ) {\r
+ z1 = a0 | ( a1 != 0 );\r
+ }\r
+ else if ( count < 128 ) {\r
+ z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );\r
+ }\r
+ else {\r
+ z1 = ( ( a0 | a1 ) != 0 );\r
+ }\r
+ z0 = 0;\r
+ }\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right\r
+| by 64 _plus_ the number of bits given in `count'. The shifted result is\r
+| at most 128 nonzero bits; these are broken into two 64-bit pieces which are\r
+| stored at the locations pointed to by `z0Ptr' and `z1Ptr'. The bits shifted\r
+| off form a third 64-bit result as follows: The _last_ bit shifted off is\r
+| the most-significant bit of the extra result, and the other 63 bits of the\r
+| extra result are all zero if and only if _all_but_the_last_ bits shifted off\r
+| were all zero. This extra result is stored in the location pointed to by\r
+| `z2Ptr'. The value of `count' can be arbitrarily large.\r
+| (This routine makes more sense if `a0', `a1', and `a2' are considered\r
+| to form a fixed-point value with binary point between `a1' and `a2'. This\r
+| fixed-point value is shifted right by the number of bits given in `count',\r
+| and the integer part of the result is returned at the locations pointed to\r
+| by `z0Ptr' and `z1Ptr'. The fractional part of the result may be slightly\r
+| corrupted as described above, and is returned at the location pointed to by\r
+| `z2Ptr'.)\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shift128ExtraRightJamming(\r
+ bits64 a0,\r
+ bits64 a1,\r
+ bits64 a2,\r
+ int16 count,\r
+ bits64 *z0Ptr,\r
+ bits64 *z1Ptr,\r
+ bits64 *z2Ptr\r
+ )\r
+{\r
+ bits64 z0, z1, z2;\r
+ int8 negCount = ( - count ) & 63;\r
+\r
+ if ( count == 0 ) {\r
+ z2 = a2;\r
+ z1 = a1;\r
+ z0 = a0;\r
+ }\r
+ else {\r
+ if ( count < 64 ) {\r
+ z2 = a1<<negCount;\r
+ z1 = ( a0<<negCount ) | ( a1>>count );\r
+ z0 = a0>>count;\r
+ }\r
+ else {\r
+ if ( count == 64 ) {\r
+ z2 = a1;\r
+ z1 = a0;\r
+ }\r
+ else {\r
+ a2 |= a1;\r
+ if ( count < 128 ) {\r
+ z2 = a0<<negCount;\r
+ z1 = a0>>( count & 63 );\r
+ }\r
+ else {\r
+ z2 = ( count == 128 ) ? a0 : ( a0 != 0 );\r
+ z1 = 0;\r
+ }\r
+ }\r
+ z0 = 0;\r
+ }\r
+ z2 |= ( a2 != 0 );\r
+ }\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the\r
+| number of bits given in `count'. Any bits shifted off are lost. The value\r
+| of `count' must be less than 64. The result is broken into two 64-bit\r
+| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shortShift128Left(\r
+ bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+\r
+ *z1Ptr = a1<<count;\r
+ *z0Ptr =\r
+ ( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left\r
+| by the number of bits given in `count'. Any bits shifted off are lost.\r
+| The value of `count' must be less than 64. The result is broken into three\r
+| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',\r
+| `z1Ptr', and `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ shortShift192Left(\r
+ bits64 a0,\r
+ bits64 a1,\r
+ bits64 a2,\r
+ int16 count,\r
+ bits64 *z0Ptr,\r
+ bits64 *z1Ptr,\r
+ bits64 *z2Ptr\r
+ )\r
+{\r
+ bits64 z0, z1, z2;\r
+ int8 negCount;\r
+\r
+ z2 = a2<<count;\r
+ z1 = a1<<count;\r
+ z0 = a0<<count;\r
+ if ( 0 < count ) {\r
+ negCount = ( ( - count ) & 63 );\r
+ z1 |= a2>>negCount;\r
+ z0 |= a1>>negCount;\r
+ }\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit\r
+| value formed by concatenating `b0' and `b1'. Addition is modulo 2^128, so\r
+| any carry out is lost. The result is broken into two 64-bit pieces which\r
+| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ add128(\r
+ bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+ bits64 z1;\r
+\r
+ z1 = a1 + b1;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = a0 + b0 + ( z1 < a1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the\r
+| 192-bit value formed by concatenating `b0', `b1', and `b2'. Addition is\r
+| modulo 2^192, so any carry out is lost. The result is broken into three\r
+| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',\r
+| `z1Ptr', and `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ add192(\r
+ bits64 a0,\r
+ bits64 a1,\r
+ bits64 a2,\r
+ bits64 b0,\r
+ bits64 b1,\r
+ bits64 b2,\r
+ bits64 *z0Ptr,\r
+ bits64 *z1Ptr,\r
+ bits64 *z2Ptr\r
+ )\r
+{\r
+ bits64 z0, z1, z2;\r
+ int8 carry0, carry1;\r
+\r
+ z2 = a2 + b2;\r
+ carry1 = ( z2 < a2 );\r
+ z1 = a1 + b1;\r
+ carry0 = ( z1 < a1 );\r
+ z0 = a0 + b0;\r
+ z1 += carry1;\r
+ z0 += ( z1 < carry1 );\r
+ z0 += carry0;\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the\r
+| 128-bit value formed by concatenating `a0' and `a1'. Subtraction is modulo\r
+| 2^128, so any borrow out (carry out) is lost. The result is broken into two\r
+| 64-bit pieces which are stored at the locations pointed to by `z0Ptr' and\r
+| `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ sub128(\r
+ bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+\r
+ *z1Ptr = a1 - b1;\r
+ *z0Ptr = a0 - b0 - ( a1 < b1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'\r
+| from the 192-bit value formed by concatenating `a0', `a1', and `a2'.\r
+| Subtraction is modulo 2^192, so any borrow out (carry out) is lost. The\r
+| result is broken into three 64-bit pieces which are stored at the locations\r
+| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ sub192(\r
+ bits64 a0,\r
+ bits64 a1,\r
+ bits64 a2,\r
+ bits64 b0,\r
+ bits64 b1,\r
+ bits64 b2,\r
+ bits64 *z0Ptr,\r
+ bits64 *z1Ptr,\r
+ bits64 *z2Ptr\r
+ )\r
+{\r
+ bits64 z0, z1, z2;\r
+ int8 borrow0, borrow1;\r
+\r
+ z2 = a2 - b2;\r
+ borrow1 = ( a2 < b2 );\r
+ z1 = a1 - b1;\r
+ borrow0 = ( a1 < b1 );\r
+ z0 = a0 - b0;\r
+ z0 -= ( z1 < borrow1 );\r
+ z1 -= borrow1;\r
+ z0 -= borrow0;\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Multiplies `a' by `b' to obtain a 128-bit product. The product is broken\r
+| into two 64-bit pieces which are stored at the locations pointed to by\r
+| `z0Ptr' and `z1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )\r
+{\r
+ bits32 aHigh, aLow, bHigh, bLow;\r
+ bits64 z0, zMiddleA, zMiddleB, z1;\r
+\r
+ aLow = a;\r
+ aHigh = a>>32;\r
+ bLow = b;\r
+ bHigh = b>>32;\r
+ z1 = ( (bits64) aLow ) * bLow;\r
+ zMiddleA = ( (bits64) aLow ) * bHigh;\r
+ zMiddleB = ( (bits64) aHigh ) * bLow;\r
+ z0 = ( (bits64) aHigh ) * bHigh;\r
+ zMiddleA += zMiddleB;\r
+ z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );\r
+ zMiddleA <<= 32;\r
+ z1 += zMiddleA;\r
+ z0 += ( z1 < zMiddleA );\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Multiplies the 128-bit value formed by concatenating `a0' and `a1' by\r
+| `b' to obtain a 192-bit product. The product is broken into three 64-bit\r
+| pieces which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and\r
+| `z2Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ mul128By64To192(\r
+ bits64 a0,\r
+ bits64 a1,\r
+ bits64 b,\r
+ bits64 *z0Ptr,\r
+ bits64 *z1Ptr,\r
+ bits64 *z2Ptr\r
+ )\r
+{\r
+ bits64 z0, z1, z2, more1;\r
+\r
+ mul64To128( a1, b, &z1, &z2 );\r
+ mul64To128( a0, b, &z0, &more1 );\r
+ add128( z0, more1, 0, z1, &z0, &z1 );\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the\r
+| 128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit\r
+| product. The product is broken into four 64-bit pieces which are stored at\r
+| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE void\r
+ mul128To256(\r
+ bits64 a0,\r
+ bits64 a1,\r
+ bits64 b0,\r
+ bits64 b1,\r
+ bits64 *z0Ptr,\r
+ bits64 *z1Ptr,\r
+ bits64 *z2Ptr,\r
+ bits64 *z3Ptr\r
+ )\r
+{\r
+ bits64 z0, z1, z2, z3;\r
+ bits64 more1, more2;\r
+\r
+ mul64To128( a1, b1, &z2, &z3 );\r
+ mul64To128( a1, b0, &z1, &more2 );\r
+ add128( z1, more2, 0, z2, &z1, &z2 );\r
+ mul64To128( a0, b0, &z0, &more1 );\r
+ add128( z0, more1, 0, z1, &z0, &z1 );\r
+ mul64To128( a0, b1, &more1, &more2 );\r
+ add128( more1, more2, 0, z2, &more1, &z2 );\r
+ add128( z0, z1, 0, more1, &z0, &z1 );\r
+ *z3Ptr = z3;\r
+ *z2Ptr = z2;\r
+ *z1Ptr = z1;\r
+ *z0Ptr = z0;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns an approximation to the 64-bit integer quotient obtained by dividing\r
+| `b' into the 128-bit value formed by concatenating `a0' and `a1'. The\r
+| divisor `b' must be at least 2^63. If q is the exact quotient truncated\r
+| toward zero, the approximation returned lies between q and q + 2 inclusive.\r
+| If the exact quotient q is larger than 64 bits, the maximum positive 64-bit\r
+| unsigned integer is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )\r
+{\r
+ bits64 b0, b1;\r
+ bits64 rem0, rem1, term0, term1;\r
+ bits64 z;\r
+\r
+ if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );\r
+ b0 = b>>32;\r
+ z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;\r
+ mul64To128( b, z, &term0, &term1 );\r
+ sub128( a0, a1, term0, term1, &rem0, &rem1 );\r
+ while ( ( (sbits64) rem0 ) < 0 ) {\r
+ z -= LIT64( 0x100000000 );\r
+ b1 = b<<32;\r
+ add128( rem0, rem1, b0, b1, &rem0, &rem1 );\r
+ }\r
+ rem0 = ( rem0<<32 ) | ( rem1>>32 );\r
+ z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns an approximation to the square root of the 32-bit significand given\r
+| by `a'. Considered as an integer, `a' must be at least 2^31. If bit 0 of\r
+| `aExp' (the least significant bit) is 1, the integer returned approximates\r
+| 2^31*sqrt(`a'/2^31), where `a' is considered an integer. If bit 0 of `aExp'\r
+| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30). In either\r
+| case, the approximation returned lies strictly within +/-2 of the exact\r
+| value.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static bits32 estimateSqrt32( int16 aExp, bits32 a )\r
+{\r
+ static const bits16 sqrtOddAdjustments[] = {\r
+ 0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,\r
+ 0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67\r
+ };\r
+ static const bits16 sqrtEvenAdjustments[] = {\r
+ 0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,\r
+ 0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002\r
+ };\r
+ int8 index;\r
+ bits32 z;\r
+\r
+ index = ( a>>27 ) & 15;\r
+ if ( aExp & 1 ) {\r
+ z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];\r
+ z = ( ( a / z )<<14 ) + ( z<<15 );\r
+ a >>= 1;\r
+ }\r
+ else {\r
+ z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];\r
+ z = a / z + z;\r
+ z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );\r
+ if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );\r
+ }\r
+ return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the number of leading 0 bits before the most-significant 1 bit of\r
+| `a'. If `a' is zero, 32 is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static int8 countLeadingZeros32( bits32 a )\r
+{\r
+ static const int8 countLeadingZerosHigh[] = {\r
+ 8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,\r
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\r
+ };\r
+ int8 shiftCount;\r
+\r
+ shiftCount = 0;\r
+ if ( a < 0x10000 ) {\r
+ shiftCount += 16;\r
+ a <<= 16;\r
+ }\r
+ if ( a < 0x1000000 ) {\r
+ shiftCount += 8;\r
+ a <<= 8;\r
+ }\r
+ shiftCount += countLeadingZerosHigh[ a>>24 ];\r
+ return shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the number of leading 0 bits before the most-significant 1 bit of\r
+| `a'. If `a' is zero, 64 is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static int8 countLeadingZeros64( bits64 a )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = 0;\r
+ if ( a < ( (bits64) 1 )<<32 ) {\r
+ shiftCount += 32;\r
+ }\r
+ else {\r
+ a >>= 32;\r
+ }\r
+ shiftCount += countLeadingZeros32( a );\r
+ return shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'\r
+| is equal to the 128-bit value formed by concatenating `b0' and `b1'.\r
+| Otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
+{\r
+\r
+ return ( a0 == b0 ) && ( a1 == b1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less\r
+| than or equal to the 128-bit value formed by concatenating `b0' and `b1'.\r
+| Otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
+{\r
+\r
+ return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less\r
+| than the 128-bit value formed by concatenating `b0' and `b1'. Otherwise,\r
+| returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
+{\r
+\r
+ return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is\r
+| not equal to the 128-bit value formed by concatenating `b0' and `b1'.\r
+| Otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
+{\r
+\r
+ return ( a0 != b0 ) || ( a1 != b1 );\r
+\r
+}\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include "milieu.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Floating-point rounding mode, extended double-precision rounding precision,\r
+| and exception flags.\r
+*----------------------------------------------------------------------------*/\r
+int8 float_rounding_mode = float_round_nearest_even;\r
+int8 float_exception_flags = 0;\r
+#ifdef FLOATX80\r
+int8 floatx80_rounding_precision = 80;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Primitive arithmetic functions, including multi-word arithmetic, and\r
+| division and square root approximations. (Can be specialized to target if\r
+| desired.)\r
+*----------------------------------------------------------------------------*/\r
+#include "softfloat-macros"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Functions and definitions to determine: (1) whether tininess for underflow\r
+| is detected before or after rounding by default, (2) what (if anything)\r
+| happens when exceptions are raised, (3) how signaling NaNs are distinguished\r
+| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs\r
+| are propagated from function inputs to output. These details are target-\r
+| specific.\r
+*----------------------------------------------------------------------------*/\r
+#include "softfloat-specialize"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6\r
+| and 7, and returns the properly rounded 32-bit integer corresponding to the\r
+| input. If `zSign' is 1, the input is negated before being converted to an\r
+| integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point input\r
+| is simply rounded to an integer, with the inexact exception raised if the\r
+| input cannot be represented exactly as an integer. However, if the fixed-\r
+| point input is too large, the invalid exception is raised and the largest\r
+| positive or negative integer is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static int32 roundAndPackInt32( flag zSign, bits64 absZ )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven;\r
+ int8 roundIncrement, roundBits;\r
+ int32 z;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ roundIncrement = 0x40;\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ roundIncrement = 0;\r
+ }\r
+ else {\r
+ roundIncrement = 0x7F;\r
+ if ( zSign ) {\r
+ if ( roundingMode == float_round_up ) roundIncrement = 0;\r
+ }\r
+ else {\r
+ if ( roundingMode == float_round_down ) roundIncrement = 0;\r
+ }\r
+ }\r
+ }\r
+ roundBits = absZ & 0x7F;\r
+ absZ = ( absZ + roundIncrement )>>7;\r
+ absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );\r
+ z = absZ;\r
+ if ( zSign ) z = - z;\r
+ if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {\r
+ float_raise( float_flag_invalid );\r
+ return zSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
+ }\r
+ if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and\r
+| `absZ1', with binary point between bits 63 and 64 (between the input words),\r
+| and returns the properly rounded 64-bit integer corresponding to the input.\r
+| If `zSign' is 1, the input is negated before being converted to an integer.\r
+| Ordinarily, the fixed-point input is simply rounded to an integer, with\r
+| the inexact exception raised if the input cannot be represented exactly as\r
+| an integer. However, if the fixed-point input is too large, the invalid\r
+| exception is raised and the largest positive or negative integer is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static int64 roundAndPackInt64( flag zSign, bits64 absZ0, bits64 absZ1 )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven, increment;\r
+ int64 z;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ increment = ( (sbits64) absZ1 < 0 );\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ increment = 0;\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && absZ1;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && absZ1;\r
+ }\r
+ }\r
+ }\r
+ if ( increment ) {\r
+ ++absZ0;\r
+ if ( absZ0 == 0 ) goto overflow;\r
+ absZ0 &= ~ ( ( (bits64) ( absZ1<<1 ) == 0 ) & roundNearestEven );\r
+ }\r
+ z = absZ0;\r
+ if ( zSign ) z = - z;\r
+ if ( z && ( ( z < 0 ) ^ zSign ) ) {\r
+ overflow:\r
+ float_raise( float_flag_invalid );\r
+ return\r
+ zSign ? (sbits64) LIT64( 0x8000000000000000 )\r
+ : LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ if ( absZ1 ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the fraction bits of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits32 extractFloat32Frac( float32 a )\r
+{\r
+\r
+ return a & 0x007FFFFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE int16 extractFloat32Exp( float32 a )\r
+{\r
+\r
+ return ( a>>23 ) & 0xFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag extractFloat32Sign( float32 a )\r
+{\r
+\r
+ return a>>31;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal single-precision floating-point value represented\r
+| by the denormalized significand `aSig'. The normalized exponent and\r
+| significand are stored at the locations pointed to by `zExpPtr' and\r
+| `zSigPtr', respectively.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static void\r
+ normalizeFloat32Subnormal( bits32 aSig, int16 *zExpPtr, bits32 *zSigPtr )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros32( aSig ) - 8;\r
+ *zSigPtr = aSig<<shiftCount;\r
+ *zExpPtr = 1 - shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
+| single-precision floating-point value, returning the result. After being\r
+| shifted into the proper positions, the three fields are simply added\r
+| together to form the result. This means that any integer portion of `zSig'\r
+| will be added into the exponent. Since a properly normalized significand\r
+| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
+| than the desired result exponent whenever `zSig' is a complete, normalized\r
+| significand.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE float32 packFloat32( flag zSign, int16 zExp, bits32 zSig )\r
+{\r
+\r
+ return ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper single-precision floating-\r
+| point value corresponding to the abstract input. Ordinarily, the abstract\r
+| value is simply rounded and packed into the single-precision format, with\r
+| the inexact exception raised if the abstract input cannot be represented\r
+| exactly. However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned. If the abstract value is too small, the input value is rounded to\r
+| a subnormal number, and the underflow and inexact exceptions are raised if\r
+| the abstract input cannot be represented exactly as a subnormal single-\r
+| precision floating-point number.\r
+| The input significand `zSig' has its binary point between bits 30\r
+| and 29, which is 7 bits to the left of the usual location. This shifted\r
+| significand must be normalized or smaller. If `zSig' is not normalized,\r
+| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
+| and it must not require rounding. In the usual case that `zSig' is\r
+| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
+| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven;\r
+ int8 roundIncrement, roundBits;\r
+ flag isTiny;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ roundIncrement = 0x40;\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ roundIncrement = 0;\r
+ }\r
+ else {\r
+ roundIncrement = 0x7F;\r
+ if ( zSign ) {\r
+ if ( roundingMode == float_round_up ) roundIncrement = 0;\r
+ }\r
+ else {\r
+ if ( roundingMode == float_round_down ) roundIncrement = 0;\r
+ }\r
+ }\r
+ }\r
+ roundBits = zSig & 0x7F;\r
+ if ( 0xFD <= (bits16) zExp ) {\r
+ if ( ( 0xFD < zExp )\r
+ || ( ( zExp == 0xFD )\r
+ && ( (sbits32) ( zSig + roundIncrement ) < 0 ) )\r
+ ) {\r
+ float_raise( float_flag_overflow | float_flag_inexact );\r
+ return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );\r
+ }\r
+ if ( zExp < 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < -1 )\r
+ || ( zSig + roundIncrement < 0x80000000 );\r
+ shift32RightJamming( zSig, - zExp, &zSig );\r
+ zExp = 0;\r
+ roundBits = zSig & 0x7F;\r
+ if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
+ }\r
+ }\r
+ if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
+ zSig = ( zSig + roundIncrement )>>7;\r
+ zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );\r
+ if ( zSig == 0 ) zExp = 0;\r
+ return packFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper single-precision floating-\r
+| point value corresponding to the abstract input. This routine is just like\r
+| `roundAndPackFloat32' except that `zSig' does not have to be normalized.\r
+| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
+| floating-point exponent.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32\r
+ normalizeRoundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros32( zSig ) - 1;\r
+ return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the fraction bits of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits64 extractFloat64Frac( float64 a )\r
+{\r
+\r
+ return a & LIT64( 0x000FFFFFFFFFFFFF );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE int16 extractFloat64Exp( float64 a )\r
+{\r
+\r
+ return ( a>>52 ) & 0x7FF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag extractFloat64Sign( float64 a )\r
+{\r
+\r
+ return a>>63;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal double-precision floating-point value represented\r
+| by the denormalized significand `aSig'. The normalized exponent and\r
+| significand are stored at the locations pointed to by `zExpPtr' and\r
+| `zSigPtr', respectively.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static void\r
+ normalizeFloat64Subnormal( bits64 aSig, int16 *zExpPtr, bits64 *zSigPtr )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros64( aSig ) - 11;\r
+ *zSigPtr = aSig<<shiftCount;\r
+ *zExpPtr = 1 - shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
+| double-precision floating-point value, returning the result. After being\r
+| shifted into the proper positions, the three fields are simply added\r
+| together to form the result. This means that any integer portion of `zSig'\r
+| will be added into the exponent. Since a properly normalized significand\r
+| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
+| than the desired result exponent whenever `zSig' is a complete, normalized\r
+| significand.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE float64 packFloat64( flag zSign, int16 zExp, bits64 zSig )\r
+{\r
+\r
+ return ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<52 ) + zSig;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper double-precision floating-\r
+| point value corresponding to the abstract input. Ordinarily, the abstract\r
+| value is simply rounded and packed into the double-precision format, with\r
+| the inexact exception raised if the abstract input cannot be represented\r
+| exactly. However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned. If the abstract value is too small, the input value is rounded\r
+| to a subnormal number, and the underflow and inexact exceptions are raised\r
+| if the abstract input cannot be represented exactly as a subnormal double-\r
+| precision floating-point number.\r
+| The input significand `zSig' has its binary point between bits 62\r
+| and 61, which is 10 bits to the left of the usual location. This shifted\r
+| significand must be normalized or smaller. If `zSig' is not normalized,\r
+| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
+| and it must not require rounding. In the usual case that `zSig' is\r
+| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
+| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven;\r
+ int16 roundIncrement, roundBits;\r
+ flag isTiny;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ roundIncrement = 0x200;\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ roundIncrement = 0;\r
+ }\r
+ else {\r
+ roundIncrement = 0x3FF;\r
+ if ( zSign ) {\r
+ if ( roundingMode == float_round_up ) roundIncrement = 0;\r
+ }\r
+ else {\r
+ if ( roundingMode == float_round_down ) roundIncrement = 0;\r
+ }\r
+ }\r
+ }\r
+ roundBits = zSig & 0x3FF;\r
+ if ( 0x7FD <= (bits16) zExp ) {\r
+ if ( ( 0x7FD < zExp )\r
+ || ( ( zExp == 0x7FD )\r
+ && ( (sbits64) ( zSig + roundIncrement ) < 0 ) )\r
+ ) {\r
+ float_raise( float_flag_overflow | float_flag_inexact );\r
+ return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );\r
+ }\r
+ if ( zExp < 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < -1 )\r
+ || ( zSig + roundIncrement < LIT64( 0x8000000000000000 ) );\r
+ shift64RightJamming( zSig, - zExp, &zSig );\r
+ zExp = 0;\r
+ roundBits = zSig & 0x3FF;\r
+ if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
+ }\r
+ }\r
+ if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
+ zSig = ( zSig + roundIncrement )>>10;\r
+ zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven );\r
+ if ( zSig == 0 ) zExp = 0;\r
+ return packFloat64( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper double-precision floating-\r
+| point value corresponding to the abstract input. This routine is just like\r
+| `roundAndPackFloat64' except that `zSig' does not have to be normalized.\r
+| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
+| floating-point exponent.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64\r
+ normalizeRoundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros64( zSig ) - 1;\r
+ return roundAndPackFloat64( zSign, zExp - shiftCount, zSig<<shiftCount );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the fraction bits of the extended double-precision floating-point\r
+| value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits64 extractFloatx80Frac( floatx80 a )\r
+{\r
+\r
+ return a.low;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the extended double-precision floating-point\r
+| value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE int32 extractFloatx80Exp( floatx80 a )\r
+{\r
+\r
+ return a.high & 0x7FFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the extended double-precision floating-point value\r
+| `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag extractFloatx80Sign( floatx80 a )\r
+{\r
+\r
+ return a.high>>15;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal extended double-precision floating-point value\r
+| represented by the denormalized significand `aSig'. The normalized exponent\r
+| and significand are stored at the locations pointed to by `zExpPtr' and\r
+| `zSigPtr', respectively.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static void\r
+ normalizeFloatx80Subnormal( bits64 aSig, int32 *zExpPtr, bits64 *zSigPtr )\r
+{\r
+ int8 shiftCount;\r
+\r
+ shiftCount = countLeadingZeros64( aSig );\r
+ *zSigPtr = aSig<<shiftCount;\r
+ *zExpPtr = 1 - shiftCount;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', exponent `zExp', and significand `zSig' into an\r
+| extended double-precision floating-point value, returning the result.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE floatx80 packFloatx80( flag zSign, int32 zExp, bits64 zSig )\r
+{\r
+ floatx80 z;\r
+\r
+ z.low = zSig;\r
+ z.high = ( ( (bits16) zSign )<<15 ) + zExp;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and extended significand formed by the concatenation of `zSig0' and `zSig1',\r
+| and returns the proper extended double-precision floating-point value\r
+| corresponding to the abstract input. Ordinarily, the abstract value is\r
+| rounded and packed into the extended double-precision format, with the\r
+| inexact exception raised if the abstract input cannot be represented\r
+| exactly. However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned. If the abstract value is too small, the input value is rounded to\r
+| a subnormal number, and the underflow and inexact exceptions are raised if\r
+| the abstract input cannot be represented exactly as a subnormal extended\r
+| double-precision floating-point number.\r
+| If `roundingPrecision' is 32 or 64, the result is rounded to the same\r
+| number of bits as single or double precision, respectively. Otherwise, the\r
+| result is rounded to the full precision of the extended double-precision\r
+| format.\r
+| The input significand must be normalized or smaller. If the input\r
+| significand is not normalized, `zExp' must be 0; in that case, the result\r
+| returned is a subnormal number, and it must not require rounding. The\r
+| handling of underflow and overflow follows the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80\r
+ roundAndPackFloatx80(\r
+ int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1\r
+ )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven, increment, isTiny;\r
+ int64 roundIncrement, roundMask, roundBits;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ if ( roundingPrecision == 80 ) goto precision80;\r
+ if ( roundingPrecision == 64 ) {\r
+ roundIncrement = LIT64( 0x0000000000000400 );\r
+ roundMask = LIT64( 0x00000000000007FF );\r
+ }\r
+ else if ( roundingPrecision == 32 ) {\r
+ roundIncrement = LIT64( 0x0000008000000000 );\r
+ roundMask = LIT64( 0x000000FFFFFFFFFF );\r
+ }\r
+ else {\r
+ goto precision80;\r
+ }\r
+ zSig0 |= ( zSig1 != 0 );\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ roundIncrement = 0;\r
+ }\r
+ else {\r
+ roundIncrement = roundMask;\r
+ if ( zSign ) {\r
+ if ( roundingMode == float_round_up ) roundIncrement = 0;\r
+ }\r
+ else {\r
+ if ( roundingMode == float_round_down ) roundIncrement = 0;\r
+ }\r
+ }\r
+ }\r
+ roundBits = zSig0 & roundMask;\r
+ if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {\r
+ if ( ( 0x7FFE < zExp )\r
+ || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )\r
+ ) {\r
+ goto overflow;\r
+ }\r
+ if ( zExp <= 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < 0 )\r
+ || ( zSig0 <= zSig0 + roundIncrement );\r
+ shift64RightJamming( zSig0, 1 - zExp, &zSig0 );\r
+ zExp = 0;\r
+ roundBits = zSig0 & roundMask;\r
+ if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
+ if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
+ zSig0 += roundIncrement;\r
+ if ( (sbits64) zSig0 < 0 ) zExp = 1;\r
+ roundIncrement = roundMask + 1;\r
+ if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {\r
+ roundMask |= roundIncrement;\r
+ }\r
+ zSig0 &= ~ roundMask;\r
+ return packFloatx80( zSign, zExp, zSig0 );\r
+ }\r
+ }\r
+ if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
+ zSig0 += roundIncrement;\r
+ if ( zSig0 < roundIncrement ) {\r
+ ++zExp;\r
+ zSig0 = LIT64( 0x8000000000000000 );\r
+ }\r
+ roundIncrement = roundMask + 1;\r
+ if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {\r
+ roundMask |= roundIncrement;\r
+ }\r
+ zSig0 &= ~ roundMask;\r
+ if ( zSig0 == 0 ) zExp = 0;\r
+ return packFloatx80( zSign, zExp, zSig0 );\r
+ precision80:\r
+ increment = ( (sbits64) zSig1 < 0 );\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ increment = 0;\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && zSig1;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && zSig1;\r
+ }\r
+ }\r
+ }\r
+ if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {\r
+ if ( ( 0x7FFE < zExp )\r
+ || ( ( zExp == 0x7FFE )\r
+ && ( zSig0 == LIT64( 0xFFFFFFFFFFFFFFFF ) )\r
+ && increment\r
+ )\r
+ ) {\r
+ roundMask = 0;\r
+ overflow:\r
+ float_raise( float_flag_overflow | float_flag_inexact );\r
+ if ( ( roundingMode == float_round_to_zero )\r
+ || ( zSign && ( roundingMode == float_round_up ) )\r
+ || ( ! zSign && ( roundingMode == float_round_down ) )\r
+ ) {\r
+ return packFloatx80( zSign, 0x7FFE, ~ roundMask );\r
+ }\r
+ return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( zExp <= 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < 0 )\r
+ || ! increment\r
+ || ( zSig0 < LIT64( 0xFFFFFFFFFFFFFFFF ) );\r
+ shift64ExtraRightJamming( zSig0, zSig1, 1 - zExp, &zSig0, &zSig1 );\r
+ zExp = 0;\r
+ if ( isTiny && zSig1 ) float_raise( float_flag_underflow );\r
+ if ( zSig1 ) float_exception_flags |= float_flag_inexact;\r
+ if ( roundNearestEven ) {\r
+ increment = ( (sbits64) zSig1 < 0 );\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && zSig1;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && zSig1;\r
+ }\r
+ }\r
+ if ( increment ) {\r
+ ++zSig0;\r
+ zSig0 &=\r
+ ~ ( ( (bits64) ( zSig1<<1 ) == 0 ) & roundNearestEven );\r
+ if ( (sbits64) zSig0 < 0 ) zExp = 1;\r
+ }\r
+ return packFloatx80( zSign, zExp, zSig0 );\r
+ }\r
+ }\r
+ if ( zSig1 ) float_exception_flags |= float_flag_inexact;\r
+ if ( increment ) {\r
+ ++zSig0;\r
+ if ( zSig0 == 0 ) {\r
+ ++zExp;\r
+ zSig0 = LIT64( 0x8000000000000000 );\r
+ }\r
+ else {\r
+ zSig0 &= ~ ( ( (bits64) ( zSig1<<1 ) == 0 ) & roundNearestEven );\r
+ }\r
+ }\r
+ else {\r
+ if ( zSig0 == 0 ) zExp = 0;\r
+ }\r
+ return packFloatx80( zSign, zExp, zSig0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent\r
+| `zExp', and significand formed by the concatenation of `zSig0' and `zSig1',\r
+| and returns the proper extended double-precision floating-point value\r
+| corresponding to the abstract input. This routine is just like\r
+| `roundAndPackFloatx80' except that the input significand does not have to be\r
+| normalized.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80\r
+ normalizeRoundAndPackFloatx80(\r
+ int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1\r
+ )\r
+{\r
+ int8 shiftCount;\r
+\r
+ if ( zSig0 == 0 ) {\r
+ zSig0 = zSig1;\r
+ zSig1 = 0;\r
+ zExp -= 64;\r
+ }\r
+ shiftCount = countLeadingZeros64( zSig0 );\r
+ shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
+ zExp -= shiftCount;\r
+ return\r
+ roundAndPackFloatx80( roundingPrecision, zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the least-significant 64 fraction bits of the quadruple-precision\r
+| floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits64 extractFloat128Frac1( float128 a )\r
+{\r
+\r
+ return a.low;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the most-significant 48 fraction bits of the quadruple-precision\r
+| floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE bits64 extractFloat128Frac0( float128 a )\r
+{\r
+\r
+ return a.high & LIT64( 0x0000FFFFFFFFFFFF );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the quadruple-precision floating-point value\r
+| `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE int32 extractFloat128Exp( float128 a )\r
+{\r
+\r
+ return ( a.high>>48 ) & 0x7FFF;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the quadruple-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE flag extractFloat128Sign( float128 a )\r
+{\r
+\r
+ return a.high>>63;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal quadruple-precision floating-point value\r
+| represented by the denormalized significand formed by the concatenation of\r
+| `aSig0' and `aSig1'. The normalized exponent is stored at the location\r
+| pointed to by `zExpPtr'. The most significant 49 bits of the normalized\r
+| significand are stored at the location pointed to by `zSig0Ptr', and the\r
+| least significant 64 bits of the normalized significand are stored at the\r
+| location pointed to by `zSig1Ptr'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static void\r
+ normalizeFloat128Subnormal(\r
+ bits64 aSig0,\r
+ bits64 aSig1,\r
+ int32 *zExpPtr,\r
+ bits64 *zSig0Ptr,\r
+ bits64 *zSig1Ptr\r
+ )\r
+{\r
+ int8 shiftCount;\r
+\r
+ if ( aSig0 == 0 ) {\r
+ shiftCount = countLeadingZeros64( aSig1 ) - 15;\r
+ if ( shiftCount < 0 ) {\r
+ *zSig0Ptr = aSig1>>( - shiftCount );\r
+ *zSig1Ptr = aSig1<<( shiftCount & 63 );\r
+ }\r
+ else {\r
+ *zSig0Ptr = aSig1<<shiftCount;\r
+ *zSig1Ptr = 0;\r
+ }\r
+ *zExpPtr = - shiftCount - 63;\r
+ }\r
+ else {\r
+ shiftCount = countLeadingZeros64( aSig0 ) - 15;\r
+ shortShift128Left( aSig0, aSig1, shiftCount, zSig0Ptr, zSig1Ptr );\r
+ *zExpPtr = 1 - shiftCount;\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', the exponent `zExp', and the significand formed\r
+| by the concatenation of `zSig0' and `zSig1' into a quadruple-precision\r
+| floating-point value, returning the result. After being shifted into the\r
+| proper positions, the three fields `zSign', `zExp', and `zSig0' are simply\r
+| added together to form the most significant 32 bits of the result. This\r
+| means that any integer portion of `zSig0' will be added into the exponent.\r
+| Since a properly normalized significand will have an integer portion equal\r
+| to 1, the `zExp' input should be 1 less than the desired result exponent\r
+| whenever `zSig0' and `zSig1' concatenated form a complete, normalized\r
+| significand.\r
+*----------------------------------------------------------------------------*/\r
+\r
+INLINE float128\r
+ packFloat128( flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )\r
+{\r
+ float128 z;\r
+\r
+ z.low = zSig1;\r
+ z.high = ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<48 ) + zSig0;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and extended significand formed by the concatenation of `zSig0', `zSig1',\r
+| and `zSig2', and returns the proper quadruple-precision floating-point value\r
+| corresponding to the abstract input. Ordinarily, the abstract value is\r
+| simply rounded and packed into the quadruple-precision format, with the\r
+| inexact exception raised if the abstract input cannot be represented\r
+| exactly. However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned. If the abstract value is too small, the input value is rounded to\r
+| a subnormal number, and the underflow and inexact exceptions are raised if\r
+| the abstract input cannot be represented exactly as a subnormal quadruple-\r
+| precision floating-point number.\r
+| The input significand must be normalized or smaller. If the input\r
+| significand is not normalized, `zExp' must be 0; in that case, the result\r
+| returned is a subnormal number, and it must not require rounding. In the\r
+| usual case that the input significand is normalized, `zExp' must be 1 less\r
+| than the ``true'' floating-point exponent. The handling of underflow and\r
+| overflow follows the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128\r
+ roundAndPackFloat128(\r
+ flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1, bits64 zSig2 )\r
+{\r
+ int8 roundingMode;\r
+ flag roundNearestEven, increment, isTiny;\r
+\r
+ roundingMode = float_rounding_mode;\r
+ roundNearestEven = ( roundingMode == float_round_nearest_even );\r
+ increment = ( (sbits64) zSig2 < 0 );\r
+ if ( ! roundNearestEven ) {\r
+ if ( roundingMode == float_round_to_zero ) {\r
+ increment = 0;\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && zSig2;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && zSig2;\r
+ }\r
+ }\r
+ }\r
+ if ( 0x7FFD <= (bits32) zExp ) {\r
+ if ( ( 0x7FFD < zExp )\r
+ || ( ( zExp == 0x7FFD )\r
+ && eq128(\r
+ LIT64( 0x0001FFFFFFFFFFFF ),\r
+ LIT64( 0xFFFFFFFFFFFFFFFF ),\r
+ zSig0,\r
+ zSig1\r
+ )\r
+ && increment\r
+ )\r
+ ) {\r
+ float_raise( float_flag_overflow | float_flag_inexact );\r
+ if ( ( roundingMode == float_round_to_zero )\r
+ || ( zSign && ( roundingMode == float_round_up ) )\r
+ || ( ! zSign && ( roundingMode == float_round_down ) )\r
+ ) {\r
+ return\r
+ packFloat128(\r
+ zSign,\r
+ 0x7FFE,\r
+ LIT64( 0x0000FFFFFFFFFFFF ),\r
+ LIT64( 0xFFFFFFFFFFFFFFFF )\r
+ );\r
+ }\r
+ return packFloat128( zSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( zExp < 0 ) {\r
+ isTiny =\r
+ ( float_detect_tininess == float_tininess_before_rounding )\r
+ || ( zExp < -1 )\r
+ || ! increment\r
+ || lt128(\r
+ zSig0,\r
+ zSig1,\r
+ LIT64( 0x0001FFFFFFFFFFFF ),\r
+ LIT64( 0xFFFFFFFFFFFFFFFF )\r
+ );\r
+ shift128ExtraRightJamming(\r
+ zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 );\r
+ zExp = 0;\r
+ if ( isTiny && zSig2 ) float_raise( float_flag_underflow );\r
+ if ( roundNearestEven ) {\r
+ increment = ( (sbits64) zSig2 < 0 );\r
+ }\r
+ else {\r
+ if ( zSign ) {\r
+ increment = ( roundingMode == float_round_down ) && zSig2;\r
+ }\r
+ else {\r
+ increment = ( roundingMode == float_round_up ) && zSig2;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ if ( zSig2 ) float_exception_flags |= float_flag_inexact;\r
+ if ( increment ) {\r
+ add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 );\r
+ zSig1 &= ~ ( ( zSig2 + zSig2 == 0 ) & roundNearestEven );\r
+ }\r
+ else {\r
+ if ( ( zSig0 | zSig1 ) == 0 ) zExp = 0;\r
+ }\r
+ return packFloat128( zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand formed by the concatenation of `zSig0' and `zSig1', and\r
+| returns the proper quadruple-precision floating-point value corresponding\r
+| to the abstract input. This routine is just like `roundAndPackFloat128'\r
+| except that the input significand has fewer bits and does not have to be\r
+| normalized. In all cases, `zExp' must be 1 less than the ``true'' floating-\r
+| point exponent.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128\r
+ normalizeRoundAndPackFloat128(\r
+ flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )\r
+{\r
+ int8 shiftCount;\r
+ bits64 zSig2;\r
+\r
+ if ( zSig0 == 0 ) {\r
+ zSig0 = zSig1;\r
+ zSig1 = 0;\r
+ zExp -= 64;\r
+ }\r
+ shiftCount = countLeadingZeros64( zSig0 ) - 15;\r
+ if ( 0 <= shiftCount ) {\r
+ zSig2 = 0;\r
+ shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
+ }\r
+ else {\r
+ shift128ExtraRightJamming(\r
+ zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 );\r
+ }\r
+ zExp -= shiftCount;\r
+ return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 32-bit two's complement integer `a'\r
+| to the single-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 int32_to_float32( int32 a )\r
+{\r
+ flag zSign;\r
+\r
+ if ( a == 0 ) return 0;\r
+ if ( a == (sbits32) 0x80000000 ) return packFloat32( 1, 0x9E, 0 );\r
+ zSign = ( a < 0 );\r
+ return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 32-bit two's complement integer `a'\r
+| to the double-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 int32_to_float64( int32 a )\r
+{\r
+ flag zSign;\r
+ uint32 absA;\r
+ int8 shiftCount;\r
+ bits64 zSig;\r
+\r
+ if ( a == 0 ) return 0;\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros32( absA ) + 21;\r
+ zSig = absA;\r
+ return packFloat64( zSign, 0x432 - shiftCount, zSig<<shiftCount );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 32-bit two's complement integer `a'\r
+| to the extended double-precision floating-point format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 int32_to_floatx80( int32 a )\r
+{\r
+ flag zSign;\r
+ uint32 absA;\r
+ int8 shiftCount;\r
+ bits64 zSig;\r
+\r
+ if ( a == 0 ) return packFloatx80( 0, 0, 0 );\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros32( absA ) + 32;\r
+ zSig = absA;\r
+ return packFloatx80( zSign, 0x403E - shiftCount, zSig<<shiftCount );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 32-bit two's complement integer `a' to\r
+| the quadruple-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 int32_to_float128( int32 a )\r
+{\r
+ flag zSign;\r
+ uint32 absA;\r
+ int8 shiftCount;\r
+ bits64 zSig0;\r
+\r
+ if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros32( absA ) + 17;\r
+ zSig0 = absA;\r
+ return packFloat128( zSign, 0x402E - shiftCount, zSig0<<shiftCount, 0 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 64-bit two's complement integer `a'\r
+| to the single-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 int64_to_float32( int64 a )\r
+{\r
+ flag zSign;\r
+ uint64 absA;\r
+ int8 shiftCount;\r
+ bits32 zSig;\r
+\r
+ if ( a == 0 ) return 0;\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros64( absA ) - 40;\r
+ if ( 0 <= shiftCount ) {\r
+ return packFloat32( zSign, 0x95 - shiftCount, absA<<shiftCount );\r
+ }\r
+ else {\r
+ shiftCount += 7;\r
+ if ( shiftCount < 0 ) {\r
+ shift64RightJamming( absA, - shiftCount, &absA );\r
+ }\r
+ else {\r
+ absA <<= shiftCount;\r
+ }\r
+ return roundAndPackFloat32( zSign, 0x9C - shiftCount, absA );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 64-bit two's complement integer `a'\r
+| to the double-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 int64_to_float64( int64 a )\r
+{\r
+ flag zSign;\r
+\r
+ if ( a == 0 ) return 0;\r
+ if ( a == (sbits64) LIT64( 0x8000000000000000 ) ) {\r
+ return packFloat64( 1, 0x43E, 0 );\r
+ }\r
+ zSign = ( a < 0 );\r
+ return normalizeRoundAndPackFloat64( zSign, 0x43C, zSign ? - a : a );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 64-bit two's complement integer `a'\r
+| to the extended double-precision floating-point format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 int64_to_floatx80( int64 a )\r
+{\r
+ flag zSign;\r
+ uint64 absA;\r
+ int8 shiftCount;\r
+\r
+ if ( a == 0 ) return packFloatx80( 0, 0, 0 );\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros64( absA );\r
+ return packFloatx80( zSign, 0x403E - shiftCount, absA<<shiftCount );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the 64-bit two's complement integer `a' to\r
+| the quadruple-precision floating-point format. The conversion is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 int64_to_float128( int64 a )\r
+{\r
+ flag zSign;\r
+ uint64 absA;\r
+ int8 shiftCount;\r
+ int32 zExp;\r
+ bits64 zSig0, zSig1;\r
+\r
+ if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );\r
+ zSign = ( a < 0 );\r
+ absA = zSign ? - a : a;\r
+ shiftCount = countLeadingZeros64( absA ) + 49;\r
+ zExp = 0x406E - shiftCount;\r
+ if ( 64 <= shiftCount ) {\r
+ zSig1 = 0;\r
+ zSig0 = absA;\r
+ shiftCount -= 64;\r
+ }\r
+ else {\r
+ zSig1 = absA;\r
+ zSig0 = 0;\r
+ }\r
+ shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
+ return packFloat128( zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float32_to_int32( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig;\r
+ bits64 aSig64;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( ( aExp == 0xFF ) && aSig ) aSign = 0;\r
+ if ( aExp ) aSig |= 0x00800000;\r
+ shiftCount = 0xAF - aExp;\r
+ aSig64 = aSig;\r
+ aSig64 <<= 32;\r
+ if ( 0 < shiftCount ) shift64RightJamming( aSig64, shiftCount, &aSig64 );\r
+ return roundAndPackInt32( aSign, aSig64 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero.\r
+| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\r
+| the conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float32_to_int32_round_to_zero( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig;\r
+ int32 z;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ shiftCount = aExp - 0x9E;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( a != 0xCF000000 ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF;\r
+ }\r
+ return (sbits32) 0x80000000;\r
+ }\r
+ else if ( aExp <= 0x7E ) {\r
+ if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ aSig = ( aSig | 0x00800000 )<<8;\r
+ z = aSig>>( - shiftCount );\r
+ if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ if ( aSign ) z = - z;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the 64-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 float32_to_int64( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig;\r
+ bits64 aSig64, aSigExtra;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ shiftCount = 0xBE - aExp;\r
+ if ( shiftCount < 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ if ( aExp ) aSig |= 0x00800000;\r
+ aSig64 = aSig;\r
+ aSig64 <<= 40;\r
+ shift64ExtraRightJamming( aSig64, 0, shiftCount, &aSig64, &aSigExtra );\r
+ return roundAndPackInt64( aSign, aSig64, aSigExtra );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the 64-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero. If\r
+| `a' is a NaN, the largest positive integer is returned. Otherwise, if the\r
+| conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 float32_to_int64_round_to_zero( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits32 aSig;\r
+ bits64 aSig64;\r
+ int64 z;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ shiftCount = aExp - 0xBE;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( a != 0xDF000000 ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ else if ( aExp <= 0x7E ) {\r
+ if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ aSig64 = aSig | 0x00800000;\r
+ aSig64 <<= 40;\r
+ z = aSig64>>( - shiftCount );\r
+ if ( (bits64) ( aSig64<<( shiftCount & 63 ) ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ if ( aSign ) z = - z;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the double-precision floating-point format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float32_to_float64( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 aSig;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return commonNaNToFloat64( float32ToCommonNaN( a ) );\r
+ return packFloat64( aSign, 0x7FF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat64( aSign, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ --aExp;\r
+ }\r
+ return packFloat64( aSign, aExp + 0x380, ( (bits64) aSig )<<29 );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the extended double-precision floating-point format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 float32_to_floatx80( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 aSig;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return commonNaNToFloatx80( float32ToCommonNaN( a ) );\r
+ return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ aSig |= 0x00800000;\r
+ return packFloatx80( aSign, aExp + 0x3F80, ( (bits64) aSig )<<40 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point value\r
+| `a' to the double-precision floating-point format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float32_to_float128( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 aSig;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return commonNaNToFloat128( float32ToCommonNaN( a ) );\r
+ return packFloat128( aSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ --aExp;\r
+ }\r
+ return packFloat128( aSign, aExp + 0x3F80, ( (bits64) aSig )<<25, 0 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Rounds the single-precision floating-point value `a' to an integer, and\r
+| returns the result as a single-precision floating-point value. The\r
+| operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_round_to_int( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits32 lastBitMask, roundBitsMask;\r
+ int8 roundingMode;\r
+ float32 z;\r
+\r
+ aExp = extractFloat32Exp( a );\r
+ if ( 0x96 <= aExp ) {\r
+ if ( ( aExp == 0xFF ) && extractFloat32Frac( a ) ) {\r
+ return propagateFloat32NaN( a, a );\r
+ }\r
+ return a;\r
+ }\r
+ if ( aExp <= 0x7E ) {\r
+ if ( (bits32) ( a<<1 ) == 0 ) return a;\r
+ float_exception_flags |= float_flag_inexact;\r
+ aSign = extractFloat32Sign( a );\r
+ switch ( float_rounding_mode ) {\r
+ case float_round_nearest_even:\r
+ if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) {\r
+ return packFloat32( aSign, 0x7F, 0 );\r
+ }\r
+ break;\r
+ case float_round_down:\r
+ return aSign ? 0xBF800000 : 0;\r
+ case float_round_up:\r
+ return aSign ? 0x80000000 : 0x3F800000;\r
+ }\r
+ return packFloat32( aSign, 0, 0 );\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask <<= 0x96 - aExp;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z = a;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ z += lastBitMask>>1;\r
+ if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
+ z += roundBitsMask;\r
+ }\r
+ }\r
+ z &= ~ roundBitsMask;\r
+ if ( z != a ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the single-precision\r
+| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated\r
+| before being returned. `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig;\r
+ int16 expDiff;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ expDiff = aExp - bExp;\r
+ aSig <<= 6;\r
+ bSig <<= 6;\r
+ if ( 0 < expDiff ) {\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig |= 0x20000000;\r
+ }\r
+ shift32RightJamming( bSig, expDiff, &bSig );\r
+ zExp = aExp;\r
+ }\r
+ else if ( expDiff < 0 ) {\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig |= 0x20000000;\r
+ }\r
+ shift32RightJamming( aSig, - expDiff, &aSig );\r
+ zExp = bExp;\r
+ }\r
+ else {\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig | bSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( aExp == 0 ) return packFloat32( zSign, 0, ( aSig + bSig )>>6 );\r
+ zSig = 0x40000000 + aSig + bSig;\r
+ zExp = aExp;\r
+ goto roundAndPack;\r
+ }\r
+ aSig |= 0x20000000;\r
+ zSig = ( aSig + bSig )<<1;\r
+ --zExp;\r
+ if ( (sbits32) zSig < 0 ) {\r
+ zSig = aSig + bSig;\r
+ ++zExp;\r
+ }\r
+ roundAndPack:\r
+ return roundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the single-\r
+| precision floating-point values `a' and `b'. If `zSign' is 1, the\r
+| difference is negated before being returned. `zSign' is ignored if the\r
+| result is a NaN. The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig;\r
+ int16 expDiff;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ expDiff = aExp - bExp;\r
+ aSig <<= 7;\r
+ bSig <<= 7;\r
+ if ( 0 < expDiff ) goto aExpBigger;\r
+ if ( expDiff < 0 ) goto bExpBigger;\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig | bSig ) return propagateFloat32NaN( a, b );\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ aExp = 1;\r
+ bExp = 1;\r
+ }\r
+ if ( bSig < aSig ) goto aBigger;\r
+ if ( aSig < bSig ) goto bBigger;\r
+ return packFloat32( float_rounding_mode == float_round_down, 0, 0 );\r
+ bExpBigger:\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return packFloat32( zSign ^ 1, 0xFF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig |= 0x40000000;\r
+ }\r
+ shift32RightJamming( aSig, - expDiff, &aSig );\r
+ bSig |= 0x40000000;\r
+ bBigger:\r
+ zSig = bSig - aSig;\r
+ zExp = bExp;\r
+ zSign ^= 1;\r
+ goto normalizeRoundAndPack;\r
+ aExpBigger:\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig |= 0x40000000;\r
+ }\r
+ shift32RightJamming( bSig, expDiff, &bSig );\r
+ aSig |= 0x40000000;\r
+ aBigger:\r
+ zSig = aSig - bSig;\r
+ zExp = aExp;\r
+ normalizeRoundAndPack:\r
+ --zExp;\r
+ return normalizeRoundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the single-precision floating-point values `a'\r
+| and `b'. The operation is performed according to the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_add( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return addFloat32Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return subFloat32Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the single-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_sub( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return subFloat32Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return addFloat32Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of multiplying the single-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_mul( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig;\r
+ bits64 zSig64;\r
+ bits32 zSig;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ bSign = extractFloat32Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {\r
+ return propagateFloat32NaN( a, b );\r
+ }\r
+ if ( ( bExp | bSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );\r
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ zExp = aExp + bExp - 0x7F;\r
+ aSig = ( aSig | 0x00800000 )<<7;\r
+ bSig = ( bSig | 0x00800000 )<<8;\r
+ shift64RightJamming( ( (bits64) aSig ) * bSig, 32, &zSig64 );\r
+ zSig = zSig64;\r
+ if ( 0 <= (sbits32) ( zSig<<1 ) ) {\r
+ zSig <<= 1;\r
+ --zExp;\r
+ }\r
+ return roundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of dividing the single-precision floating-point value `a'\r
+| by the corresponding value `b'. The operation is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_div( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits32 aSig, bSig, zSig;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ bSign = extractFloat32Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, b );\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return packFloat32( zSign, 0, 0 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ float_raise( float_flag_divbyzero );\r
+ return packFloat32( zSign, 0xFF, 0 );\r
+ }\r
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = aExp - bExp + 0x7D;\r
+ aSig = ( aSig | 0x00800000 )<<7;\r
+ bSig = ( bSig | 0x00800000 )<<8;\r
+ if ( bSig <= ( aSig + aSig ) ) {\r
+ aSig >>= 1;\r
+ ++zExp;\r
+ }\r
+ zSig = ( ( (bits64) aSig )<<32 ) / bSig;\r
+ if ( ( zSig & 0x3F ) == 0 ) {\r
+ zSig |= ( (bits64) bSig * zSig != ( (bits64) aSig )<<32 );\r
+ }\r
+ return roundAndPackFloat32( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the remainder of the single-precision floating-point value `a'\r
+| with respect to the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_rem( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, expDiff;\r
+ bits32 aSig, bSig;\r
+ bits32 q;\r
+ bits64 aSig64, bSig64, q64;\r
+ bits32 alternateASig;\r
+ sbits32 sigMean;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ bSig = extractFloat32Frac( b );\r
+ bExp = extractFloat32Exp( b );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {\r
+ return propagateFloat32NaN( a, b );\r
+ }\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( bExp == 0xFF ) {\r
+ if ( bSig ) return propagateFloat32NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return a;\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ expDiff = aExp - bExp;\r
+ aSig |= 0x00800000;\r
+ bSig |= 0x00800000;\r
+ if ( expDiff < 32 ) {\r
+ aSig <<= 8;\r
+ bSig <<= 8;\r
+ if ( expDiff < 0 ) {\r
+ if ( expDiff < -1 ) return a;\r
+ aSig >>= 1;\r
+ }\r
+ q = ( bSig <= aSig );\r
+ if ( q ) aSig -= bSig;\r
+ if ( 0 < expDiff ) {\r
+ q = ( ( (bits64) aSig )<<32 ) / bSig;\r
+ q >>= 32 - expDiff;\r
+ bSig >>= 2;\r
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;\r
+ }\r
+ else {\r
+ aSig >>= 2;\r
+ bSig >>= 2;\r
+ }\r
+ }\r
+ else {\r
+ if ( bSig <= aSig ) aSig -= bSig;\r
+ aSig64 = ( (bits64) aSig )<<40;\r
+ bSig64 = ( (bits64) bSig )<<40;\r
+ expDiff -= 64;\r
+ while ( 0 < expDiff ) {\r
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );\r
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;\r
+ aSig64 = - ( ( bSig * q64 )<<38 );\r
+ expDiff -= 62;\r
+ }\r
+ expDiff += 64;\r
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );\r
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;\r
+ q = q64>>( 64 - expDiff );\r
+ bSig <<= 6;\r
+ aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;\r
+ }\r
+ do {\r
+ alternateASig = aSig;\r
+ ++q;\r
+ aSig -= bSig;\r
+ } while ( 0 <= (sbits32) aSig );\r
+ sigMean = aSig + alternateASig;\r
+ if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {\r
+ aSig = alternateASig;\r
+ }\r
+ zSign = ( (sbits32) aSig < 0 );\r
+ if ( zSign ) aSig = - aSig;\r
+ return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the square root of the single-precision floating-point value `a'.\r
+| The operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float32_sqrt( float32 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, zExp;\r
+ bits32 aSig, zSig;\r
+ bits64 rem, term;\r
+\r
+ aSig = extractFloat32Frac( a );\r
+ aExp = extractFloat32Exp( a );\r
+ aSign = extractFloat32Sign( a );\r
+ if ( aExp == 0xFF ) {\r
+ if ( aSig ) return propagateFloat32NaN( a, 0 );\r
+ if ( ! aSign ) return a;\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( aSign ) {\r
+ if ( ( aExp | aSig ) == 0 ) return a;\r
+ float_raise( float_flag_invalid );\r
+ return float32_default_nan;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return 0;\r
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;\r
+ aSig = ( aSig | 0x00800000 )<<8;\r
+ zSig = estimateSqrt32( aExp, aSig ) + 2;\r
+ if ( ( zSig & 0x7F ) <= 5 ) {\r
+ if ( zSig < 2 ) {\r
+ zSig = 0x7FFFFFFF;\r
+ goto roundAndPack;\r
+ }\r
+ aSig >>= aExp & 1;\r
+ term = ( (bits64) zSig ) * zSig;\r
+ rem = ( ( (bits64) aSig )<<32 ) - term;\r
+ while ( (sbits64) rem < 0 ) {\r
+ --zSig;\r
+ rem += ( ( (bits64) zSig )<<1 ) | 1;\r
+ }\r
+ zSig |= ( rem != 0 );\r
+ }\r
+ shift32RightJamming( zSig, 1, &zSig );\r
+ roundAndPack:\r
+ return roundAndPackFloat32( 0, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_eq( float32 a, float32 b )\r
+{\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than\r
+| or equal to the corresponding value `b', and 0 otherwise. The comparison\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_le( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+ return ( a == b ) || ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_lt( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );\r
+ return ( a != b ) && ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The invalid exception is\r
+| raised if either operand is a NaN. Otherwise, the comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_eq_signaling( float32 a, float32 b )\r
+{\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than or\r
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not\r
+| cause an exception. Otherwise, the comparison is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_le_quiet( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+ int16 aExp, bExp;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
+ return ( a == b ) || ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an\r
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_lt_quiet( float32 a, float32 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
+ || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
+ ) {\r
+ if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat32Sign( a );\r
+ bSign = extractFloat32Sign( b );\r
+ if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );\r
+ return ( a != b ) && ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float64_to_int32( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits64 aSig;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;\r
+ if ( aExp ) aSig |= LIT64( 0x0010000000000000 );\r
+ shiftCount = 0x42C - aExp;\r
+ if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );\r
+ return roundAndPackInt32( aSign, aSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the 32-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero.\r
+| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\r
+| the conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float64_to_int32_round_to_zero( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits64 aSig, savedASig;\r
+ int32 z;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( 0x41E < aExp ) {\r
+ if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;\r
+ goto invalid;\r
+ }\r
+ else if ( aExp < 0x3FF ) {\r
+ if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ aSig |= LIT64( 0x0010000000000000 );\r
+ shiftCount = 0x433 - aExp;\r
+ savedASig = aSig;\r
+ aSig >>= shiftCount;\r
+ z = aSig;\r
+ if ( aSign ) z = - z;\r
+ if ( ( z < 0 ) ^ aSign ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
+ }\r
+ if ( ( aSig<<shiftCount ) != savedASig ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the 64-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 float64_to_int64( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits64 aSig, aSigExtra;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp ) aSig |= LIT64( 0x0010000000000000 );\r
+ shiftCount = 0x433 - aExp;\r
+ if ( shiftCount <= 0 ) {\r
+ if ( 0x43E < aExp ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign\r
+ || ( ( aExp == 0x7FF )\r
+ && ( aSig != LIT64( 0x0010000000000000 ) ) )\r
+ ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ aSigExtra = 0;\r
+ aSig <<= - shiftCount;\r
+ }\r
+ else {\r
+ shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra );\r
+ }\r
+ return roundAndPackInt64( aSign, aSig, aSigExtra );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the 64-bit two's complement integer format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero.\r
+| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\r
+| the conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 float64_to_int64_round_to_zero( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, shiftCount;\r
+ bits64 aSig;\r
+ int64 z;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp ) aSig |= LIT64( 0x0010000000000000 );\r
+ shiftCount = aExp - 0x433;\r
+ if ( 0 <= shiftCount ) {\r
+ if ( 0x43E <= aExp ) {\r
+ if ( a != LIT64( 0xC3E0000000000000 ) ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign\r
+ || ( ( aExp == 0x7FF )\r
+ && ( aSig != LIT64( 0x0010000000000000 ) ) )\r
+ ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ z = aSig<<shiftCount;\r
+ }\r
+ else {\r
+ if ( aExp < 0x3FE ) {\r
+ if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ z = aSig>>( - shiftCount );\r
+ if ( (bits64) ( aSig<<( shiftCount & 63 ) ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ }\r
+ if ( aSign ) z = - z;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the single-precision floating-point format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float64_to_float32( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits64 aSig;\r
+ bits32 zSig;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return commonNaNToFloat32( float64ToCommonNaN( a ) );\r
+ return packFloat32( aSign, 0xFF, 0 );\r
+ }\r
+ shift64RightJamming( aSig, 22, &aSig );\r
+ zSig = aSig;\r
+ if ( aExp || zSig ) {\r
+ zSig |= 0x40000000;\r
+ aExp -= 0x381;\r
+ }\r
+ return roundAndPackFloat32( aSign, aExp, zSig );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the extended double-precision floating-point format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 float64_to_floatx80( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits64 aSig;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return commonNaNToFloatx80( float64ToCommonNaN( a ) );\r
+ return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ return\r
+ packFloatx80(\r
+ aSign, aExp + 0x3C00, ( aSig | LIT64( 0x0010000000000000 ) )<<11 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point value\r
+| `a' to the quadruple-precision floating-point format. The conversion is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float64_to_float128( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits64 aSig, zSig0, zSig1;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return commonNaNToFloat128( float64ToCommonNaN( a ) );\r
+ return packFloat128( aSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
+ --aExp;\r
+ }\r
+ shift128Right( aSig, 0, 4, &zSig0, &zSig1 );\r
+ return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Rounds the double-precision floating-point value `a' to an integer, and\r
+| returns the result as a double-precision floating-point value. The\r
+| operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_round_to_int( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits64 lastBitMask, roundBitsMask;\r
+ int8 roundingMode;\r
+ float64 z;\r
+\r
+ aExp = extractFloat64Exp( a );\r
+ if ( 0x433 <= aExp ) {\r
+ if ( ( aExp == 0x7FF ) && extractFloat64Frac( a ) ) {\r
+ return propagateFloat64NaN( a, a );\r
+ }\r
+ return a;\r
+ }\r
+ if ( aExp < 0x3FF ) {\r
+ if ( (bits64) ( a<<1 ) == 0 ) return a;\r
+ float_exception_flags |= float_flag_inexact;\r
+ aSign = extractFloat64Sign( a );\r
+ switch ( float_rounding_mode ) {\r
+ case float_round_nearest_even:\r
+ if ( ( aExp == 0x3FE ) && extractFloat64Frac( a ) ) {\r
+ return packFloat64( aSign, 0x3FF, 0 );\r
+ }\r
+ break;\r
+ case float_round_down:\r
+ return aSign ? LIT64( 0xBFF0000000000000 ) : 0;\r
+ case float_round_up:\r
+ return\r
+ aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 );\r
+ }\r
+ return packFloat64( aSign, 0, 0 );\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask <<= 0x433 - aExp;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z = a;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ z += lastBitMask>>1;\r
+ if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat64Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
+ z += roundBitsMask;\r
+ }\r
+ }\r
+ z &= ~ roundBitsMask;\r
+ if ( z != a ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the double-precision\r
+| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated\r
+| before being returned. `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig;\r
+ int16 expDiff;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ bSig = extractFloat64Frac( b );\r
+ bExp = extractFloat64Exp( b );\r
+ expDiff = aExp - bExp;\r
+ aSig <<= 9;\r
+ bSig <<= 9;\r
+ if ( 0 < expDiff ) {\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig |= LIT64( 0x2000000000000000 );\r
+ }\r
+ shift64RightJamming( bSig, expDiff, &bSig );\r
+ zExp = aExp;\r
+ }\r
+ else if ( expDiff < 0 ) {\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig ) return propagateFloat64NaN( a, b );\r
+ return packFloat64( zSign, 0x7FF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig |= LIT64( 0x2000000000000000 );\r
+ }\r
+ shift64RightJamming( aSig, - expDiff, &aSig );\r
+ zExp = bExp;\r
+ }\r
+ else {\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig | bSig ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( aExp == 0 ) return packFloat64( zSign, 0, ( aSig + bSig )>>9 );\r
+ zSig = LIT64( 0x4000000000000000 ) + aSig + bSig;\r
+ zExp = aExp;\r
+ goto roundAndPack;\r
+ }\r
+ aSig |= LIT64( 0x2000000000000000 );\r
+ zSig = ( aSig + bSig )<<1;\r
+ --zExp;\r
+ if ( (sbits64) zSig < 0 ) {\r
+ zSig = aSig + bSig;\r
+ ++zExp;\r
+ }\r
+ roundAndPack:\r
+ return roundAndPackFloat64( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the double-\r
+| precision floating-point values `a' and `b'. If `zSign' is 1, the\r
+| difference is negated before being returned. `zSign' is ignored if the\r
+| result is a NaN. The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )\r
+{\r
+ int16 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig;\r
+ int16 expDiff;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ bSig = extractFloat64Frac( b );\r
+ bExp = extractFloat64Exp( b );\r
+ expDiff = aExp - bExp;\r
+ aSig <<= 10;\r
+ bSig <<= 10;\r
+ if ( 0 < expDiff ) goto aExpBigger;\r
+ if ( expDiff < 0 ) goto bExpBigger;\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig | bSig ) return propagateFloat64NaN( a, b );\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ aExp = 1;\r
+ bExp = 1;\r
+ }\r
+ if ( bSig < aSig ) goto aBigger;\r
+ if ( aSig < bSig ) goto bBigger;\r
+ return packFloat64( float_rounding_mode == float_round_down, 0, 0 );\r
+ bExpBigger:\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig ) return propagateFloat64NaN( a, b );\r
+ return packFloat64( zSign ^ 1, 0x7FF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig |= LIT64( 0x4000000000000000 );\r
+ }\r
+ shift64RightJamming( aSig, - expDiff, &aSig );\r
+ bSig |= LIT64( 0x4000000000000000 );\r
+ bBigger:\r
+ zSig = bSig - aSig;\r
+ zExp = bExp;\r
+ zSign ^= 1;\r
+ goto normalizeRoundAndPack;\r
+ aExpBigger:\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig |= LIT64( 0x4000000000000000 );\r
+ }\r
+ shift64RightJamming( bSig, expDiff, &bSig );\r
+ aSig |= LIT64( 0x4000000000000000 );\r
+ aBigger:\r
+ zSig = aSig - bSig;\r
+ zExp = aExp;\r
+ normalizeRoundAndPack:\r
+ --zExp;\r
+ return normalizeRoundAndPackFloat64( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the double-precision floating-point values `a'\r
+| and `b'. The operation is performed according to the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_add( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return addFloat64Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return subFloat64Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the double-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_sub( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return subFloat64Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return addFloat64Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of multiplying the double-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_mul( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig0, zSig1;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ bSig = extractFloat64Frac( b );\r
+ bExp = extractFloat64Exp( b );\r
+ bSign = extractFloat64Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {\r
+ return propagateFloat64NaN( a, b );\r
+ }\r
+ if ( ( bExp | bSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ return packFloat64( zSign, 0x7FF, 0 );\r
+ }\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig ) return propagateFloat64NaN( a, b );\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ return packFloat64( zSign, 0x7FF, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) return packFloat64( zSign, 0, 0 );\r
+ normalizeFloat64Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ zExp = aExp + bExp - 0x3FF;\r
+ aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;\r
+ bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;\r
+ mul64To128( aSig, bSig, &zSig0, &zSig1 );\r
+ zSig0 |= ( zSig1 != 0 );\r
+ if ( 0 <= (sbits64) ( zSig0<<1 ) ) {\r
+ zSig0 <<= 1;\r
+ --zExp;\r
+ }\r
+ return roundAndPackFloat64( zSign, zExp, zSig0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of dividing the double-precision floating-point value `a'\r
+| by the corresponding value `b'. The operation is performed according to\r
+| the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_div( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig;\r
+ bits64 rem0, rem1;\r
+ bits64 term0, term1;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ bSig = extractFloat64Frac( b );\r
+ bExp = extractFloat64Exp( b );\r
+ bSign = extractFloat64Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return propagateFloat64NaN( a, b );\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig ) return propagateFloat64NaN( a, b );\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ return packFloat64( zSign, 0x7FF, 0 );\r
+ }\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig ) return propagateFloat64NaN( a, b );\r
+ return packFloat64( zSign, 0, 0 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ float_raise( float_flag_divbyzero );\r
+ return packFloat64( zSign, 0x7FF, 0 );\r
+ }\r
+ normalizeFloat64Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );\r
+ normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = aExp - bExp + 0x3FD;\r
+ aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;\r
+ bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;\r
+ if ( bSig <= ( aSig + aSig ) ) {\r
+ aSig >>= 1;\r
+ ++zExp;\r
+ }\r
+ zSig = estimateDiv128To64( aSig, 0, bSig );\r
+ if ( ( zSig & 0x1FF ) <= 2 ) {\r
+ mul64To128( bSig, zSig, &term0, &term1 );\r
+ sub128( aSig, 0, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits64) rem0 < 0 ) {\r
+ --zSig;\r
+ add128( rem0, rem1, 0, bSig, &rem0, &rem1 );\r
+ }\r
+ zSig |= ( rem1 != 0 );\r
+ }\r
+ return roundAndPackFloat64( zSign, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the remainder of the double-precision floating-point value `a'\r
+| with respect to the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_rem( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int16 aExp, bExp, expDiff;\r
+ bits64 aSig, bSig;\r
+ bits64 q, alternateASig;\r
+ sbits64 sigMean;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ bSig = extractFloat64Frac( b );\r
+ bExp = extractFloat64Exp( b );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {\r
+ return propagateFloat64NaN( a, b );\r
+ }\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ if ( bExp == 0x7FF ) {\r
+ if ( bSig ) return propagateFloat64NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ normalizeFloat64Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return a;\r
+ normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ expDiff = aExp - bExp;\r
+ aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<11;\r
+ bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;\r
+ if ( expDiff < 0 ) {\r
+ if ( expDiff < -1 ) return a;\r
+ aSig >>= 1;\r
+ }\r
+ q = ( bSig <= aSig );\r
+ if ( q ) aSig -= bSig;\r
+ expDiff -= 64;\r
+ while ( 0 < expDiff ) {\r
+ q = estimateDiv128To64( aSig, 0, bSig );\r
+ q = ( 2 < q ) ? q - 2 : 0;\r
+ aSig = - ( ( bSig>>2 ) * q );\r
+ expDiff -= 62;\r
+ }\r
+ expDiff += 64;\r
+ if ( 0 < expDiff ) {\r
+ q = estimateDiv128To64( aSig, 0, bSig );\r
+ q = ( 2 < q ) ? q - 2 : 0;\r
+ q >>= 64 - expDiff;\r
+ bSig >>= 2;\r
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;\r
+ }\r
+ else {\r
+ aSig >>= 2;\r
+ bSig >>= 2;\r
+ }\r
+ do {\r
+ alternateASig = aSig;\r
+ ++q;\r
+ aSig -= bSig;\r
+ } while ( 0 <= (sbits64) aSig );\r
+ sigMean = aSig + alternateASig;\r
+ if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {\r
+ aSig = alternateASig;\r
+ }\r
+ zSign = ( (sbits64) aSig < 0 );\r
+ if ( zSign ) aSig = - aSig;\r
+ return normalizeRoundAndPackFloat64( aSign ^ zSign, bExp, aSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the square root of the double-precision floating-point value `a'.\r
+| The operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float64_sqrt( float64 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp, zExp;\r
+ bits64 aSig, zSig, doubleZSig;\r
+ bits64 rem0, rem1, term0, term1;\r
+ float64 z;\r
+\r
+ aSig = extractFloat64Frac( a );\r
+ aExp = extractFloat64Exp( a );\r
+ aSign = extractFloat64Sign( a );\r
+ if ( aExp == 0x7FF ) {\r
+ if ( aSig ) return propagateFloat64NaN( a, a );\r
+ if ( ! aSign ) return a;\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ if ( aSign ) {\r
+ if ( ( aExp | aSig ) == 0 ) return a;\r
+ float_raise( float_flag_invalid );\r
+ return float64_default_nan;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return 0;\r
+ normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;\r
+ aSig |= LIT64( 0x0010000000000000 );\r
+ zSig = estimateSqrt32( aExp, aSig>>21 );\r
+ aSig <<= 9 - ( aExp & 1 );\r
+ zSig = estimateDiv128To64( aSig, 0, zSig<<32 ) + ( zSig<<30 );\r
+ if ( ( zSig & 0x1FF ) <= 5 ) {\r
+ doubleZSig = zSig<<1;\r
+ mul64To128( zSig, zSig, &term0, &term1 );\r
+ sub128( aSig, 0, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits64) rem0 < 0 ) {\r
+ --zSig;\r
+ doubleZSig -= 2;\r
+ add128( rem0, rem1, zSig>>63, doubleZSig | 1, &rem0, &rem1 );\r
+ }\r
+ zSig |= ( ( rem0 | rem1 ) != 0 );\r
+ }\r
+ return roundAndPackFloat64( 0, zExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is equal to the\r
+| corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_eq( float64 a, float64 b )\r
+{\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
+ ) {\r
+ if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than or\r
+| equal to the corresponding value `b', and 0 otherwise. The comparison is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_le( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
+ return ( a == b ) || ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_lt( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );\r
+ return ( a != b ) && ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is equal to the\r
+| corresponding value `b', and 0 otherwise. The invalid exception is raised\r
+| if either operand is a NaN. Otherwise, the comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_eq_signaling( float64 a, float64 b )\r
+{\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than or\r
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not\r
+| cause an exception. Otherwise, the comparison is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_le_quiet( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+ int16 aExp, bExp;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
+ ) {\r
+ if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
+ return ( a == b ) || ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an\r
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_lt_quiet( float64 a, float64 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
+ || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
+ ) {\r
+ if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat64Sign( a );\r
+ bSign = extractFloat64Sign( b );\r
+ if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );\r
+ return ( a != b ) && ( aSign ^ ( a < b ) );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the 32-bit two's complement integer format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic---which means in particular that the conversion\r
+| is rounded according to the current rounding mode. If `a' is a NaN, the\r
+| largest positive integer is returned. Otherwise, if the conversion\r
+| overflows, the largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 floatx80_to_int32( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;\r
+ shiftCount = 0x4037 - aExp;\r
+ if ( shiftCount <= 0 ) shiftCount = 1;\r
+ shift64RightJamming( aSig, shiftCount, &aSig );\r
+ return roundAndPackInt32( aSign, aSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the 32-bit two's complement integer format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic, except that the conversion is always rounded\r
+| toward zero. If `a' is a NaN, the largest positive integer is returned.\r
+| Otherwise, if the conversion overflows, the largest integer with the same\r
+| sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 floatx80_to_int32_round_to_zero( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig, savedASig;\r
+ int32 z;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ if ( 0x401E < aExp ) {\r
+ if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;\r
+ goto invalid;\r
+ }\r
+ else if ( aExp < 0x3FFF ) {\r
+ if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ shiftCount = 0x403E - aExp;\r
+ savedASig = aSig;\r
+ aSig >>= shiftCount;\r
+ z = aSig;\r
+ if ( aSign ) z = - z;\r
+ if ( ( z < 0 ) ^ aSign ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
+ }\r
+ if ( ( aSig<<shiftCount ) != savedASig ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the 64-bit two's complement integer format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic---which means in particular that the conversion\r
+| is rounded according to the current rounding mode. If `a' is a NaN,\r
+| the largest positive integer is returned. Otherwise, if the conversion\r
+| overflows, the largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 floatx80_to_int64( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig, aSigExtra;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ shiftCount = 0x403E - aExp;\r
+ if ( shiftCount <= 0 ) {\r
+ if ( shiftCount ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign\r
+ || ( ( aExp == 0x7FFF )\r
+ && ( aSig != LIT64( 0x8000000000000000 ) ) )\r
+ ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ aSigExtra = 0;\r
+ }\r
+ else {\r
+ shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra );\r
+ }\r
+ return roundAndPackInt64( aSign, aSig, aSigExtra );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the 64-bit two's complement integer format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic, except that the conversion is always rounded\r
+| toward zero. If `a' is a NaN, the largest positive integer is returned.\r
+| Otherwise, if the conversion overflows, the largest integer with the same\r
+| sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 floatx80_to_int64_round_to_zero( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig;\r
+ int64 z;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ shiftCount = aExp - 0x403E;\r
+ if ( 0 <= shiftCount ) {\r
+ aSig &= LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ if ( ( a.high != 0xC03E ) || aSig ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0x7FFF ) && aSig ) ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ else if ( aExp < 0x3FFF ) {\r
+ if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ z = aSig>>( - shiftCount );\r
+ if ( (bits64) ( aSig<<( shiftCount & 63 ) ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ if ( aSign ) z = - z;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the single-precision floating-point format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 floatx80_to_float32( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 aSig;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig<<1 ) ) {\r
+ return commonNaNToFloat32( floatx80ToCommonNaN( a ) );\r
+ }\r
+ return packFloat32( aSign, 0xFF, 0 );\r
+ }\r
+ shift64RightJamming( aSig, 33, &aSig );\r
+ if ( aExp || aSig ) aExp -= 0x3F81;\r
+ return roundAndPackFloat32( aSign, aExp, aSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the double-precision floating-point format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 floatx80_to_float64( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 aSig, zSig;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig<<1 ) ) {\r
+ return commonNaNToFloat64( floatx80ToCommonNaN( a ) );\r
+ }\r
+ return packFloat64( aSign, 0x7FF, 0 );\r
+ }\r
+ shift64RightJamming( aSig, 1, &zSig );\r
+ if ( aExp || aSig ) aExp -= 0x3C01;\r
+ return roundAndPackFloat64( aSign, aExp, zSig );\r
+\r
+}\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point value `a' to the quadruple-precision floating-point format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 floatx80_to_float128( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int16 aExp;\r
+ bits64 aSig, zSig0, zSig1;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) {\r
+ return commonNaNToFloat128( floatx80ToCommonNaN( a ) );\r
+ }\r
+ shift128Right( aSig<<1, 0, 16, &zSig0, &zSig1 );\r
+ return packFloat128( aSign, aExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Rounds the extended double-precision floating-point value `a' to an integer,\r
+| and returns the result as an extended quadruple-precision floating-point\r
+| value. The operation is performed according to the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_round_to_int( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 lastBitMask, roundBitsMask;\r
+ int8 roundingMode;\r
+ floatx80 z;\r
+\r
+ aExp = extractFloatx80Exp( a );\r
+ if ( 0x403E <= aExp ) {\r
+ if ( ( aExp == 0x7FFF ) && (bits64) ( extractFloatx80Frac( a )<<1 ) ) {\r
+ return propagateFloatx80NaN( a, a );\r
+ }\r
+ return a;\r
+ }\r
+ if ( aExp < 0x3FFF ) {\r
+ if ( ( aExp == 0 )\r
+ && ( (bits64) ( extractFloatx80Frac( a )<<1 ) == 0 ) ) {\r
+ return a;\r
+ }\r
+ float_exception_flags |= float_flag_inexact;\r
+ aSign = extractFloatx80Sign( a );\r
+ switch ( float_rounding_mode ) {\r
+ case float_round_nearest_even:\r
+ if ( ( aExp == 0x3FFE ) && (bits64) ( extractFloatx80Frac( a )<<1 )\r
+ ) {\r
+ return\r
+ packFloatx80( aSign, 0x3FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ break;\r
+ case float_round_down:\r
+ return\r
+ aSign ?\r
+ packFloatx80( 1, 0x3FFF, LIT64( 0x8000000000000000 ) )\r
+ : packFloatx80( 0, 0, 0 );\r
+ case float_round_up:\r
+ return\r
+ aSign ? packFloatx80( 1, 0, 0 )\r
+ : packFloatx80( 0, 0x3FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ return packFloatx80( aSign, 0, 0 );\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask <<= 0x403E - aExp;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z = a;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ z.low += lastBitMask>>1;\r
+ if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloatx80Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
+ z.low += roundBitsMask;\r
+ }\r
+ }\r
+ z.low &= ~ roundBitsMask;\r
+ if ( z.low == 0 ) {\r
+ ++z.high;\r
+ z.low = LIT64( 0x8000000000000000 );\r
+ }\r
+ if ( z.low != a.low ) float_exception_flags |= float_flag_inexact;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the extended double-\r
+| precision floating-point values `a' and `b'. If `zSign' is 1, the sum is\r
+| negated before being returned. `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )\r
+{\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig0, zSig1;\r
+ int32 expDiff;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ bSig = extractFloatx80Frac( b );\r
+ bExp = extractFloatx80Exp( b );\r
+ expDiff = aExp - bExp;\r
+ if ( 0 < expDiff ) {\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) --expDiff;\r
+ shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 );\r
+ zExp = aExp;\r
+ }\r
+ else if ( expDiff < 0 ) {\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( aExp == 0 ) ++expDiff;\r
+ shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );\r
+ zExp = bExp;\r
+ }\r
+ else {\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( ( aSig | bSig )<<1 ) ) {\r
+ return propagateFloatx80NaN( a, b );\r
+ }\r
+ return a;\r
+ }\r
+ zSig1 = 0;\r
+ zSig0 = aSig + bSig;\r
+ if ( aExp == 0 ) {\r
+ normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 );\r
+ goto roundAndPack;\r
+ }\r
+ zExp = aExp;\r
+ goto shiftRight1;\r
+ }\r
+ zSig0 = aSig + bSig;\r
+ if ( (sbits64) zSig0 < 0 ) goto roundAndPack;\r
+ shiftRight1:\r
+ shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 );\r
+ zSig0 |= LIT64( 0x8000000000000000 );\r
+ ++zExp;\r
+ roundAndPack:\r
+ return\r
+ roundAndPackFloatx80(\r
+ floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the extended\r
+| double-precision floating-point values `a' and `b'. If `zSign' is 1, the\r
+| difference is negated before being returned. `zSign' is ignored if the\r
+| result is a NaN. The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )\r
+{\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig0, zSig1;\r
+ int32 expDiff;\r
+ floatx80 z;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ bSig = extractFloatx80Frac( b );\r
+ bExp = extractFloatx80Exp( b );\r
+ expDiff = aExp - bExp;\r
+ if ( 0 < expDiff ) goto aExpBigger;\r
+ if ( expDiff < 0 ) goto bExpBigger;\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( ( aSig | bSig )<<1 ) ) {\r
+ return propagateFloatx80NaN( a, b );\r
+ }\r
+ float_raise( float_flag_invalid );\r
+ z.low = floatx80_default_nan_low;\r
+ z.high = floatx80_default_nan_high;\r
+ return z;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ aExp = 1;\r
+ bExp = 1;\r
+ }\r
+ zSig1 = 0;\r
+ if ( bSig < aSig ) goto aBigger;\r
+ if ( aSig < bSig ) goto bBigger;\r
+ return packFloatx80( float_rounding_mode == float_round_down, 0, 0 );\r
+ bExpBigger:\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( aExp == 0 ) ++expDiff;\r
+ shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );\r
+ bBigger:\r
+ sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 );\r
+ zExp = bExp;\r
+ zSign ^= 1;\r
+ goto normalizeRoundAndPack;\r
+ aExpBigger:\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) --expDiff;\r
+ shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 );\r
+ aBigger:\r
+ sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 );\r
+ zExp = aExp;\r
+ normalizeRoundAndPack:\r
+ return\r
+ normalizeRoundAndPackFloatx80(\r
+ floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the extended double-precision floating-point\r
+| values `a' and `b'. The operation is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_add( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloatx80Sign( a );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return addFloatx80Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return subFloatx80Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the extended double-precision floating-\r
+| point values `a' and `b'. The operation is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_sub( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloatx80Sign( a );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return subFloatx80Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return addFloatx80Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of multiplying the extended double-precision floating-\r
+| point values `a' and `b'. The operation is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_mul( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig0, zSig1;\r
+ floatx80 z;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ bSig = extractFloatx80Frac( b );\r
+ bExp = extractFloatx80Exp( b );\r
+ bSign = extractFloatx80Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig<<1 )\r
+ || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {\r
+ return propagateFloatx80NaN( a, b );\r
+ }\r
+ if ( ( bExp | bSig ) == 0 ) goto invalid;\r
+ return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = floatx80_default_nan_low;\r
+ z.high = floatx80_default_nan_high;\r
+ return z;\r
+ }\r
+ return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );\r
+ normalizeFloatx80Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) return packFloatx80( zSign, 0, 0 );\r
+ normalizeFloatx80Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ zExp = aExp + bExp - 0x3FFE;\r
+ mul64To128( aSig, bSig, &zSig0, &zSig1 );\r
+ if ( 0 < (sbits64) zSig0 ) {\r
+ shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 );\r
+ --zExp;\r
+ }\r
+ return\r
+ roundAndPackFloatx80(\r
+ floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of dividing the extended double-precision floating-point\r
+| value `a' by the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_div( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig, bSig, zSig0, zSig1;\r
+ bits64 rem0, rem1, rem2, term0, term1, term2;\r
+ floatx80 z;\r
+\r
+ aSig = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ bSig = extractFloatx80Frac( b );\r
+ bExp = extractFloatx80Exp( b );\r
+ bSign = extractFloatx80Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ goto invalid;\r
+ }\r
+ return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ return packFloatx80( zSign, 0, 0 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ if ( ( aExp | aSig ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = floatx80_default_nan_low;\r
+ z.high = floatx80_default_nan_high;\r
+ return z;\r
+ }\r
+ float_raise( float_flag_divbyzero );\r
+ return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ normalizeFloatx80Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );\r
+ normalizeFloatx80Subnormal( aSig, &aExp, &aSig );\r
+ }\r
+ zExp = aExp - bExp + 0x3FFE;\r
+ rem1 = 0;\r
+ if ( bSig <= aSig ) {\r
+ shift128Right( aSig, 0, 1, &aSig, &rem1 );\r
+ ++zExp;\r
+ }\r
+ zSig0 = estimateDiv128To64( aSig, rem1, bSig );\r
+ mul64To128( bSig, zSig0, &term0, &term1 );\r
+ sub128( aSig, rem1, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits64) rem0 < 0 ) {\r
+ --zSig0;\r
+ add128( rem0, rem1, 0, bSig, &rem0, &rem1 );\r
+ }\r
+ zSig1 = estimateDiv128To64( rem1, 0, bSig );\r
+ if ( (bits64) ( zSig1<<1 ) <= 8 ) {\r
+ mul64To128( bSig, zSig1, &term1, &term2 );\r
+ sub128( rem1, 0, term1, term2, &rem1, &rem2 );\r
+ while ( (sbits64) rem1 < 0 ) {\r
+ --zSig1;\r
+ add128( rem1, rem2, 0, bSig, &rem1, &rem2 );\r
+ }\r
+ zSig1 |= ( ( rem1 | rem2 ) != 0 );\r
+ }\r
+ return\r
+ roundAndPackFloatx80(\r
+ floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the remainder of the extended double-precision floating-point value\r
+| `a' with respect to the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_rem( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int32 aExp, bExp, expDiff;\r
+ bits64 aSig0, aSig1, bSig;\r
+ bits64 q, term0, term1, alternateASig0, alternateASig1;\r
+ floatx80 z;\r
+\r
+ aSig0 = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ bSig = extractFloatx80Frac( b );\r
+ bExp = extractFloatx80Exp( b );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig0<<1 )\r
+ || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {\r
+ return propagateFloatx80NaN( a, b );\r
+ }\r
+ goto invalid;\r
+ }\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( bSig == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = floatx80_default_nan_low;\r
+ z.high = floatx80_default_nan_high;\r
+ return z;\r
+ }\r
+ normalizeFloatx80Subnormal( bSig, &bExp, &bSig );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( (bits64) ( aSig0<<1 ) == 0 ) return a;\r
+ normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );\r
+ }\r
+ bSig |= LIT64( 0x8000000000000000 );\r
+ zSign = aSign;\r
+ expDiff = aExp - bExp;\r
+ aSig1 = 0;\r
+ if ( expDiff < 0 ) {\r
+ if ( expDiff < -1 ) return a;\r
+ shift128Right( aSig0, 0, 1, &aSig0, &aSig1 );\r
+ expDiff = 0;\r
+ }\r
+ q = ( bSig <= aSig0 );\r
+ if ( q ) aSig0 -= bSig;\r
+ expDiff -= 64;\r
+ while ( 0 < expDiff ) {\r
+ q = estimateDiv128To64( aSig0, aSig1, bSig );\r
+ q = ( 2 < q ) ? q - 2 : 0;\r
+ mul64To128( bSig, q, &term0, &term1 );\r
+ sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );\r
+ shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 );\r
+ expDiff -= 62;\r
+ }\r
+ expDiff += 64;\r
+ if ( 0 < expDiff ) {\r
+ q = estimateDiv128To64( aSig0, aSig1, bSig );\r
+ q = ( 2 < q ) ? q - 2 : 0;\r
+ q >>= 64 - expDiff;\r
+ mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 );\r
+ sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );\r
+ shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 );\r
+ while ( le128( term0, term1, aSig0, aSig1 ) ) {\r
+ ++q;\r
+ sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );\r
+ }\r
+ }\r
+ else {\r
+ term1 = 0;\r
+ term0 = bSig;\r
+ }\r
+ sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASig1 );\r
+ if ( lt128( alternateASig0, alternateASig1, aSig0, aSig1 )\r
+ || ( eq128( alternateASig0, alternateASig1, aSig0, aSig1 )\r
+ && ( q & 1 ) )\r
+ ) {\r
+ aSig0 = alternateASig0;\r
+ aSig1 = alternateASig1;\r
+ zSign = ! zSign;\r
+ }\r
+ return\r
+ normalizeRoundAndPackFloatx80(\r
+ 80, zSign, bExp + expDiff, aSig0, aSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the square root of the extended double-precision floating-point\r
+| value `a'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 floatx80_sqrt( floatx80 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, zExp;\r
+ bits64 aSig0, aSig1, zSig0, zSig1, doubleZSig0;\r
+ bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
+ floatx80 z;\r
+\r
+ aSig0 = extractFloatx80Frac( a );\r
+ aExp = extractFloatx80Exp( a );\r
+ aSign = extractFloatx80Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( (bits64) ( aSig0<<1 ) ) return propagateFloatx80NaN( a, a );\r
+ if ( ! aSign ) return a;\r
+ goto invalid;\r
+ }\r
+ if ( aSign ) {\r
+ if ( ( aExp | aSig0 ) == 0 ) return a;\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = floatx80_default_nan_low;\r
+ z.high = floatx80_default_nan_high;\r
+ return z;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );\r
+ normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );\r
+ }\r
+ zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF;\r
+ zSig0 = estimateSqrt32( aExp, aSig0>>32 );\r
+ shift128Right( aSig0, 0, 2 + ( aExp & 1 ), &aSig0, &aSig1 );\r
+ zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );\r
+ doubleZSig0 = zSig0<<1;\r
+ mul64To128( zSig0, zSig0, &term0, &term1 );\r
+ sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits64) rem0 < 0 ) {\r
+ --zSig0;\r
+ doubleZSig0 -= 2;\r
+ add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 );\r
+ }\r
+ zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 );\r
+ if ( ( zSig1 & LIT64( 0x3FFFFFFFFFFFFFFF ) ) <= 5 ) {\r
+ if ( zSig1 == 0 ) zSig1 = 1;\r
+ mul64To128( doubleZSig0, zSig1, &term1, &term2 );\r
+ sub128( rem1, 0, term1, term2, &rem1, &rem2 );\r
+ mul64To128( zSig1, zSig1, &term2, &term3 );\r
+ sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );\r
+ while ( (sbits64) rem1 < 0 ) {\r
+ --zSig1;\r
+ shortShift128Left( 0, zSig1, 1, &term2, &term3 );\r
+ term3 |= 1;\r
+ term2 |= doubleZSig0;\r
+ add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );\r
+ }\r
+ zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
+ }\r
+ shortShift128Left( 0, zSig1, 1, &zSig0, &zSig1 );\r
+ zSig0 |= doubleZSig0;\r
+ return\r
+ roundAndPackFloatx80(\r
+ floatx80_rounding_precision, 0, zExp, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is\r
+| equal to the corresponding value `b', and 0 otherwise. The comparison is\r
+| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_eq( floatx80 a, floatx80 b )\r
+{\r
+\r
+ if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
+ || ( ( extractFloatx80Exp( b ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
+ ) {\r
+ if ( floatx80_is_signaling_nan( a )\r
+ || floatx80_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ return\r
+ ( a.low == b.low )\r
+ && ( ( a.high == b.high )\r
+ || ( ( a.low == 0 )\r
+ && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )\r
+ );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is\r
+| less than or equal to the corresponding value `b', and 0 otherwise. The\r
+| comparison is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_le( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
+ || ( ( extractFloatx80Exp( b ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloatx80Sign( a );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ || ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ == 0 );\r
+ }\r
+ return\r
+ aSign ? le128( b.high, b.low, a.high, a.low )\r
+ : le128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is\r
+| less than the corresponding value `b', and 0 otherwise. The comparison\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_lt( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
+ || ( ( extractFloatx80Exp( b ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloatx80Sign( a );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ && ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ != 0 );\r
+ }\r
+ return\r
+ aSign ? lt128( b.high, b.low, a.high, a.low )\r
+ : lt128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is equal\r
+| to the corresponding value `b', and 0 otherwise. The invalid exception is\r
+| raised if either operand is a NaN. Otherwise, the comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_eq_signaling( floatx80 a, floatx80 b )\r
+{\r
+\r
+ if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
+ || ( ( extractFloatx80Exp( b ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ return\r
+ ( a.low == b.low )\r
+ && ( ( a.high == b.high )\r
+ || ( ( a.low == 0 )\r
+ && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )\r
+ );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is less\r
+| than or equal to the corresponding value `b', and 0 otherwise. Quiet NaNs\r
+| do not cause an exception. Otherwise, the comparison is performed according\r
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_le_quiet( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
+ || ( ( extractFloatx80Exp( b ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
+ ) {\r
+ if ( floatx80_is_signaling_nan( a )\r
+ || floatx80_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloatx80Sign( a );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ || ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ == 0 );\r
+ }\r
+ return\r
+ aSign ? le128( b.high, b.low, a.high, a.low )\r
+ : le128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is less\r
+| than the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause\r
+| an exception. Otherwise, the comparison is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_lt_quiet( floatx80 a, floatx80 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloatx80Exp( a ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
+ || ( ( extractFloatx80Exp( b ) == 0x7FFF )\r
+ && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
+ ) {\r
+ if ( floatx80_is_signaling_nan( a )\r
+ || floatx80_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloatx80Sign( a );\r
+ bSign = extractFloatx80Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ && ( ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ != 0 );\r
+ }\r
+ return\r
+ aSign ? lt128( b.high, b.low, a.high, a.low )\r
+ : lt128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the 32-bit two's complement integer format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float128_to_int32( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig0, aSig1;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0;\r
+ if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );\r
+ aSig0 |= ( aSig1 != 0 );\r
+ shiftCount = 0x4028 - aExp;\r
+ if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 );\r
+ return roundAndPackInt32( aSign, aSig0 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the 32-bit two's complement integer format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero. If\r
+| `a' is a NaN, the largest positive integer is returned. Otherwise, if the\r
+| conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int32 float128_to_int32_round_to_zero( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig0, aSig1, savedASig;\r
+ int32 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ aSig0 |= ( aSig1 != 0 );\r
+ if ( 0x401E < aExp ) {\r
+ if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0;\r
+ goto invalid;\r
+ }\r
+ else if ( aExp < 0x3FFF ) {\r
+ if ( aExp || aSig0 ) float_exception_flags |= float_flag_inexact;\r
+ return 0;\r
+ }\r
+ aSig0 |= LIT64( 0x0001000000000000 );\r
+ shiftCount = 0x402F - aExp;\r
+ savedASig = aSig0;\r
+ aSig0 >>= shiftCount;\r
+ z = aSig0;\r
+ if ( aSign ) z = - z;\r
+ if ( ( z < 0 ) ^ aSign ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
+ }\r
+ if ( ( aSig0<<shiftCount ) != savedASig ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the 64-bit two's complement integer format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic---which means in particular that the conversion is rounded\r
+| according to the current rounding mode. If `a' is a NaN, the largest\r
+| positive integer is returned. Otherwise, if the conversion overflows, the\r
+| largest integer with the same sign as `a' is returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 float128_to_int64( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig0, aSig1;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );\r
+ shiftCount = 0x402F - aExp;\r
+ if ( shiftCount <= 0 ) {\r
+ if ( 0x403E < aExp ) {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign\r
+ || ( ( aExp == 0x7FFF )\r
+ && ( aSig1 || ( aSig0 != LIT64( 0x0001000000000000 ) ) )\r
+ )\r
+ ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ shortShift128Left( aSig0, aSig1, - shiftCount, &aSig0, &aSig1 );\r
+ }\r
+ else {\r
+ shift64ExtraRightJamming( aSig0, aSig1, shiftCount, &aSig0, &aSig1 );\r
+ }\r
+ return roundAndPackInt64( aSign, aSig0, aSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the 64-bit two's complement integer format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic, except that the conversion is always rounded toward zero.\r
+| If `a' is a NaN, the largest positive integer is returned. Otherwise, if\r
+| the conversion overflows, the largest integer with the same sign as `a' is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+\r
+int64 float128_to_int64_round_to_zero( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, shiftCount;\r
+ bits64 aSig0, aSig1;\r
+ int64 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );\r
+ shiftCount = aExp - 0x402F;\r
+ if ( 0 < shiftCount ) {\r
+ if ( 0x403E <= aExp ) {\r
+ aSig0 &= LIT64( 0x0000FFFFFFFFFFFF );\r
+ if ( ( a.high == LIT64( 0xC03E000000000000 ) )\r
+ && ( aSig1 < LIT64( 0x0002000000000000 ) ) ) {\r
+ if ( aSig1 ) float_exception_flags |= float_flag_inexact;\r
+ }\r
+ else {\r
+ float_raise( float_flag_invalid );\r
+ if ( ! aSign || ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) ) {\r
+ return LIT64( 0x7FFFFFFFFFFFFFFF );\r
+ }\r
+ }\r
+ return (sbits64) LIT64( 0x8000000000000000 );\r
+ }\r
+ z = ( aSig0<<shiftCount ) | ( aSig1>>( ( - shiftCount ) & 63 ) );\r
+ if ( (bits64) ( aSig1<<shiftCount ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ }\r
+ else {\r
+ if ( aExp < 0x3FFF ) {\r
+ if ( aExp | aSig0 | aSig1 ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return 0;\r
+ }\r
+ z = aSig0>>( - shiftCount );\r
+ if ( aSig1\r
+ || ( shiftCount && (bits64) ( aSig0<<( shiftCount & 63 ) ) ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ }\r
+ if ( aSign ) z = - z;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the single-precision floating-point format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float32 float128_to_float32( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 aSig0, aSig1;\r
+ bits32 zSig;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) {\r
+ return commonNaNToFloat32( float128ToCommonNaN( a ) );\r
+ }\r
+ return packFloat32( aSign, 0xFF, 0 );\r
+ }\r
+ aSig0 |= ( aSig1 != 0 );\r
+ shift64RightJamming( aSig0, 18, &aSig0 );\r
+ zSig = aSig0;\r
+ if ( aExp || zSig ) {\r
+ zSig |= 0x40000000;\r
+ aExp -= 0x3F81;\r
+ }\r
+ return roundAndPackFloat32( aSign, aExp, zSig );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the double-precision floating-point format. The conversion\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float64 float128_to_float64( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 aSig0, aSig1;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) {\r
+ return commonNaNToFloat64( float128ToCommonNaN( a ) );\r
+ }\r
+ return packFloat64( aSign, 0x7FF, 0 );\r
+ }\r
+ shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );\r
+ aSig0 |= ( aSig1 != 0 );\r
+ if ( aExp || aSig0 ) {\r
+ aSig0 |= LIT64( 0x4000000000000000 );\r
+ aExp -= 0x3C01;\r
+ }\r
+ return roundAndPackFloat64( aSign, aExp, aSig0 );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point\r
+| value `a' to the extended double-precision floating-point format. The\r
+| conversion is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+floatx80 float128_to_floatx80( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 aSig0, aSig1;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) {\r
+ return commonNaNToFloatx80( float128ToCommonNaN( a ) );\r
+ }\r
+ return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloatx80( aSign, 0, 0 );\r
+ normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ else {\r
+ aSig0 |= LIT64( 0x0001000000000000 );\r
+ }\r
+ shortShift128Left( aSig0, aSig1, 15, &aSig0, &aSig1 );\r
+ return roundAndPackFloatx80( 80, aSign, aExp, aSig0, aSig1 );\r
+\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Rounds the quadruple-precision floating-point value `a' to an integer, and\r
+| returns the result as a quadruple-precision floating-point value. The\r
+| operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_round_to_int( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp;\r
+ bits64 lastBitMask, roundBitsMask;\r
+ int8 roundingMode;\r
+ float128 z;\r
+\r
+ aExp = extractFloat128Exp( a );\r
+ if ( 0x402F <= aExp ) {\r
+ if ( 0x406F <= aExp ) {\r
+ if ( ( aExp == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) )\r
+ ) {\r
+ return propagateFloat128NaN( a, a );\r
+ }\r
+ return a;\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask = ( lastBitMask<<( 0x406E - aExp ) )<<1;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z = a;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ if ( lastBitMask ) {\r
+ add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low );\r
+ if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;\r
+ }\r
+ else {\r
+ if ( (sbits64) z.low < 0 ) {\r
+ ++z.high;\r
+ if ( (bits64) ( z.low<<1 ) == 0 ) z.high &= ~1;\r
+ }\r
+ }\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat128Sign( z )\r
+ ^ ( roundingMode == float_round_up ) ) {\r
+ add128( z.high, z.low, 0, roundBitsMask, &z.high, &z.low );\r
+ }\r
+ }\r
+ z.low &= ~ roundBitsMask;\r
+ }\r
+ else {\r
+ if ( aExp < 0x3FFF ) {\r
+ if ( ( ( (bits64) ( a.high<<1 ) ) | a.low ) == 0 ) return a;\r
+ float_exception_flags |= float_flag_inexact;\r
+ aSign = extractFloat128Sign( a );\r
+ switch ( float_rounding_mode ) {\r
+ case float_round_nearest_even:\r
+ if ( ( aExp == 0x3FFE )\r
+ && ( extractFloat128Frac0( a )\r
+ | extractFloat128Frac1( a ) )\r
+ ) {\r
+ return packFloat128( aSign, 0x3FFF, 0, 0 );\r
+ }\r
+ break;\r
+ case float_round_down:\r
+ return\r
+ aSign ? packFloat128( 1, 0x3FFF, 0, 0 )\r
+ : packFloat128( 0, 0, 0, 0 );\r
+ case float_round_up:\r
+ return\r
+ aSign ? packFloat128( 1, 0, 0, 0 )\r
+ : packFloat128( 0, 0x3FFF, 0, 0 );\r
+ }\r
+ return packFloat128( aSign, 0, 0, 0 );\r
+ }\r
+ lastBitMask = 1;\r
+ lastBitMask <<= 0x402F - aExp;\r
+ roundBitsMask = lastBitMask - 1;\r
+ z.low = 0;\r
+ z.high = a.high;\r
+ roundingMode = float_rounding_mode;\r
+ if ( roundingMode == float_round_nearest_even ) {\r
+ z.high += lastBitMask>>1;\r
+ if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) {\r
+ z.high &= ~ lastBitMask;\r
+ }\r
+ }\r
+ else if ( roundingMode != float_round_to_zero ) {\r
+ if ( extractFloat128Sign( z )\r
+ ^ ( roundingMode == float_round_up ) ) {\r
+ z.high |= ( a.low != 0 );\r
+ z.high += roundBitsMask;\r
+ }\r
+ }\r
+ z.high &= ~ roundBitsMask;\r
+ }\r
+ if ( ( z.low != a.low ) || ( z.high != a.high ) ) {\r
+ float_exception_flags |= float_flag_inexact;\r
+ }\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the quadruple-precision\r
+| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated\r
+| before being returned. `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 addFloat128Sigs( float128 a, float128 b, flag zSign )\r
+{\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\r
+ int32 expDiff;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ bSig1 = extractFloat128Frac1( b );\r
+ bSig0 = extractFloat128Frac0( b );\r
+ bExp = extractFloat128Exp( b );\r
+ expDiff = aExp - bExp;\r
+ if ( 0 < expDiff ) {\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig0 |= LIT64( 0x0001000000000000 );\r
+ }\r
+ shift128ExtraRightJamming(\r
+ bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 );\r
+ zExp = aExp;\r
+ }\r
+ else if ( expDiff < 0 ) {\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
+ return packFloat128( zSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig0 |= LIT64( 0x0001000000000000 );\r
+ }\r
+ shift128ExtraRightJamming(\r
+ aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 );\r
+ zExp = bExp;\r
+ }\r
+ else {\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 | bSig0 | bSig1 ) {\r
+ return propagateFloat128NaN( a, b );\r
+ }\r
+ return a;\r
+ }\r
+ add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
+ if ( aExp == 0 ) return packFloat128( zSign, 0, zSig0, zSig1 );\r
+ zSig2 = 0;\r
+ zSig0 |= LIT64( 0x0002000000000000 );\r
+ zExp = aExp;\r
+ goto shiftRight1;\r
+ }\r
+ aSig0 |= LIT64( 0x0001000000000000 );\r
+ add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
+ --zExp;\r
+ if ( zSig0 < LIT64( 0x0002000000000000 ) ) goto roundAndPack;\r
+ ++zExp;\r
+ shiftRight1:\r
+ shift128ExtraRightJamming(\r
+ zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\r
+ roundAndPack:\r
+ return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the quadruple-\r
+| precision floating-point values `a' and `b'. If `zSign' is 1, the\r
+| difference is negated before being returned. `zSign' is ignored if the\r
+| result is a NaN. The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 subFloat128Sigs( float128 a, float128 b, flag zSign )\r
+{\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;\r
+ int32 expDiff;\r
+ float128 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ bSig1 = extractFloat128Frac1( b );\r
+ bSig0 = extractFloat128Frac0( b );\r
+ bExp = extractFloat128Exp( b );\r
+ expDiff = aExp - bExp;\r
+ shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );\r
+ shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 );\r
+ if ( 0 < expDiff ) goto aExpBigger;\r
+ if ( expDiff < 0 ) goto bExpBigger;\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 | bSig0 | bSig1 ) {\r
+ return propagateFloat128NaN( a, b );\r
+ }\r
+ float_raise( float_flag_invalid );\r
+ z.low = float128_default_nan_low;\r
+ z.high = float128_default_nan_high;\r
+ return z;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ aExp = 1;\r
+ bExp = 1;\r
+ }\r
+ if ( bSig0 < aSig0 ) goto aBigger;\r
+ if ( aSig0 < bSig0 ) goto bBigger;\r
+ if ( bSig1 < aSig1 ) goto aBigger;\r
+ if ( aSig1 < bSig1 ) goto bBigger;\r
+ return packFloat128( float_rounding_mode == float_round_down, 0, 0, 0 );\r
+ bExpBigger:\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
+ return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ ++expDiff;\r
+ }\r
+ else {\r
+ aSig0 |= LIT64( 0x4000000000000000 );\r
+ }\r
+ shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );\r
+ bSig0 |= LIT64( 0x4000000000000000 );\r
+ bBigger:\r
+ sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 );\r
+ zExp = bExp;\r
+ zSign ^= 1;\r
+ goto normalizeRoundAndPack;\r
+ aExpBigger:\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ --expDiff;\r
+ }\r
+ else {\r
+ bSig0 |= LIT64( 0x4000000000000000 );\r
+ }\r
+ shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 );\r
+ aSig0 |= LIT64( 0x4000000000000000 );\r
+ aBigger:\r
+ sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
+ zExp = aExp;\r
+ normalizeRoundAndPack:\r
+ --zExp;\r
+ return normalizeRoundAndPackFloat128( zSign, zExp - 14, zSig0, zSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the quadruple-precision floating-point values\r
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard\r
+| for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_add( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat128Sign( a );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return addFloat128Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return subFloat128Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the quadruple-precision floating-point\r
+| values `a' and `b'. The operation is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_sub( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ aSign = extractFloat128Sign( a );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aSign == bSign ) {\r
+ return subFloat128Sigs( a, b, aSign );\r
+ }\r
+ else {\r
+ return addFloat128Sigs( a, b, aSign );\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of multiplying the quadruple-precision floating-point\r
+| values `a' and `b'. The operation is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_mul( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;\r
+ float128 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ bSig1 = extractFloat128Frac1( b );\r
+ bSig0 = extractFloat128Frac0( b );\r
+ bExp = extractFloat128Exp( b );\r
+ bSign = extractFloat128Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( ( aSig0 | aSig1 )\r
+ || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {\r
+ return propagateFloat128NaN( a, b );\r
+ }\r
+ if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid;\r
+ return packFloat128( zSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
+ if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float128_default_nan_low;\r
+ z.high = float128_default_nan_high;\r
+ return z;\r
+ }\r
+ return packFloat128( zSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\r
+ normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\r
+ normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
+ }\r
+ zExp = aExp + bExp - 0x4000;\r
+ aSig0 |= LIT64( 0x0001000000000000 );\r
+ shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 );\r
+ mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 );\r
+ add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 );\r
+ zSig2 |= ( zSig3 != 0 );\r
+ if ( LIT64( 0x0002000000000000 ) <= zSig0 ) {\r
+ shift128ExtraRightJamming(\r
+ zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\r
+ ++zExp;\r
+ }\r
+ return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of dividing the quadruple-precision floating-point value\r
+| `a' by the corresponding value `b'. The operation is performed according to\r
+| the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_div( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int32 aExp, bExp, zExp;\r
+ bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\r
+ bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
+ float128 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ bSig1 = extractFloat128Frac1( b );\r
+ bSig0 = extractFloat128Frac0( b );\r
+ bExp = extractFloat128Exp( b );\r
+ bSign = extractFloat128Sign( b );\r
+ zSign = aSign ^ bSign;\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
+ goto invalid;\r
+ }\r
+ return packFloat128( zSign, 0x7FFF, 0, 0 );\r
+ }\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
+ return packFloat128( zSign, 0, 0, 0 );\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( ( bSig0 | bSig1 ) == 0 ) {\r
+ if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float128_default_nan_low;\r
+ z.high = float128_default_nan_high;\r
+ return z;\r
+ }\r
+ float_raise( float_flag_divbyzero );\r
+ return packFloat128( zSign, 0x7FFF, 0, 0 );\r
+ }\r
+ normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\r
+ normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ zExp = aExp - bExp + 0x3FFD;\r
+ shortShift128Left(\r
+ aSig0 | LIT64( 0x0001000000000000 ), aSig1, 15, &aSig0, &aSig1 );\r
+ shortShift128Left(\r
+ bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );\r
+ if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) {\r
+ shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 );\r
+ ++zExp;\r
+ }\r
+ zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 );\r
+ mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 );\r
+ sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 );\r
+ while ( (sbits64) rem0 < 0 ) {\r
+ --zSig0;\r
+ add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 );\r
+ }\r
+ zSig1 = estimateDiv128To64( rem1, rem2, bSig0 );\r
+ if ( ( zSig1 & 0x3FFF ) <= 4 ) {\r
+ mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 );\r
+ sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 );\r
+ while ( (sbits64) rem1 < 0 ) {\r
+ --zSig1;\r
+ add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 );\r
+ }\r
+ zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
+ }\r
+ shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 );\r
+ return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the remainder of the quadruple-precision floating-point value `a'\r
+| with respect to the corresponding value `b'. The operation is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_rem( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign, zSign;\r
+ int32 aExp, bExp, expDiff;\r
+ bits64 aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2;\r
+ bits64 allZero, alternateASig0, alternateASig1, sigMean1;\r
+ sbits64 sigMean0;\r
+ float128 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ bSig1 = extractFloat128Frac1( b );\r
+ bSig0 = extractFloat128Frac0( b );\r
+ bExp = extractFloat128Exp( b );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( ( aSig0 | aSig1 )\r
+ || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {\r
+ return propagateFloat128NaN( a, b );\r
+ }\r
+ goto invalid;\r
+ }\r
+ if ( bExp == 0x7FFF ) {\r
+ if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
+ return a;\r
+ }\r
+ if ( bExp == 0 ) {\r
+ if ( ( bSig0 | bSig1 ) == 0 ) {\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float128_default_nan_low;\r
+ z.high = float128_default_nan_high;\r
+ return z;\r
+ }\r
+ normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return a;\r
+ normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ expDiff = aExp - bExp;\r
+ if ( expDiff < -1 ) return a;\r
+ shortShift128Left(\r
+ aSig0 | LIT64( 0x0001000000000000 ),\r
+ aSig1,\r
+ 15 - ( expDiff < 0 ),\r
+ &aSig0,\r
+ &aSig1\r
+ );\r
+ shortShift128Left(\r
+ bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );\r
+ q = le128( bSig0, bSig1, aSig0, aSig1 );\r
+ if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );\r
+ expDiff -= 64;\r
+ while ( 0 < expDiff ) {\r
+ q = estimateDiv128To64( aSig0, aSig1, bSig0 );\r
+ q = ( 4 < q ) ? q - 4 : 0;\r
+ mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );\r
+ shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZero );\r
+ shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero );\r
+ sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 );\r
+ expDiff -= 61;\r
+ }\r
+ if ( -64 < expDiff ) {\r
+ q = estimateDiv128To64( aSig0, aSig1, bSig0 );\r
+ q = ( 4 < q ) ? q - 4 : 0;\r
+ q >>= - expDiff;\r
+ shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );\r
+ expDiff += 52;\r
+ if ( expDiff < 0 ) {\r
+ shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );\r
+ }\r
+ else {\r
+ shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 );\r
+ }\r
+ mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );\r
+ sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 );\r
+ }\r
+ else {\r
+ shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 );\r
+ shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );\r
+ }\r
+ do {\r
+ alternateASig0 = aSig0;\r
+ alternateASig1 = aSig1;\r
+ ++q;\r
+ sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );\r
+ } while ( 0 <= (sbits64) aSig0 );\r
+ add128(\r
+ aSig0, aSig1, alternateASig0, alternateASig1, &sigMean0, &sigMean1 );\r
+ if ( ( sigMean0 < 0 )\r
+ || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) {\r
+ aSig0 = alternateASig0;\r
+ aSig1 = alternateASig1;\r
+ }\r
+ zSign = ( (sbits64) aSig0 < 0 );\r
+ if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 );\r
+ return\r
+ normalizeRoundAndPackFloat128( aSign ^ zSign, bExp - 4, aSig0, aSig1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the square root of the quadruple-precision floating-point value `a'.\r
+| The operation is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+float128 float128_sqrt( float128 a )\r
+{\r
+ flag aSign;\r
+ int32 aExp, zExp;\r
+ bits64 aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0;\r
+ bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
+ float128 z;\r
+\r
+ aSig1 = extractFloat128Frac1( a );\r
+ aSig0 = extractFloat128Frac0( a );\r
+ aExp = extractFloat128Exp( a );\r
+ aSign = extractFloat128Sign( a );\r
+ if ( aExp == 0x7FFF ) {\r
+ if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, a );\r
+ if ( ! aSign ) return a;\r
+ goto invalid;\r
+ }\r
+ if ( aSign ) {\r
+ if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;\r
+ invalid:\r
+ float_raise( float_flag_invalid );\r
+ z.low = float128_default_nan_low;\r
+ z.high = float128_default_nan_high;\r
+ return z;\r
+ }\r
+ if ( aExp == 0 ) {\r
+ if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );\r
+ normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
+ }\r
+ zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE;\r
+ aSig0 |= LIT64( 0x0001000000000000 );\r
+ zSig0 = estimateSqrt32( aExp, aSig0>>17 );\r
+ shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 );\r
+ zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );\r
+ doubleZSig0 = zSig0<<1;\r
+ mul64To128( zSig0, zSig0, &term0, &term1 );\r
+ sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );\r
+ while ( (sbits64) rem0 < 0 ) {\r
+ --zSig0;\r
+ doubleZSig0 -= 2;\r
+ add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 );\r
+ }\r
+ zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 );\r
+ if ( ( zSig1 & 0x1FFF ) <= 5 ) {\r
+ if ( zSig1 == 0 ) zSig1 = 1;\r
+ mul64To128( doubleZSig0, zSig1, &term1, &term2 );\r
+ sub128( rem1, 0, term1, term2, &rem1, &rem2 );\r
+ mul64To128( zSig1, zSig1, &term2, &term3 );\r
+ sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );\r
+ while ( (sbits64) rem1 < 0 ) {\r
+ --zSig1;\r
+ shortShift128Left( 0, zSig1, 1, &term2, &term3 );\r
+ term3 |= 1;\r
+ term2 |= doubleZSig0;\r
+ add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );\r
+ }\r
+ zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
+ }\r
+ shift128ExtraRightJamming( zSig0, zSig1, 0, 14, &zSig0, &zSig1, &zSig2 );\r
+ return roundAndPackFloat128( 0, zExp, zSig0, zSig1, zSig2 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_eq( float128 a, float128 b )\r
+{\r
+\r
+ if ( ( ( extractFloat128Exp( a ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
+ || ( ( extractFloat128Exp( b ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
+ ) {\r
+ if ( float128_is_signaling_nan( a )\r
+ || float128_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ return\r
+ ( a.low == b.low )\r
+ && ( ( a.high == b.high )\r
+ || ( ( a.low == 0 )\r
+ && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )\r
+ );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
+| or equal to the corresponding value `b', and 0 otherwise. The comparison\r
+| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
+| Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_le( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat128Exp( a ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
+ || ( ( extractFloat128Exp( b ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat128Sign( a );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ || ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ == 0 );\r
+ }\r
+ return\r
+ aSign ? le128( b.high, b.low, a.high, a.low )\r
+ : le128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. The comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_lt( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat128Exp( a ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
+ || ( ( extractFloat128Exp( b ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ aSign = extractFloat128Sign( a );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ && ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ != 0 );\r
+ }\r
+ return\r
+ aSign ? lt128( b.high, b.low, a.high, a.low )\r
+ : lt128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is equal to\r
+| the corresponding value `b', and 0 otherwise. The invalid exception is\r
+| raised if either operand is a NaN. Otherwise, the comparison is performed\r
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_eq_signaling( float128 a, float128 b )\r
+{\r
+\r
+ if ( ( ( extractFloat128Exp( a ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
+ || ( ( extractFloat128Exp( b ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
+ ) {\r
+ float_raise( float_flag_invalid );\r
+ return 0;\r
+ }\r
+ return\r
+ ( a.low == b.low )\r
+ && ( ( a.high == b.high )\r
+ || ( ( a.low == 0 )\r
+ && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )\r
+ );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
+| or equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not\r
+| cause an exception. Otherwise, the comparison is performed according to the\r
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_le_quiet( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat128Exp( a ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
+ || ( ( extractFloat128Exp( b ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
+ ) {\r
+ if ( float128_is_signaling_nan( a )\r
+ || float128_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat128Sign( a );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ || ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ == 0 );\r
+ }\r
+ return\r
+ aSign ? le128( b.high, b.low, a.high, a.low )\r
+ : le128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an\r
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_lt_quiet( float128 a, float128 b )\r
+{\r
+ flag aSign, bSign;\r
+\r
+ if ( ( ( extractFloat128Exp( a ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
+ || ( ( extractFloat128Exp( b ) == 0x7FFF )\r
+ && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
+ ) {\r
+ if ( float128_is_signaling_nan( a )\r
+ || float128_is_signaling_nan( b ) ) {\r
+ float_raise( float_flag_invalid );\r
+ }\r
+ return 0;\r
+ }\r
+ aSign = extractFloat128Sign( a );\r
+ bSign = extractFloat128Sign( b );\r
+ if ( aSign != bSign ) {\r
+ return\r
+ aSign\r
+ && ( ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
+ != 0 );\r
+ }\r
+ return\r
+ aSign ? lt128( b.high, b.low, a.high, a.low )\r
+ : lt128( a.high, a.low, b.high, b.low );\r
+\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Include common integer types and flags.\r
+*----------------------------------------------------------------------------*/\r
+#include "../../../processors/!!!processor.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Symbolic Boolean literals.\r
+*----------------------------------------------------------------------------*/\r
+enum {\r
+ FALSE = 0,\r
+ TRUE = 1\r
+};\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Underflow tininess-detection mode, statically initialized to default value.\r
+| (The declaration in `softfloat.h' must match the `int8' type here.)\r
+*----------------------------------------------------------------------------*/\r
+int8 float_detect_tininess = float_tininess_after_rounding;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Raises the exceptions specified by `flags'. Floating-point traps can be\r
+| defined here if desired. It is currently not possible for such a trap to\r
+| substitute a result value. If traps are not implemented, this routine\r
+| should be simply `float_exception_flags |= flags;'.\r
+*----------------------------------------------------------------------------*/\r
+\r
+void float_raise( int8 flags )\r
+{\r
+\r
+ float_exception_flags |= flags;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Internal canonical NaN format.\r
+*----------------------------------------------------------------------------*/\r
+typedef struct {\r
+ flag sign;\r
+ bits64 high, low;\r
+} commonNaNT;\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define float32_default_nan 0xFFFFFFFF\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_nan( float32 a )\r
+{\r
+\r
+ return ( 0xFF000000 < (bits32) ( a<<1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float32_is_signaling_nan( float32 a )\r
+{\r
+\r
+ return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float32ToCommonNaN( float32 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a>>31;\r
+ z.low = 0;\r
+ z.high = ( (bits64) a )<<41;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the single-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 commonNaNToFloat32( commonNaNT a )\r
+{\r
+\r
+ return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float32 propagateFloat32NaN( float32 a, float32 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float32_is_nan( a );\r
+ aIsSignalingNaN = float32_is_signaling_nan( a );\r
+ bIsNaN = float32_is_nan( b );\r
+ bIsSignalingNaN = float32_is_signaling_nan( b );\r
+ a |= 0x00400000;\r
+ b |= 0x00400000;\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsNaN ) {\r
+ return ( aIsSignalingNaN & bIsNaN ) ? b : a;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define float64_default_nan LIT64( 0xFFFFFFFFFFFFFFFF )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_nan( float64 a )\r
+{\r
+\r
+ return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a signaling\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_signaling_nan( float64 a )\r
+{\r
+\r
+ return\r
+ ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )\r
+ && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float64ToCommonNaN( float64 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a>>63;\r
+ z.low = 0;\r
+ z.high = a<<12;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the double-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 commonNaNToFloat64( commonNaNT a )\r
+{\r
+\r
+ return\r
+ ( ( (bits64) a.sign )<<63 )\r
+ | LIT64( 0x7FF8000000000000 )\r
+ | ( a.high>>12 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 propagateFloat64NaN( float64 a, float64 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float64_is_nan( a );\r
+ aIsSignalingNaN = float64_is_signaling_nan( a );\r
+ bIsNaN = float64_is_nan( b );\r
+ bIsSignalingNaN = float64_is_signaling_nan( b );\r
+ a |= LIT64( 0x0008000000000000 );\r
+ b |= LIT64( 0x0008000000000000 );\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsNaN ) {\r
+ return ( aIsSignalingNaN & bIsNaN ) ? b : a;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated extended double-precision NaN. The\r
+| `high' and `low' values hold the most- and least-significant bits,\r
+| respectively.\r
+*----------------------------------------------------------------------------*/\r
+#define floatx80_default_nan_high 0xFFFF\r
+#define floatx80_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is a\r
+| NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_is_nan( floatx80 a )\r
+{\r
+\r
+ return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is a\r
+| signaling NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_is_signaling_nan( floatx80 a )\r
+{\r
+ bits64 aLow;\r
+\r
+ aLow = a.low & ~ LIT64( 0x4000000000000000 );\r
+ return\r
+ ( ( a.high & 0x7FFF ) == 0x7FFF )\r
+ && (bits64) ( aLow<<1 )\r
+ && ( a.low == aLow );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the\r
+| invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT floatx80ToCommonNaN( floatx80 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a.high>>15;\r
+ z.low = 0;\r
+ z.high = a.low<<1;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the extended\r
+| double-precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 commonNaNToFloatx80( commonNaNT a )\r
+{\r
+ floatx80 z;\r
+\r
+ z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );\r
+ z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two extended double-precision floating-point values `a' and `b', one\r
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or\r
+| `b' is a signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = floatx80_is_nan( a );\r
+ aIsSignalingNaN = floatx80_is_signaling_nan( a );\r
+ bIsNaN = floatx80_is_nan( b );\r
+ bIsSignalingNaN = floatx80_is_signaling_nan( b );\r
+ a.low |= LIT64( 0xC000000000000000 );\r
+ b.low |= LIT64( 0xC000000000000000 );\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsNaN ) {\r
+ return ( aIsSignalingNaN & bIsNaN ) ? b : a;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated quadruple-precision NaN. The `high' and\r
+| `low' values hold the most- and least-significant bits, respectively.\r
+*----------------------------------------------------------------------------*/\r
+#define float128_default_nan_high LIT64( 0xFFFFFFFFFFFFFFFF )\r
+#define float128_default_nan_low LIT64( 0xFFFFFFFFFFFFFFFF )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;\r
+| otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_is_nan( float128 a )\r
+{\r
+\r
+ return\r
+ ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )\r
+ && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is a\r
+| signaling NaN; otherwise returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_is_signaling_nan( float128 a )\r
+{\r
+\r
+ return\r
+ ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )\r
+ && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point NaN\r
+| `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float128ToCommonNaN( float128 a )\r
+{\r
+ commonNaNT z;\r
+\r
+ if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+ z.sign = a.high>>63;\r
+ shortShift128Left( a.high, a.low, 16, &z.high, &z.low );\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the quadruple-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 commonNaNToFloat128( commonNaNT a )\r
+{\r
+ float128 z;\r
+\r
+ shift128Right( a.high, a.low, 16, &z.high, &z.low );\r
+ z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );\r
+ return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two quadruple-precision floating-point values `a' and `b', one of\r
+| which is a NaN, and returns the appropriate NaN result. If either `a' or\r
+| `b' is a signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 propagateFloat128NaN( float128 a, float128 b )\r
+{\r
+ flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+ aIsNaN = float128_is_nan( a );\r
+ aIsSignalingNaN = float128_is_signaling_nan( a );\r
+ bIsNaN = float128_is_nan( b );\r
+ bIsSignalingNaN = float128_is_signaling_nan( b );\r
+ a.high |= LIT64( 0x0000800000000000 );\r
+ b.high |= LIT64( 0x0000800000000000 );\r
+ if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+ if ( aIsNaN ) {\r
+ return ( aIsSignalingNaN & bIsNaN ) ? b : a;\r
+ }\r
+ else {\r
+ return b;\r
+ }\r
+\r
+}\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser. This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704. Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980. The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek. More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| The macro `FLOATX80' must be defined to enable the extended double-precision\r
+| floating-point format `floatx80'. If this macro is not defined, the\r
+| `floatx80' type will not be defined, and none of the functions that either\r
+| input or output the `floatx80' type will be defined. The same applies to\r
+| the `FLOAT128' macro and the quadruple-precision format `float128'.\r
+*----------------------------------------------------------------------------*/\r
+#define FLOATX80\r
+#define FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point types.\r
+*----------------------------------------------------------------------------*/\r
+typedef !!!bits32 float32;\r
+typedef !!!bits64 float64;\r
+#ifdef FLOATX80\r
+typedef struct {\r
+ !!!bits16 high;\r
+ !!!bits64 low;\r
+} floatx80;\r
+#endif\r
+#ifdef FLOAT128\r
+typedef struct {\r
+ !!!bits64 high, low;\r
+} float128;\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point underflow tininess-detection mode.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 float_detect_tininess;\r
+enum {\r
+ float_tininess_after_rounding = 0,\r
+ float_tininess_before_rounding = 1\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point rounding mode.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 float_rounding_mode;\r
+enum {\r
+ float_round_nearest_even = 0,\r
+ float_round_to_zero = 1,\r
+ float_round_down = 2,\r
+ float_round_up = 3\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE floating-point exception flags.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 float_exception_flags;\r
+enum {\r
+ float_flag_inexact = 1,\r
+ float_flag_underflow = 2,\r
+ float_flag_overflow = 4,\r
+ float_flag_divbyzero = 8,\r
+ float_flag_invalid = 16\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Routine to raise any or all of the software IEC/IEEE floating-point\r
+| exception flags.\r
+*----------------------------------------------------------------------------*/\r
+void float_raise( !!!int8 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE integer-to-floating-point conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+float32 int32_to_float32( !!!int32 );\r
+float64 int32_to_float64( !!!int32 );\r
+#ifdef FLOATX80\r
+floatx80 int32_to_floatx80( !!!int32 );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 int32_to_float128( !!!int32 );\r
+#endif\r
+float32 int64_to_float32( !!!int64 );\r
+float64 int64_to_float64( !!!int64 );\r
+#ifdef FLOATX80\r
+floatx80 int64_to_floatx80( !!!int64 );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 int64_to_float128( !!!int64 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+!!!int32 float32_to_int32( float32 );\r
+!!!int32 float32_to_int32_round_to_zero( float32 );\r
+!!!int64 float32_to_int64( float32 );\r
+!!!int64 float32_to_int64_round_to_zero( float32 );\r
+float64 float32_to_float64( float32 );\r
+#ifdef FLOATX80\r
+floatx80 float32_to_floatx80( float32 );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 float32_to_float128( float32 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE single-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float32 float32_round_to_int( float32 );\r
+float32 float32_add( float32, float32 );\r
+float32 float32_sub( float32, float32 );\r
+float32 float32_mul( float32, float32 );\r
+float32 float32_div( float32, float32 );\r
+float32 float32_rem( float32, float32 );\r
+float32 float32_sqrt( float32 );\r
+!!!flag float32_eq( float32, float32 );\r
+!!!flag float32_le( float32, float32 );\r
+!!!flag float32_lt( float32, float32 );\r
+!!!flag float32_eq_signaling( float32, float32 );\r
+!!!flag float32_le_quiet( float32, float32 );\r
+!!!flag float32_lt_quiet( float32, float32 );\r
+!!!flag float32_is_signaling_nan( float32 );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+!!!int32 float64_to_int32( float64 );\r
+!!!int32 float64_to_int32_round_to_zero( float64 );\r
+!!!int64 float64_to_int64( float64 );\r
+!!!int64 float64_to_int64_round_to_zero( float64 );\r
+float32 float64_to_float32( float64 );\r
+#ifdef FLOATX80\r
+floatx80 float64_to_floatx80( float64 );\r
+#endif\r
+#ifdef FLOAT128\r
+float128 float64_to_float128( float64 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE double-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float64 float64_round_to_int( float64 );\r
+float64 float64_add( float64, float64 );\r
+float64 float64_sub( float64, float64 );\r
+float64 float64_mul( float64, float64 );\r
+float64 float64_div( float64, float64 );\r
+float64 float64_rem( float64, float64 );\r
+float64 float64_sqrt( float64 );\r
+!!!flag float64_eq( float64, float64 );\r
+!!!flag float64_le( float64, float64 );\r
+!!!flag float64_lt( float64, float64 );\r
+!!!flag float64_eq_signaling( float64, float64 );\r
+!!!flag float64_le_quiet( float64, float64 );\r
+!!!flag float64_lt_quiet( float64, float64 );\r
+!!!flag float64_is_signaling_nan( float64 );\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE extended double-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+!!!int32 floatx80_to_int32( floatx80 );\r
+!!!int32 floatx80_to_int32_round_to_zero( floatx80 );\r
+!!!int64 floatx80_to_int64( floatx80 );\r
+!!!int64 floatx80_to_int64_round_to_zero( floatx80 );\r
+float32 floatx80_to_float32( floatx80 );\r
+float64 floatx80_to_float64( floatx80 );\r
+#ifdef FLOAT128\r
+float128 floatx80_to_float128( floatx80 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE extended double-precision rounding precision. Valid\r
+| values are 32, 64, and 80.\r
+*----------------------------------------------------------------------------*/\r
+extern !!!int8 floatx80_rounding_precision;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE extended double-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+floatx80 floatx80_round_to_int( floatx80 );\r
+floatx80 floatx80_add( floatx80, floatx80 );\r
+floatx80 floatx80_sub( floatx80, floatx80 );\r
+floatx80 floatx80_mul( floatx80, floatx80 );\r
+floatx80 floatx80_div( floatx80, floatx80 );\r
+floatx80 floatx80_rem( floatx80, floatx80 );\r
+floatx80 floatx80_sqrt( floatx80 );\r
+!!!flag floatx80_eq( floatx80, floatx80 );\r
+!!!flag floatx80_le( floatx80, floatx80 );\r
+!!!flag floatx80_lt( floatx80, floatx80 );\r
+!!!flag floatx80_eq_signaling( floatx80, floatx80 );\r
+!!!flag floatx80_le_quiet( floatx80, floatx80 );\r
+!!!flag floatx80_lt_quiet( floatx80, floatx80 );\r
+!!!flag floatx80_is_signaling_nan( floatx80 );\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE quadruple-precision conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+!!!int32 float128_to_int32( float128 );\r
+!!!int32 float128_to_int32_round_to_zero( float128 );\r
+!!!int64 float128_to_int64( float128 );\r
+!!!int64 float128_to_int64_round_to_zero( float128 );\r
+float32 float128_to_float32( float128 );\r
+float64 float128_to_float64( float128 );\r
+#ifdef FLOATX80\r
+floatx80 float128_to_floatx80( float128 );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software IEC/IEEE quadruple-precision operations.\r
+*----------------------------------------------------------------------------*/\r
+float128 float128_round_to_int( float128 );\r
+float128 float128_add( float128, float128 );\r
+float128 float128_sub( float128, float128 );\r
+float128 float128_mul( float128, float128 );\r
+float128 float128_div( float128, float128 );\r
+float128 float128_rem( float128, float128 );\r
+float128 float128_sqrt( float128 );\r
+!!!flag float128_eq( float128, float128 );\r
+!!!flag float128_le( float128, float128 );\r
+!!!flag float128_lt( float128, float128 );\r
+!!!flag float128_eq_signaling( float128, float128 );\r
+!!!flag float128_le_quiet( float128, float128 );\r
+!!!flag float128_lt_quiet( float128, float128 );\r
+!!!flag float128_is_signaling_nan( float128 );\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+/*============================================================================\r
+\r
+This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY THE AUTHOR, JOHN HAUSER, (possibly via similar legal\r
+warning) AGAINST ALL LOSSES, COSTS, OR OTHER PROBLEMS INCURRED BY THEIR\r
+CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include <stdlib.h>\r
+#include <stdarg.h>\r
+#include <string.h>\r
+#include <stdio.h>\r
+#include <time.h>\r
+#include "milieu.h"\r
+#include "softfloat.h"\r
+\r
+enum {\r
+ minIterations = 1000\r
+};\r
+\r
+static void fail( const char *message, ... )\r
+{\r
+ va_list varArgs;\r
+\r
+ fputs( "timesoftfloat: ", stderr );\r
+ va_start( varArgs, message );\r
+ vfprintf( stderr, message, varArgs );\r
+ va_end( varArgs );\r
+ fputs( ".\n", stderr );\r
+ exit( EXIT_FAILURE );\r
+\r
+}\r
+\r
+static char *functionName;\r
+static char *roundingPrecisionName, *roundingModeName, *tininessModeName;\r
+\r
+static void reportTime( int32 count, long clocks )\r
+{\r
+\r
+ printf(\r
+ "%8.1f kops/s: %s",\r
+ ( count / ( ( (float) clocks ) / CLOCKS_PER_SEC ) ) / 1000,\r
+ functionName\r
+ );\r
+ if ( roundingModeName ) {\r
+ if ( roundingPrecisionName ) {\r
+ fputs( ", precision ", stdout );\r
+ fputs( roundingPrecisionName, stdout );\r
+ }\r
+ fputs( ", rounding ", stdout );\r
+ fputs( roundingModeName, stdout );\r
+ if ( tininessModeName ) {\r
+ fputs( ", tininess ", stdout );\r
+ fputs( tininessModeName, stdout );\r
+ fputs( " rounding", stdout );\r
+ }\r
+ }\r
+ fputc( '\n', stdout );\r
+\r
+}\r
+\r
+enum {\r
+ numInputs_int32 = 32\r
+};\r
+\r
+static const int32 inputs_int32[ numInputs_int32 ] = {\r
+ 0xFFFFBB79, 0x405CF80F, 0x00000000, 0xFFFFFD04,\r
+ 0xFFF20002, 0x0C8EF795, 0xF00011FF, 0x000006CA,\r
+ 0x00009BFE, 0xFF4862E3, 0x9FFFEFFE, 0xFFFFFFB7,\r
+ 0x0BFF7FFF, 0x0000F37A, 0x0011DFFE, 0x00000006,\r
+ 0xFFF02006, 0xFFFFF7D1, 0x10200003, 0xDE8DF765,\r
+ 0x00003E02, 0x000019E8, 0x0008FFFE, 0xFFFFFB5C,\r
+ 0xFFDF7FFE, 0x07C42FBF, 0x0FFFE3FF, 0x040B9F13,\r
+ 0xBFFFFFF8, 0x0001BF56, 0x000017F6, 0x000A908A\r
+};\r
+\r
+static void time_a_int32_z_float32( float32 function( int32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_int32_z_float64( float64 function( int32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+static void time_a_int32_z_floatx80( floatx80 function( int32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+static void time_a_int32_z_float128( float128 function( int32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+enum {\r
+ numInputs_int64 = 32\r
+};\r
+\r
+static const int64 inputs_int64[ numInputs_int64 ] = {\r
+ LIT64( 0xFBFFC3FFFFFFFFFF ),\r
+ LIT64( 0x0000000003C589BC ),\r
+ LIT64( 0x00000000400013FE ),\r
+ LIT64( 0x0000000000186171 ),\r
+ LIT64( 0xFFFFFFFFFFFEFBFA ),\r
+ LIT64( 0xFFFFFD79E6DFFC73 ),\r
+ LIT64( 0x0000000010001DFF ),\r
+ LIT64( 0xDD1A0F0C78513710 ),\r
+ LIT64( 0xFFFF83FFFFFEFFFE ),\r
+ LIT64( 0x00756EBD1AD0C1C7 ),\r
+ LIT64( 0x0003FDFFFFFFFFBE ),\r
+ LIT64( 0x0007D0FB2C2CA951 ),\r
+ LIT64( 0x0007FC0007FFFFFE ),\r
+ LIT64( 0x0000001F942B18BB ),\r
+ LIT64( 0x0000080101FFFFFE ),\r
+ LIT64( 0xFFFFFFFFFFFF0978 ),\r
+ LIT64( 0x000000000008BFFF ),\r
+ LIT64( 0x0000000006F5AF08 ),\r
+ LIT64( 0xFFDEFF7FFFFFFFFE ),\r
+ LIT64( 0x0000000000000003 ),\r
+ LIT64( 0x3FFFFFFFFF80007D ),\r
+ LIT64( 0x0000000000000078 ),\r
+ LIT64( 0xFFF80000007FDFFD ),\r
+ LIT64( 0x1BBC775B78016AB0 ),\r
+ LIT64( 0xFFF9001FFFFFFFFE ),\r
+ LIT64( 0xFFFD4767AB98E43F ),\r
+ LIT64( 0xFFFFFEFFFE00001E ),\r
+ LIT64( 0xFFFFFFFFFFF04EFD ),\r
+ LIT64( 0x07FFFFFFFFFFF7FF ),\r
+ LIT64( 0xFFFC9EAA38F89050 ),\r
+ LIT64( 0x00000020FBFFFFFE ),\r
+ LIT64( 0x0000099AE6455357 )\r
+};\r
+\r
+static void time_a_int64_z_float32( float32 function( int64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_int64_z_float64( float64 function( int64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+static void time_a_int64_z_floatx80( floatx80 function( int64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+static void time_a_int64_z_float128( float128 function( int64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_int64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_int64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+enum {\r
+ numInputs_float32 = 32\r
+};\r
+\r
+static const float32 inputs_float32[ numInputs_float32 ] = {\r
+ 0x4EFA0000, 0xC1D0B328, 0x80000000, 0x3E69A31E,\r
+ 0xAF803EFF, 0x3F800000, 0x17BF8000, 0xE74A301A,\r
+ 0x4E010003, 0x7EE3C75D, 0xBD803FE0, 0xBFFEFF00,\r
+ 0x7981F800, 0x431FFFFC, 0xC100C000, 0x3D87EFFF,\r
+ 0x4103FEFE, 0xBC000007, 0xBF01F7FF, 0x4E6C6B5C,\r
+ 0xC187FFFE, 0xC58B9F13, 0x4F88007F, 0xDF004007,\r
+ 0xB7FFD7FE, 0x7E8001FB, 0x46EFFBFF, 0x31C10000,\r
+ 0xDB428661, 0x33F89B1F, 0xA3BFEFFF, 0x537BFFBE\r
+};\r
+\r
+static void time_a_float32_z_int32( int32 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float32_z_int64( int64 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float32_z_float64( float64 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+static void time_a_float32_z_floatx80( floatx80 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+static void time_a_float32_z_float128( float128 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+static void time_az_float32( float32 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_ab_float32_z_flag( flag function( float32, float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_abz_float32( float32 function( float32, float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function(\r
+ inputs_float32[ inputNumA ], inputs_float32[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float32 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static const float32 inputs_float32_pos[ numInputs_float32 ] = {\r
+ 0x4EFA0000, 0x41D0B328, 0x00000000, 0x3E69A31E,\r
+ 0x2F803EFF, 0x3F800000, 0x17BF8000, 0x674A301A,\r
+ 0x4E010003, 0x7EE3C75D, 0x3D803FE0, 0x3FFEFF00,\r
+ 0x7981F800, 0x431FFFFC, 0x4100C000, 0x3D87EFFF,\r
+ 0x4103FEFE, 0x3C000007, 0x3F01F7FF, 0x4E6C6B5C,\r
+ 0x4187FFFE, 0x458B9F13, 0x4F88007F, 0x5F004007,\r
+ 0x37FFD7FE, 0x7E8001FB, 0x46EFFBFF, 0x31C10000,\r
+ 0x5B428661, 0x33F89B1F, 0x23BFEFFF, 0x537BFFBE\r
+};\r
+\r
+static void time_az_float32_pos( float32 function( float32 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float32_pos[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float32_pos[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float32 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+enum {\r
+ numInputs_float64 = 32\r
+};\r
+\r
+static const float64 inputs_float64[ numInputs_float64 ] = {\r
+ LIT64( 0x422FFFC008000000 ),\r
+ LIT64( 0xB7E0000480000000 ),\r
+ LIT64( 0xF3FD2546120B7935 ),\r
+ LIT64( 0x3FF0000000000000 ),\r
+ LIT64( 0xCE07F766F09588D6 ),\r
+ LIT64( 0x8000000000000000 ),\r
+ LIT64( 0x3FCE000400000000 ),\r
+ LIT64( 0x8313B60F0032BED8 ),\r
+ LIT64( 0xC1EFFFFFC0002000 ),\r
+ LIT64( 0x3FB3C75D224F2B0F ),\r
+ LIT64( 0x7FD00000004000FF ),\r
+ LIT64( 0xA12FFF8000001FFF ),\r
+ LIT64( 0x3EE0000000FE0000 ),\r
+ LIT64( 0x0010000080000004 ),\r
+ LIT64( 0x41CFFFFE00000020 ),\r
+ LIT64( 0x40303FFFFFFFFFFD ),\r
+ LIT64( 0x3FD000003FEFFFFF ),\r
+ LIT64( 0xBFD0000010000000 ),\r
+ LIT64( 0xB7FC6B5C16CA55CF ),\r
+ LIT64( 0x413EEB940B9D1301 ),\r
+ LIT64( 0xC7E00200001FFFFF ),\r
+ LIT64( 0x47F00021FFFFFFFE ),\r
+ LIT64( 0xBFFFFFFFF80000FF ),\r
+ LIT64( 0xC07FFFFFE00FFFFF ),\r
+ LIT64( 0x001497A63740C5E8 ),\r
+ LIT64( 0xC4BFFFE0001FFFFF ),\r
+ LIT64( 0x96FFDFFEFFFFFFFF ),\r
+ LIT64( 0x403FC000000001FE ),\r
+ LIT64( 0xFFD00000000001F6 ),\r
+ LIT64( 0x0640400002000000 ),\r
+ LIT64( 0x479CEE1E4F789FE0 ),\r
+ LIT64( 0xC237FFFFFFFFFDFE )\r
+};\r
+\r
+static void time_a_float64_z_int32( int32 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float64_z_int64( int64 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float64_z_float32( float32 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+static void time_a_float64_z_floatx80( floatx80 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+static void time_a_float64_z_float128( float128 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+static void time_az_float64( float64 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_ab_float64_z_flag( flag function( float64, float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function(\r
+ inputs_float64[ inputNumA ], inputs_float64[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function(\r
+ inputs_float64[ inputNumA ], inputs_float64[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_abz_float64( float64 function( float64, float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function(\r
+ inputs_float64[ inputNumA ], inputs_float64[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function(\r
+ inputs_float64[ inputNumA ], inputs_float64[ inputNumB ] );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float64 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static const float64 inputs_float64_pos[ numInputs_float64 ] = {\r
+ LIT64( 0x422FFFC008000000 ),\r
+ LIT64( 0x37E0000480000000 ),\r
+ LIT64( 0x73FD2546120B7935 ),\r
+ LIT64( 0x3FF0000000000000 ),\r
+ LIT64( 0x4E07F766F09588D6 ),\r
+ LIT64( 0x0000000000000000 ),\r
+ LIT64( 0x3FCE000400000000 ),\r
+ LIT64( 0x0313B60F0032BED8 ),\r
+ LIT64( 0x41EFFFFFC0002000 ),\r
+ LIT64( 0x3FB3C75D224F2B0F ),\r
+ LIT64( 0x7FD00000004000FF ),\r
+ LIT64( 0x212FFF8000001FFF ),\r
+ LIT64( 0x3EE0000000FE0000 ),\r
+ LIT64( 0x0010000080000004 ),\r
+ LIT64( 0x41CFFFFE00000020 ),\r
+ LIT64( 0x40303FFFFFFFFFFD ),\r
+ LIT64( 0x3FD000003FEFFFFF ),\r
+ LIT64( 0x3FD0000010000000 ),\r
+ LIT64( 0x37FC6B5C16CA55CF ),\r
+ LIT64( 0x413EEB940B9D1301 ),\r
+ LIT64( 0x47E00200001FFFFF ),\r
+ LIT64( 0x47F00021FFFFFFFE ),\r
+ LIT64( 0x3FFFFFFFF80000FF ),\r
+ LIT64( 0x407FFFFFE00FFFFF ),\r
+ LIT64( 0x001497A63740C5E8 ),\r
+ LIT64( 0x44BFFFE0001FFFFF ),\r
+ LIT64( 0x16FFDFFEFFFFFFFF ),\r
+ LIT64( 0x403FC000000001FE ),\r
+ LIT64( 0x7FD00000000001F6 ),\r
+ LIT64( 0x0640400002000000 ),\r
+ LIT64( 0x479CEE1E4F789FE0 ),\r
+ LIT64( 0x4237FFFFFFFFFDFE )\r
+};\r
+\r
+static void time_az_float64_pos( float64 function( float64 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ function( inputs_float64_pos[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ function( inputs_float64_pos[ inputNum ] );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float64 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+enum {\r
+ numInputs_floatx80 = 32\r
+};\r
+\r
+static const struct {\r
+ bits16 high;\r
+ bits64 low;\r
+} inputs_floatx80[ numInputs_floatx80 ] = {\r
+ { 0xC03F, LIT64( 0xA9BE15A19C1E8B62 ) },\r
+ { 0x8000, LIT64( 0x0000000000000000 ) },\r
+ { 0x75A8, LIT64( 0xE59591E4788957A5 ) },\r
+ { 0xBFFF, LIT64( 0xFFF0000000000040 ) },\r
+ { 0x0CD8, LIT64( 0xFC000000000007FE ) },\r
+ { 0x43BA, LIT64( 0x99A4000000000000 ) },\r
+ { 0x3FFF, LIT64( 0x8000000000000000 ) },\r
+ { 0x4081, LIT64( 0x94FBF1BCEB5545F0 ) },\r
+ { 0x403E, LIT64( 0xFFF0000000002000 ) },\r
+ { 0x3FFE, LIT64( 0xC860E3C75D224F28 ) },\r
+ { 0x407E, LIT64( 0xFC00000FFFFFFFFE ) },\r
+ { 0x737A, LIT64( 0x800000007FFDFFFE ) },\r
+ { 0x4044, LIT64( 0xFFFFFF80000FFFFF ) },\r
+ { 0xBBFE, LIT64( 0x8000040000001FFE ) },\r
+ { 0xC002, LIT64( 0xFF80000000000020 ) },\r
+ { 0xDE8D, LIT64( 0xFFFFFFFFFFE00004 ) },\r
+ { 0xC004, LIT64( 0x8000000000003FFB ) },\r
+ { 0x407F, LIT64( 0x800000000003FFFE ) },\r
+ { 0xC000, LIT64( 0xA459EE6A5C16CA55 ) },\r
+ { 0x8003, LIT64( 0xC42CBF7399AEEB94 ) },\r
+ { 0xBF7F, LIT64( 0xF800000000000006 ) },\r
+ { 0xC07F, LIT64( 0xBF56BE8871F28FEA ) },\r
+ { 0xC07E, LIT64( 0xFFFF77FFFFFFFFFE ) },\r
+ { 0xADC9, LIT64( 0x8000000FFFFFFFDE ) },\r
+ { 0xC001, LIT64( 0xEFF7FFFFFFFFFFFF ) },\r
+ { 0x4001, LIT64( 0xBE84F30125C497A6 ) },\r
+ { 0xC06B, LIT64( 0xEFFFFFFFFFFFFFFF ) },\r
+ { 0x4080, LIT64( 0xFFFFFFFFBFFFFFFF ) },\r
+ { 0x87E9, LIT64( 0x81FFFFFFFFFFFBFF ) },\r
+ { 0xA63F, LIT64( 0x801FFFFFFEFFFFFE ) },\r
+ { 0x403C, LIT64( 0x801FFFFFFFF7FFFF ) },\r
+ { 0x4018, LIT64( 0x8000000000080003 ) }\r
+};\r
+\r
+static void time_a_floatx80_z_int32( int32 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_floatx80_z_int64( int64 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_floatx80_z_float32( float32 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_floatx80_z_float64( float64 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOAT128\r
+\r
+static void time_a_floatx80_z_float128( float128 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+static void time_az_floatx80( floatx80 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNum ].low;\r
+ a.high = inputs_floatx80[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_ab_floatx80_z_flag( flag function( floatx80, floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+ floatx80 a, b;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNumA ].low;\r
+ a.high = inputs_floatx80[ inputNumA ].high;\r
+ b.low = inputs_floatx80[ inputNumB ].low;\r
+ b.high = inputs_floatx80[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_floatx80 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNumA ].low;\r
+ a.high = inputs_floatx80[ inputNumA ].high;\r
+ b.low = inputs_floatx80[ inputNumB ].low;\r
+ b.high = inputs_floatx80[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_floatx80 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_abz_floatx80( floatx80 function( floatx80, floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+ floatx80 a, b;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNumA ].low;\r
+ a.high = inputs_floatx80[ inputNumA ].high;\r
+ b.low = inputs_floatx80[ inputNumB ].low;\r
+ b.high = inputs_floatx80[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_floatx80 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80[ inputNumA ].low;\r
+ a.high = inputs_floatx80[ inputNumA ].high;\r
+ b.low = inputs_floatx80[ inputNumB ].low;\r
+ b.high = inputs_floatx80[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_floatx80 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static const struct {\r
+ bits16 high;\r
+ bits64 low;\r
+} inputs_floatx80_pos[ numInputs_floatx80 ] = {\r
+ { 0x403F, LIT64( 0xA9BE15A19C1E8B62 ) },\r
+ { 0x0000, LIT64( 0x0000000000000000 ) },\r
+ { 0x75A8, LIT64( 0xE59591E4788957A5 ) },\r
+ { 0x3FFF, LIT64( 0xFFF0000000000040 ) },\r
+ { 0x0CD8, LIT64( 0xFC000000000007FE ) },\r
+ { 0x43BA, LIT64( 0x99A4000000000000 ) },\r
+ { 0x3FFF, LIT64( 0x8000000000000000 ) },\r
+ { 0x4081, LIT64( 0x94FBF1BCEB5545F0 ) },\r
+ { 0x403E, LIT64( 0xFFF0000000002000 ) },\r
+ { 0x3FFE, LIT64( 0xC860E3C75D224F28 ) },\r
+ { 0x407E, LIT64( 0xFC00000FFFFFFFFE ) },\r
+ { 0x737A, LIT64( 0x800000007FFDFFFE ) },\r
+ { 0x4044, LIT64( 0xFFFFFF80000FFFFF ) },\r
+ { 0x3BFE, LIT64( 0x8000040000001FFE ) },\r
+ { 0x4002, LIT64( 0xFF80000000000020 ) },\r
+ { 0x5E8D, LIT64( 0xFFFFFFFFFFE00004 ) },\r
+ { 0x4004, LIT64( 0x8000000000003FFB ) },\r
+ { 0x407F, LIT64( 0x800000000003FFFE ) },\r
+ { 0x4000, LIT64( 0xA459EE6A5C16CA55 ) },\r
+ { 0x0003, LIT64( 0xC42CBF7399AEEB94 ) },\r
+ { 0x3F7F, LIT64( 0xF800000000000006 ) },\r
+ { 0x407F, LIT64( 0xBF56BE8871F28FEA ) },\r
+ { 0x407E, LIT64( 0xFFFF77FFFFFFFFFE ) },\r
+ { 0x2DC9, LIT64( 0x8000000FFFFFFFDE ) },\r
+ { 0x4001, LIT64( 0xEFF7FFFFFFFFFFFF ) },\r
+ { 0x4001, LIT64( 0xBE84F30125C497A6 ) },\r
+ { 0x406B, LIT64( 0xEFFFFFFFFFFFFFFF ) },\r
+ { 0x4080, LIT64( 0xFFFFFFFFBFFFFFFF ) },\r
+ { 0x07E9, LIT64( 0x81FFFFFFFFFFFBFF ) },\r
+ { 0x263F, LIT64( 0x801FFFFFFEFFFFFE ) },\r
+ { 0x403C, LIT64( 0x801FFFFFFFF7FFFF ) },\r
+ { 0x4018, LIT64( 0x8000000000080003 ) }\r
+};\r
+\r
+static void time_az_floatx80_pos( floatx80 function( floatx80 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ floatx80 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_floatx80_pos[ inputNum ].low;\r
+ a.high = inputs_floatx80_pos[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_floatx80_pos[ inputNum ].low;\r
+ a.high = inputs_floatx80_pos[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_floatx80 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+enum {\r
+ numInputs_float128 = 32\r
+};\r
+\r
+static const struct {\r
+ bits64 high, low;\r
+} inputs_float128[ numInputs_float128 ] = {\r
+ { LIT64( 0x3FDA200000100000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x3FFF000000000000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x85F14776190C8306 ), LIT64( 0xD8715F4E3D54BB92 ) },\r
+ { LIT64( 0xF2B00000007FFFFF ), LIT64( 0xFFFFFFFFFFF7FFFF ) },\r
+ { LIT64( 0x8000000000000000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0xBFFFFFFFFFE00000 ), LIT64( 0x0000008000000000 ) },\r
+ { LIT64( 0x407F1719CE722F3E ), LIT64( 0xDA6B3FE5FF29425B ) },\r
+ { LIT64( 0x43FFFF8000000000 ), LIT64( 0x0000000000400000 ) },\r
+ { LIT64( 0x401E000000000100 ), LIT64( 0x0000000000002000 ) },\r
+ { LIT64( 0x3FFED71DACDA8E47 ), LIT64( 0x4860E3C75D224F28 ) },\r
+ { LIT64( 0xBF7ECFC1E90647D1 ), LIT64( 0x7A124FE55623EE44 ) },\r
+ { LIT64( 0x0DF7007FFFFFFFFF ), LIT64( 0xFFFFFFFFEFFFFFFF ) },\r
+ { LIT64( 0x3FE5FFEFFFFFFFFF ), LIT64( 0xFFFFFFFFFFFFEFFF ) },\r
+ { LIT64( 0x403FFFFFFFFFFFFF ), LIT64( 0xFFFFFFFFFFFFFBFE ) },\r
+ { LIT64( 0xBFFB2FBF7399AFEB ), LIT64( 0xA459EE6A5C16CA55 ) },\r
+ { LIT64( 0xBDB8FFFFFFFFFFFC ), LIT64( 0x0000000000000400 ) },\r
+ { LIT64( 0x3FC8FFDFFFFFFFFF ), LIT64( 0xFFFFFFFFF0000000 ) },\r
+ { LIT64( 0x3FFBFFFFFFDFFFFF ), LIT64( 0xFFF8000000000000 ) },\r
+ { LIT64( 0x407043C11737BE84 ), LIT64( 0xDDD58212ADC937F4 ) },\r
+ { LIT64( 0x8001000000000000 ), LIT64( 0x0000001000000001 ) },\r
+ { LIT64( 0xC036FFFFFFFFFFFF ), LIT64( 0xFE40000000000000 ) },\r
+ { LIT64( 0x4002FFFFFE000002 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x4000C3FEDE897773 ), LIT64( 0x326AC4FD8EFBE6DC ) },\r
+ { LIT64( 0xBFFF0000000FFFFF ), LIT64( 0xFFFFFE0000000000 ) },\r
+ { LIT64( 0x62C3E502146E426D ), LIT64( 0x43F3CAA0DC7DF1A0 ) },\r
+ { LIT64( 0xB5CBD32E52BB570E ), LIT64( 0xBCC477CB11C6236C ) },\r
+ { LIT64( 0xE228FFFFFFC00000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x3F80000000000000 ), LIT64( 0x0000000080000008 ) },\r
+ { LIT64( 0xC1AFFFDFFFFFFFFF ), LIT64( 0xFFFC000000000000 ) },\r
+ { LIT64( 0xC96F000000000000 ), LIT64( 0x00000001FFFBFFFF ) },\r
+ { LIT64( 0x3DE09BFE7923A338 ), LIT64( 0xBCC8FBBD7CEC1F4F ) },\r
+ { LIT64( 0x401CFFFFFFFFFFFF ), LIT64( 0xFFFFFFFEFFFFFF80 ) }\r
+};\r
+\r
+static void time_a_float128_z_int32( int32 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float128_z_int64( int64 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float128_z_float32( float32 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_a_float128_z_float64( float64 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+static void time_a_float128_z_floatx80( floatx80 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+static void time_az_float128( float128 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNum ].low;\r
+ a.high = inputs_float128[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_ab_float128_z_flag( flag function( float128, float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+ float128 a, b;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNumA ].low;\r
+ a.high = inputs_float128[ inputNumA ].high;\r
+ b.low = inputs_float128[ inputNumB ].low;\r
+ b.high = inputs_float128[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float128 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNumA ].low;\r
+ a.high = inputs_float128[ inputNumA ].high;\r
+ b.low = inputs_float128[ inputNumB ].low;\r
+ b.high = inputs_float128[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float128 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static void time_abz_float128( float128 function( float128, float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNumA, inputNumB;\r
+ float128 a, b;\r
+\r
+ count = 0;\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128[ inputNumA ].low;\r
+ a.high = inputs_float128[ inputNumA ].high;\r
+ b.low = inputs_float128[ inputNumB ].low;\r
+ b.high = inputs_float128[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float128 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNumA = 0;\r
+ inputNumB = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128[ inputNumA ].low;\r
+ a.high = inputs_float128[ inputNumA ].high;\r
+ b.low = inputs_float128[ inputNumB ].low;\r
+ b.high = inputs_float128[ inputNumB ].high;\r
+ function( a, b );\r
+ inputNumA = ( inputNumA + 1 ) & ( numInputs_float128 - 1 );\r
+ if ( inputNumA == 0 ) ++inputNumB;\r
+ inputNumB = ( inputNumB + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+static const struct {\r
+ bits64 high, low;\r
+} inputs_float128_pos[ numInputs_float128 ] = {\r
+ { LIT64( 0x3FDA200000100000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x3FFF000000000000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x05F14776190C8306 ), LIT64( 0xD8715F4E3D54BB92 ) },\r
+ { LIT64( 0x72B00000007FFFFF ), LIT64( 0xFFFFFFFFFFF7FFFF ) },\r
+ { LIT64( 0x0000000000000000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x3FFFFFFFFFE00000 ), LIT64( 0x0000008000000000 ) },\r
+ { LIT64( 0x407F1719CE722F3E ), LIT64( 0xDA6B3FE5FF29425B ) },\r
+ { LIT64( 0x43FFFF8000000000 ), LIT64( 0x0000000000400000 ) },\r
+ { LIT64( 0x401E000000000100 ), LIT64( 0x0000000000002000 ) },\r
+ { LIT64( 0x3FFED71DACDA8E47 ), LIT64( 0x4860E3C75D224F28 ) },\r
+ { LIT64( 0x3F7ECFC1E90647D1 ), LIT64( 0x7A124FE55623EE44 ) },\r
+ { LIT64( 0x0DF7007FFFFFFFFF ), LIT64( 0xFFFFFFFFEFFFFFFF ) },\r
+ { LIT64( 0x3FE5FFEFFFFFFFFF ), LIT64( 0xFFFFFFFFFFFFEFFF ) },\r
+ { LIT64( 0x403FFFFFFFFFFFFF ), LIT64( 0xFFFFFFFFFFFFFBFE ) },\r
+ { LIT64( 0x3FFB2FBF7399AFEB ), LIT64( 0xA459EE6A5C16CA55 ) },\r
+ { LIT64( 0x3DB8FFFFFFFFFFFC ), LIT64( 0x0000000000000400 ) },\r
+ { LIT64( 0x3FC8FFDFFFFFFFFF ), LIT64( 0xFFFFFFFFF0000000 ) },\r
+ { LIT64( 0x3FFBFFFFFFDFFFFF ), LIT64( 0xFFF8000000000000 ) },\r
+ { LIT64( 0x407043C11737BE84 ), LIT64( 0xDDD58212ADC937F4 ) },\r
+ { LIT64( 0x0001000000000000 ), LIT64( 0x0000001000000001 ) },\r
+ { LIT64( 0x4036FFFFFFFFFFFF ), LIT64( 0xFE40000000000000 ) },\r
+ { LIT64( 0x4002FFFFFE000002 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x4000C3FEDE897773 ), LIT64( 0x326AC4FD8EFBE6DC ) },\r
+ { LIT64( 0x3FFF0000000FFFFF ), LIT64( 0xFFFFFE0000000000 ) },\r
+ { LIT64( 0x62C3E502146E426D ), LIT64( 0x43F3CAA0DC7DF1A0 ) },\r
+ { LIT64( 0x35CBD32E52BB570E ), LIT64( 0xBCC477CB11C6236C ) },\r
+ { LIT64( 0x6228FFFFFFC00000 ), LIT64( 0x0000000000000000 ) },\r
+ { LIT64( 0x3F80000000000000 ), LIT64( 0x0000000080000008 ) },\r
+ { LIT64( 0x41AFFFDFFFFFFFFF ), LIT64( 0xFFFC000000000000 ) },\r
+ { LIT64( 0x496F000000000000 ), LIT64( 0x00000001FFFBFFFF ) },\r
+ { LIT64( 0x3DE09BFE7923A338 ), LIT64( 0xBCC8FBBD7CEC1F4F ) },\r
+ { LIT64( 0x401CFFFFFFFFFFFF ), LIT64( 0xFFFFFFFEFFFFFF80 ) }\r
+};\r
+\r
+static void time_az_float128_pos( float128 function( float128 ) )\r
+{\r
+ clock_t startClock, endClock;\r
+ int32 count, i;\r
+ int8 inputNum;\r
+ float128 a;\r
+\r
+ count = 0;\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ do {\r
+ for ( i = minIterations; i; --i ) {\r
+ a.low = inputs_float128_pos[ inputNum ].low;\r
+ a.high = inputs_float128_pos[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ count += minIterations;\r
+ } while ( clock() - startClock < CLOCKS_PER_SEC );\r
+ inputNum = 0;\r
+ startClock = clock();\r
+ for ( i = count; i; --i ) {\r
+ a.low = inputs_float128_pos[ inputNum ].low;\r
+ a.high = inputs_float128_pos[ inputNum ].high;\r
+ function( a );\r
+ inputNum = ( inputNum + 1 ) & ( numInputs_float128 - 1 );\r
+ }\r
+ endClock = clock();\r
+ reportTime( count, endClock - startClock );\r
+\r
+}\r
+\r
+#endif\r
+\r
+enum {\r
+ INT32_TO_FLOAT32 = 1,\r
+ INT32_TO_FLOAT64,\r
+#ifdef FLOATX80\r
+ INT32_TO_FLOATX80,\r
+#endif\r
+#ifdef FLOAT128\r
+ INT32_TO_FLOAT128,\r
+#endif\r
+ INT64_TO_FLOAT32,\r
+ INT64_TO_FLOAT64,\r
+#ifdef FLOATX80\r
+ INT64_TO_FLOATX80,\r
+#endif\r
+#ifdef FLOAT128\r
+ INT64_TO_FLOAT128,\r
+#endif\r
+ FLOAT32_TO_INT32,\r
+ FLOAT32_TO_INT32_ROUND_TO_ZERO,\r
+ FLOAT32_TO_INT64,\r
+ FLOAT32_TO_INT64_ROUND_TO_ZERO,\r
+ FLOAT32_TO_FLOAT64,\r
+#ifdef FLOATX80\r
+ FLOAT32_TO_FLOATX80,\r
+#endif\r
+#ifdef FLOAT128\r
+ FLOAT32_TO_FLOAT128,\r
+#endif\r
+ FLOAT32_ROUND_TO_INT,\r
+ FLOAT32_ADD,\r
+ FLOAT32_SUB,\r
+ FLOAT32_MUL,\r
+ FLOAT32_DIV,\r
+ FLOAT32_REM,\r
+ FLOAT32_SQRT,\r
+ FLOAT32_EQ,\r
+ FLOAT32_LE,\r
+ FLOAT32_LT,\r
+ FLOAT32_EQ_SIGNALING,\r
+ FLOAT32_LE_QUIET,\r
+ FLOAT32_LT_QUIET,\r
+ FLOAT64_TO_INT32,\r
+ FLOAT64_TO_INT32_ROUND_TO_ZERO,\r
+ FLOAT64_TO_INT64,\r
+ FLOAT64_TO_INT64_ROUND_TO_ZERO,\r
+ FLOAT64_TO_FLOAT32,\r
+#ifdef FLOATX80\r
+ FLOAT64_TO_FLOATX80,\r
+#endif\r
+#ifdef FLOAT128\r
+ FLOAT64_TO_FLOAT128,\r
+#endif\r
+ FLOAT64_ROUND_TO_INT,\r
+ FLOAT64_ADD,\r
+ FLOAT64_SUB,\r
+ FLOAT64_MUL,\r
+ FLOAT64_DIV,\r
+ FLOAT64_REM,\r
+ FLOAT64_SQRT,\r
+ FLOAT64_EQ,\r
+ FLOAT64_LE,\r
+ FLOAT64_LT,\r
+ FLOAT64_EQ_SIGNALING,\r
+ FLOAT64_LE_QUIET,\r
+ FLOAT64_LT_QUIET,\r
+#ifdef FLOATX80\r
+ FLOATX80_TO_INT32,\r
+ FLOATX80_TO_INT32_ROUND_TO_ZERO,\r
+ FLOATX80_TO_INT64,\r
+ FLOATX80_TO_INT64_ROUND_TO_ZERO,\r
+ FLOATX80_TO_FLOAT32,\r
+ FLOATX80_TO_FLOAT64,\r
+#ifdef FLOAT128\r
+ FLOATX80_TO_FLOAT128,\r
+#endif\r
+ FLOATX80_ROUND_TO_INT,\r
+ FLOATX80_ADD,\r
+ FLOATX80_SUB,\r
+ FLOATX80_MUL,\r
+ FLOATX80_DIV,\r
+ FLOATX80_REM,\r
+ FLOATX80_SQRT,\r
+ FLOATX80_EQ,\r
+ FLOATX80_LE,\r
+ FLOATX80_LT,\r
+ FLOATX80_EQ_SIGNALING,\r
+ FLOATX80_LE_QUIET,\r
+ FLOATX80_LT_QUIET,\r
+#endif\r
+#ifdef FLOAT128\r
+ FLOAT128_TO_INT32,\r
+ FLOAT128_TO_INT32_ROUND_TO_ZERO,\r
+ FLOAT128_TO_INT64,\r
+ FLOAT128_TO_INT64_ROUND_TO_ZERO,\r
+ FLOAT128_TO_FLOAT32,\r
+ FLOAT128_TO_FLOAT64,\r
+#ifdef FLOATX80\r
+ FLOAT128_TO_FLOATX80,\r
+#endif\r
+ FLOAT128_ROUND_TO_INT,\r
+ FLOAT128_ADD,\r
+ FLOAT128_SUB,\r
+ FLOAT128_MUL,\r
+ FLOAT128_DIV,\r
+ FLOAT128_REM,\r
+ FLOAT128_SQRT,\r
+ FLOAT128_EQ,\r
+ FLOAT128_LE,\r
+ FLOAT128_LT,\r
+ FLOAT128_EQ_SIGNALING,\r
+ FLOAT128_LE_QUIET,\r
+ FLOAT128_LT_QUIET,\r
+#endif\r
+ NUM_FUNCTIONS\r
+};\r
+\r
+static struct {\r
+ char *name;\r
+ int8 numInputs;\r
+ flag roundingPrecision, roundingMode;\r
+ flag tininessMode, tininessModeAtReducedPrecision;\r
+} functions[ NUM_FUNCTIONS ] = {\r
+ { 0, 0, 0, 0, 0, 0 },\r
+ { "int32_to_float32", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "int32_to_float64", 1, FALSE, FALSE, FALSE, FALSE },\r
+#ifdef FLOATX80\r
+ { "int32_to_floatx80", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+#ifdef FLOAT128\r
+ { "int32_to_float128", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+ { "int64_to_float32", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "int64_to_float64", 1, FALSE, TRUE, FALSE, FALSE },\r
+#ifdef FLOATX80\r
+ { "int64_to_floatx80", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+#ifdef FLOAT128\r
+ { "int64_to_float128", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+ { "float32_to_int32", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_to_int32_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_to_int64", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_to_int64_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_to_float64", 1, FALSE, FALSE, FALSE, FALSE },\r
+#ifdef FLOATX80\r
+ { "float32_to_floatx80", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+#ifdef FLOAT128\r
+ { "float32_to_float128", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+ { "float32_round_to_int", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_add", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_sub", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_mul", 2, FALSE, TRUE, TRUE, FALSE },\r
+ { "float32_div", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_rem", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_sqrt", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float32_eq", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_le", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_lt", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_eq_signaling", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_le_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float32_lt_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_to_int32", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_to_int32_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_to_int64", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_to_int64_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_to_float32", 1, FALSE, TRUE, TRUE, FALSE },\r
+#ifdef FLOATX80\r
+ { "float64_to_floatx80", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+#ifdef FLOAT128\r
+ { "float64_to_float128", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+ { "float64_round_to_int", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_add", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_sub", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_mul", 2, FALSE, TRUE, TRUE, FALSE },\r
+ { "float64_div", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_rem", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_sqrt", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float64_eq", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_le", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_lt", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_eq_signaling", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_le_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float64_lt_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+#ifdef FLOATX80\r
+ { "floatx80_to_int32", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "floatx80_to_int32_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_to_int64", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "floatx80_to_int64_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_to_float32", 1, FALSE, TRUE, TRUE, FALSE },\r
+ { "floatx80_to_float64", 1, FALSE, TRUE, TRUE, FALSE },\r
+#ifdef FLOAT128\r
+ { "floatx80_to_float128", 1, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+ { "floatx80_round_to_int", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "floatx80_add", 2, TRUE, TRUE, FALSE, TRUE },\r
+ { "floatx80_sub", 2, TRUE, TRUE, FALSE, TRUE },\r
+ { "floatx80_mul", 2, TRUE, TRUE, TRUE, TRUE },\r
+ { "floatx80_div", 2, TRUE, TRUE, FALSE, TRUE },\r
+ { "floatx80_rem", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_sqrt", 1, TRUE, TRUE, FALSE, FALSE },\r
+ { "floatx80_eq", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_le", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_lt", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_eq_signaling", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_le_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "floatx80_lt_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+#ifdef FLOAT128\r
+ { "float128_to_int32", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_to_int32_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_to_int64", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_to_int64_round_to_zero", 1, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_to_float32", 1, FALSE, TRUE, TRUE, FALSE },\r
+ { "float128_to_float64", 1, FALSE, TRUE, TRUE, FALSE },\r
+#ifdef FLOATX80\r
+ { "float128_to_floatx80", 1, FALSE, TRUE, TRUE, FALSE },\r
+#endif\r
+ { "float128_round_to_int", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_add", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_sub", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_mul", 2, FALSE, TRUE, TRUE, FALSE },\r
+ { "float128_div", 2, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_rem", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_sqrt", 1, FALSE, TRUE, FALSE, FALSE },\r
+ { "float128_eq", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_le", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_lt", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_eq_signaling", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_le_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+ { "float128_lt_quiet", 2, FALSE, FALSE, FALSE, FALSE },\r
+#endif\r
+};\r
+\r
+enum {\r
+ ROUND_NEAREST_EVEN = 1,\r
+ ROUND_TO_ZERO,\r
+ ROUND_DOWN,\r
+ ROUND_UP,\r
+ NUM_ROUNDINGMODES\r
+};\r
+enum {\r
+ TININESS_BEFORE_ROUNDING = 1,\r
+ TININESS_AFTER_ROUNDING,\r
+ NUM_TININESSMODES\r
+};\r
+\r
+static void\r
+ timeFunctionVariety(\r
+ uint8 functionCode,\r
+ int8 roundingPrecision,\r
+ int8 roundingMode,\r
+ int8 tininessMode\r
+ )\r
+{\r
+ uint8 roundingCode;\r
+ int8 tininessCode;\r
+\r
+ functionName = functions[ functionCode ].name;\r
+ if ( roundingPrecision == 32 ) {\r
+ roundingPrecisionName = "32";\r
+ }\r
+ else if ( roundingPrecision == 64 ) {\r
+ roundingPrecisionName = "64";\r
+ }\r
+ else if ( roundingPrecision == 80 ) {\r
+ roundingPrecisionName = "80";\r
+ }\r
+ else {\r
+ roundingPrecisionName = 0;\r
+ }\r
+#ifdef FLOATX80\r
+ floatx80_rounding_precision = roundingPrecision;\r
+#endif\r
+ switch ( roundingMode ) {\r
+ case 0:\r
+ roundingModeName = 0;\r
+ roundingCode = float_round_nearest_even;\r
+ break;\r
+ case ROUND_NEAREST_EVEN:\r
+ roundingModeName = "nearest_even";\r
+ roundingCode = float_round_nearest_even;\r
+ break;\r
+ case ROUND_TO_ZERO:\r
+ roundingModeName = "to_zero";\r
+ roundingCode = float_round_to_zero;\r
+ break;\r
+ case ROUND_DOWN:\r
+ roundingModeName = "down";\r
+ roundingCode = float_round_down;\r
+ break;\r
+ case ROUND_UP:\r
+ roundingModeName = "up";\r
+ roundingCode = float_round_up;\r
+ break;\r
+ }\r
+ float_rounding_mode = roundingCode;\r
+ switch ( tininessMode ) {\r
+ case 0:\r
+ tininessModeName = 0;\r
+ tininessCode = float_tininess_after_rounding;\r
+ break;\r
+ case TININESS_BEFORE_ROUNDING:\r
+ tininessModeName = "before";\r
+ tininessCode = float_tininess_before_rounding;\r
+ break;\r
+ case TININESS_AFTER_ROUNDING:\r
+ tininessModeName = "after";\r
+ tininessCode = float_tininess_after_rounding;\r
+ break;\r
+ }\r
+ float_detect_tininess = tininessCode;\r
+ switch ( functionCode ) {\r
+ case INT32_TO_FLOAT32:\r
+ time_a_int32_z_float32( int32_to_float32 );\r
+ break;\r
+ case INT32_TO_FLOAT64:\r
+ time_a_int32_z_float64( int32_to_float64 );\r
+ break;\r
+#ifdef FLOATX80\r
+ case INT32_TO_FLOATX80:\r
+ time_a_int32_z_floatx80( int32_to_floatx80 );\r
+ break;\r
+#endif\r
+#ifdef FLOAT128\r
+ case INT32_TO_FLOAT128:\r
+ time_a_int32_z_float128( int32_to_float128 );\r
+ break;\r
+#endif\r
+ case INT64_TO_FLOAT32:\r
+ time_a_int64_z_float32( int64_to_float32 );\r
+ break;\r
+ case INT64_TO_FLOAT64:\r
+ time_a_int64_z_float64( int64_to_float64 );\r
+ break;\r
+#ifdef FLOATX80\r
+ case INT64_TO_FLOATX80:\r
+ time_a_int64_z_floatx80( int64_to_floatx80 );\r
+ break;\r
+#endif\r
+#ifdef FLOAT128\r
+ case INT64_TO_FLOAT128:\r
+ time_a_int64_z_float128( int64_to_float128 );\r
+ break;\r
+#endif\r
+ case FLOAT32_TO_INT32:\r
+ time_a_float32_z_int32( float32_to_int32 );\r
+ break;\r
+ case FLOAT32_TO_INT32_ROUND_TO_ZERO:\r
+ time_a_float32_z_int32( float32_to_int32_round_to_zero );\r
+ break;\r
+ case FLOAT32_TO_INT64:\r
+ time_a_float32_z_int64( float32_to_int64 );\r
+ break;\r
+ case FLOAT32_TO_INT64_ROUND_TO_ZERO:\r
+ time_a_float32_z_int64( float32_to_int64_round_to_zero );\r
+ break;\r
+ case FLOAT32_TO_FLOAT64:\r
+ time_a_float32_z_float64( float32_to_float64 );\r
+ break;\r
+#ifdef FLOATX80\r
+ case FLOAT32_TO_FLOATX80:\r
+ time_a_float32_z_floatx80( float32_to_floatx80 );\r
+ break;\r
+#endif\r
+#ifdef FLOAT128\r
+ case FLOAT32_TO_FLOAT128:\r
+ time_a_float32_z_float128( float32_to_float128 );\r
+ break;\r
+#endif\r
+ case FLOAT32_ROUND_TO_INT:\r
+ time_az_float32( float32_round_to_int );\r
+ break;\r
+ case FLOAT32_ADD:\r
+ time_abz_float32( float32_add );\r
+ break;\r
+ case FLOAT32_SUB:\r
+ time_abz_float32( float32_sub );\r
+ break;\r
+ case FLOAT32_MUL:\r
+ time_abz_float32( float32_mul );\r
+ break;\r
+ case FLOAT32_DIV:\r
+ time_abz_float32( float32_div );\r
+ break;\r
+ case FLOAT32_REM:\r
+ time_abz_float32( float32_rem );\r
+ break;\r
+ case FLOAT32_SQRT:\r
+ time_az_float32_pos( float32_sqrt );\r
+ break;\r
+ case FLOAT32_EQ:\r
+ time_ab_float32_z_flag( float32_eq );\r
+ break;\r
+ case FLOAT32_LE:\r
+ time_ab_float32_z_flag( float32_le );\r
+ break;\r
+ case FLOAT32_LT:\r
+ time_ab_float32_z_flag( float32_lt );\r
+ break;\r
+ case FLOAT32_EQ_SIGNALING:\r
+ time_ab_float32_z_flag( float32_eq_signaling );\r
+ break;\r
+ case FLOAT32_LE_QUIET:\r
+ time_ab_float32_z_flag( float32_le_quiet );\r
+ break;\r
+ case FLOAT32_LT_QUIET:\r
+ time_ab_float32_z_flag( float32_lt_quiet );\r
+ break;\r
+ case FLOAT64_TO_INT32:\r
+ time_a_float64_z_int32( float64_to_int32 );\r
+ break;\r
+ case FLOAT64_TO_INT32_ROUND_TO_ZERO:\r
+ time_a_float64_z_int32( float64_to_int32_round_to_zero );\r
+ break;\r
+ case FLOAT64_TO_INT64:\r
+ time_a_float64_z_int64( float64_to_int64 );\r
+ break;\r
+ case FLOAT64_TO_INT64_ROUND_TO_ZERO:\r
+ time_a_float64_z_int64( float64_to_int64_round_to_zero );\r
+ break;\r
+ case FLOAT64_TO_FLOAT32:\r
+ time_a_float64_z_float32( float64_to_float32 );\r
+ break;\r
+#ifdef FLOATX80\r
+ case FLOAT64_TO_FLOATX80:\r
+ time_a_float64_z_floatx80( float64_to_floatx80 );\r
+ break;\r
+#endif\r
+#ifdef FLOAT128\r
+ case FLOAT64_TO_FLOAT128:\r
+ time_a_float64_z_float128( float64_to_float128 );\r
+ break;\r
+#endif\r
+ case FLOAT64_ROUND_TO_INT:\r
+ time_az_float64( float64_round_to_int );\r
+ break;\r
+ case FLOAT64_ADD:\r
+ time_abz_float64( float64_add );\r
+ break;\r
+ case FLOAT64_SUB:\r
+ time_abz_float64( float64_sub );\r
+ break;\r
+ case FLOAT64_MUL:\r
+ time_abz_float64( float64_mul );\r
+ break;\r
+ case FLOAT64_DIV:\r
+ time_abz_float64( float64_div );\r
+ break;\r
+ case FLOAT64_REM:\r
+ time_abz_float64( float64_rem );\r
+ break;\r
+ case FLOAT64_SQRT:\r
+ time_az_float64_pos( float64_sqrt );\r
+ break;\r
+ case FLOAT64_EQ:\r
+ time_ab_float64_z_flag( float64_eq );\r
+ break;\r
+ case FLOAT64_LE:\r
+ time_ab_float64_z_flag( float64_le );\r
+ break;\r
+ case FLOAT64_LT:\r
+ time_ab_float64_z_flag( float64_lt );\r
+ break;\r
+ case FLOAT64_EQ_SIGNALING:\r
+ time_ab_float64_z_flag( float64_eq_signaling );\r
+ break;\r
+ case FLOAT64_LE_QUIET:\r
+ time_ab_float64_z_flag( float64_le_quiet );\r
+ break;\r
+ case FLOAT64_LT_QUIET:\r
+ time_ab_float64_z_flag( float64_lt_quiet );\r
+ break;\r
+#ifdef FLOATX80\r
+ case FLOATX80_TO_INT32:\r
+ time_a_floatx80_z_int32( floatx80_to_int32 );\r
+ break;\r
+ case FLOATX80_TO_INT32_ROUND_TO_ZERO:\r
+ time_a_floatx80_z_int32( floatx80_to_int32_round_to_zero );\r
+ break;\r
+ case FLOATX80_TO_INT64:\r
+ time_a_floatx80_z_int64( floatx80_to_int64 );\r
+ break;\r
+ case FLOATX80_TO_INT64_ROUND_TO_ZERO:\r
+ time_a_floatx80_z_int64( floatx80_to_int64_round_to_zero );\r
+ break;\r
+ case FLOATX80_TO_FLOAT32:\r
+ time_a_floatx80_z_float32( floatx80_to_float32 );\r
+ break;\r
+ case FLOATX80_TO_FLOAT64:\r
+ time_a_floatx80_z_float64( floatx80_to_float64 );\r
+ break;\r
+#ifdef FLOAT128\r
+ case FLOATX80_TO_FLOAT128:\r
+ time_a_floatx80_z_float128( floatx80_to_float128 );\r
+ break;\r
+#endif\r
+ case FLOATX80_ROUND_TO_INT:\r
+ time_az_floatx80( floatx80_round_to_int );\r
+ break;\r
+ case FLOATX80_ADD:\r
+ time_abz_floatx80( floatx80_add );\r
+ break;\r
+ case FLOATX80_SUB:\r
+ time_abz_floatx80( floatx80_sub );\r
+ break;\r
+ case FLOATX80_MUL:\r
+ time_abz_floatx80( floatx80_mul );\r
+ break;\r
+ case FLOATX80_DIV:\r
+ time_abz_floatx80( floatx80_div );\r
+ break;\r
+ case FLOATX80_REM:\r
+ time_abz_floatx80( floatx80_rem );\r
+ break;\r
+ case FLOATX80_SQRT:\r
+ time_az_floatx80_pos( floatx80_sqrt );\r
+ break;\r
+ case FLOATX80_EQ:\r
+ time_ab_floatx80_z_flag( floatx80_eq );\r
+ break;\r
+ case FLOATX80_LE:\r
+ time_ab_floatx80_z_flag( floatx80_le );\r
+ break;\r
+ case FLOATX80_LT:\r
+ time_ab_floatx80_z_flag( floatx80_lt );\r
+ break;\r
+ case FLOATX80_EQ_SIGNALING:\r
+ time_ab_floatx80_z_flag( floatx80_eq_signaling );\r
+ break;\r
+ case FLOATX80_LE_QUIET:\r
+ time_ab_floatx80_z_flag( floatx80_le_quiet );\r
+ break;\r
+ case FLOATX80_LT_QUIET:\r
+ time_ab_floatx80_z_flag( floatx80_lt_quiet );\r
+ break;\r
+#endif\r
+#ifdef FLOAT128\r
+ case FLOAT128_TO_INT32:\r
+ time_a_float128_z_int32( float128_to_int32 );\r
+ break;\r
+ case FLOAT128_TO_INT32_ROUND_TO_ZERO:\r
+ time_a_float128_z_int32( float128_to_int32_round_to_zero );\r
+ break;\r
+ case FLOAT128_TO_INT64:\r
+ time_a_float128_z_int64( float128_to_int64 );\r
+ break;\r
+ case FLOAT128_TO_INT64_ROUND_TO_ZERO:\r
+ time_a_float128_z_int64( float128_to_int64_round_to_zero );\r
+ break;\r
+ case FLOAT128_TO_FLOAT32:\r
+ time_a_float128_z_float32( float128_to_float32 );\r
+ break;\r
+ case FLOAT128_TO_FLOAT64:\r
+ time_a_float128_z_float64( float128_to_float64 );\r
+ break;\r
+#ifdef FLOATX80\r
+ case FLOAT128_TO_FLOATX80:\r
+ time_a_float128_z_floatx80( float128_to_floatx80 );\r
+ break;\r
+#endif\r
+ case FLOAT128_ROUND_TO_INT:\r
+ time_az_float128( float128_round_to_int );\r
+ break;\r
+ case FLOAT128_ADD:\r
+ time_abz_float128( float128_add );\r
+ break;\r
+ case FLOAT128_SUB:\r
+ time_abz_float128( float128_sub );\r
+ break;\r
+ case FLOAT128_MUL:\r
+ time_abz_float128( float128_mul );\r
+ break;\r
+ case FLOAT128_DIV:\r
+ time_abz_float128( float128_div );\r
+ break;\r
+ case FLOAT128_REM:\r
+ time_abz_float128( float128_rem );\r
+ break;\r
+ case FLOAT128_SQRT:\r
+ time_az_float128_pos( float128_sqrt );\r
+ break;\r
+ case FLOAT128_EQ:\r
+ time_ab_float128_z_flag( float128_eq );\r
+ break;\r
+ case FLOAT128_LE:\r
+ time_ab_float128_z_flag( float128_le );\r
+ break;\r
+ case FLOAT128_LT:\r
+ time_ab_float128_z_flag( float128_lt );\r
+ break;\r
+ case FLOAT128_EQ_SIGNALING:\r
+ time_ab_float128_z_flag( float128_eq_signaling );\r
+ break;\r
+ case FLOAT128_LE_QUIET:\r
+ time_ab_float128_z_flag( float128_le_quiet );\r
+ break;\r
+ case FLOAT128_LT_QUIET:\r
+ time_ab_float128_z_flag( float128_lt_quiet );\r
+ break;\r
+#endif\r
+ }\r
+\r
+}\r
+\r
+static void\r
+ timeFunction(\r
+ uint8 functionCode,\r
+ int8 roundingPrecisionIn,\r
+ int8 roundingModeIn,\r
+ int8 tininessModeIn\r
+ )\r
+{\r
+ int8 roundingPrecision, roundingMode, tininessMode;\r
+\r
+ roundingPrecision = 32;\r
+ for (;;) {\r
+ if ( ! functions[ functionCode ].roundingPrecision ) {\r
+ roundingPrecision = 0;\r
+ }\r
+ else if ( roundingPrecisionIn ) {\r
+ roundingPrecision = roundingPrecisionIn;\r
+ }\r
+ for ( roundingMode = 1;\r
+ roundingMode < NUM_ROUNDINGMODES;\r
+ ++roundingMode\r
+ ) {\r
+ if ( ! functions[ functionCode ].roundingMode ) {\r
+ roundingMode = 0;\r
+ }\r
+ else if ( roundingModeIn ) {\r
+ roundingMode = roundingModeIn;\r
+ }\r
+ for ( tininessMode = 1;\r
+ tininessMode < NUM_TININESSMODES;\r
+ ++tininessMode\r
+ ) {\r
+ if ( ( roundingPrecision == 32 )\r
+ || ( roundingPrecision == 64 ) ) {\r
+ if ( ! functions[ functionCode ]\r
+ .tininessModeAtReducedPrecision\r
+ ) {\r
+ tininessMode = 0;\r
+ }\r
+ else if ( tininessModeIn ) {\r
+ tininessMode = tininessModeIn;\r
+ }\r
+ }\r
+ else {\r
+ if ( ! functions[ functionCode ].tininessMode ) {\r
+ tininessMode = 0;\r
+ }\r
+ else if ( tininessModeIn ) {\r
+ tininessMode = tininessModeIn;\r
+ }\r
+ }\r
+ timeFunctionVariety(\r
+ functionCode, roundingPrecision, roundingMode, tininessMode\r
+ );\r
+ if ( tininessModeIn || ! tininessMode ) break;\r
+ }\r
+ if ( roundingModeIn || ! roundingMode ) break;\r
+ }\r
+ if ( roundingPrecisionIn || ! roundingPrecision ) break;\r
+ if ( roundingPrecision == 80 ) {\r
+ break;\r
+ }\r
+ else if ( roundingPrecision == 64 ) {\r
+ roundingPrecision = 80;\r
+ }\r
+ else if ( roundingPrecision == 32 ) {\r
+ roundingPrecision = 64;\r
+ }\r
+ }\r
+\r
+}\r
+\r
+main( int argc, char **argv )\r
+{\r
+ char *argPtr;\r
+ flag functionArgument;\r
+ uint8 functionCode;\r
+ int8 operands, roundingPrecision, roundingMode, tininessMode;\r
+\r
+ if ( argc <= 1 ) goto writeHelpMessage;\r
+ functionArgument = FALSE;\r
+ functionCode = 0;\r
+ operands = 0;\r
+ roundingPrecision = 0;\r
+ roundingMode = 0;\r
+ tininessMode = 0;\r
+ --argc;\r
+ ++argv;\r
+ while ( argc && ( argPtr = argv[ 0 ] ) ) {\r
+ if ( argPtr[ 0 ] == '-' ) ++argPtr;\r
+ if ( strcmp( argPtr, "help" ) == 0 ) {\r
+ writeHelpMessage:\r
+ fputs(\r
+"timesoftfloat [<option>...] <function>\n"\r
+" <option>: (* is default)\n"\r
+" -help --Write this message and exit.\n"\r
+#ifdef FLOATX80\r
+" -precision32 --Only time rounding precision equivalent to float32.\n"\r
+" -precision64 --Only time rounding precision equivalent to float64.\n"\r
+" -precision80 --Only time maximum rounding precision.\n"\r
+#endif\r
+" -nearesteven --Only time rounding to nearest/even.\n"\r
+" -tozero --Only time rounding to zero.\n"\r
+" -down --Only time rounding down.\n"\r
+" -up --Only time rounding up.\n"\r
+" -tininessbefore --Only time underflow tininess before rounding.\n"\r
+" -tininessafter --Only time underflow tininess after rounding.\n"\r
+" <function>:\n"\r
+" int32_to_<float> <float>_add <float>_eq\n"\r
+" <float>_to_int32 <float>_sub <float>_le\n"\r
+" <float>_to_int32_round_to_zero <float>_mul <float>_lt\n"\r
+" int64_to_<float> <float>_div <float>_eq_signaling\n"\r
+" <float>_to_int64 <float>_rem <float>_le_quiet\n"\r
+" <float>_to_int64_round_to_zero <float>_lt_quiet\n"\r
+" <float>_to_<float>\n"\r
+" <float>_round_to_int\n"\r
+" <float>_sqrt\n"\r
+" -all1 --All 1-operand functions.\n"\r
+" -all2 --All 2-operand functions.\n"\r
+" -all --All functions.\n"\r
+" <float>:\n"\r
+" float32 --Single precision.\n"\r
+" float64 --Double precision.\n"\r
+#ifdef FLOATX80\r
+" floatx80 --Extended double precision.\n"\r
+#endif\r
+#ifdef FLOAT128\r
+" float128 --Quadruple precision.\n"\r
+#endif\r
+ ,\r
+ stdout\r
+ );\r
+ return EXIT_SUCCESS;\r
+ }\r
+#ifdef FLOATX80\r
+ else if ( strcmp( argPtr, "precision32" ) == 0 ) {\r
+ roundingPrecision = 32;\r
+ }\r
+ else if ( strcmp( argPtr, "precision64" ) == 0 ) {\r
+ roundingPrecision = 64;\r
+ }\r
+ else if ( strcmp( argPtr, "precision80" ) == 0 ) {\r
+ roundingPrecision = 80;\r
+ }\r
+#endif\r
+ else if ( ( strcmp( argPtr, "nearesteven" ) == 0 )\r
+ || ( strcmp( argPtr, "nearest_even" ) == 0 ) ) {\r
+ roundingMode = ROUND_NEAREST_EVEN;\r
+ }\r
+ else if ( ( strcmp( argPtr, "tozero" ) == 0 )\r
+ || ( strcmp( argPtr, "to_zero" ) == 0 ) ) {\r
+ roundingMode = ROUND_TO_ZERO;\r
+ }\r
+ else if ( strcmp( argPtr, "down" ) == 0 ) {\r
+ roundingMode = ROUND_DOWN;\r
+ }\r
+ else if ( strcmp( argPtr, "up" ) == 0 ) {\r
+ roundingMode = ROUND_UP;\r
+ }\r
+ else if ( strcmp( argPtr, "tininessbefore" ) == 0 ) {\r
+ tininessMode = TININESS_BEFORE_ROUNDING;\r
+ }\r
+ else if ( strcmp( argPtr, "tininessafter" ) == 0 ) {\r
+ tininessMode = TININESS_AFTER_ROUNDING;\r
+ }\r
+ else if ( strcmp( argPtr, "all1" ) == 0 ) {\r
+ functionArgument = TRUE;\r
+ functionCode = 0;\r
+ operands = 1;\r
+ }\r
+ else if ( strcmp( argPtr, "all2" ) == 0 ) {\r
+ functionArgument = TRUE;\r
+ functionCode = 0;\r
+ operands = 2;\r
+ }\r
+ else if ( strcmp( argPtr, "all" ) == 0 ) {\r
+ functionArgument = TRUE;\r
+ functionCode = 0;\r
+ operands = 0;\r
+ }\r
+ else {\r
+ for ( functionCode = 1;\r
+ functionCode < NUM_FUNCTIONS;\r
+ ++functionCode \r
+ ) {\r
+ if ( strcmp( argPtr, functions[ functionCode ].name ) == 0 ) {\r
+ break;\r
+ }\r
+ }\r
+ if ( functionCode == NUM_FUNCTIONS ) {\r
+ fail( "Invalid option or function `%s'", argv[ 0 ] );\r
+ }\r
+ functionArgument = TRUE;\r
+ }\r
+ --argc;\r
+ ++argv;\r
+ }\r
+ if ( ! functionArgument ) fail( "Function argument required" );\r
+ if ( functionCode ) {\r
+ timeFunction(\r
+ functionCode, roundingPrecision, roundingMode, tininessMode );\r
+ }\r
+ else if ( operands == 1 ) {\r
+ for ( functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode\r
+ ) {\r
+ if ( functions[ functionCode ].numInputs == 1 ) {\r
+ timeFunction(\r
+ functionCode, roundingPrecision, roundingMode, tininessMode\r
+ );\r
+ }\r
+ }\r
+ }\r
+ else if ( operands == 2 ) {\r
+ for ( functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode\r
+ ) {\r
+ if ( functions[ functionCode ].numInputs == 2 ) {\r
+ timeFunction(\r
+ functionCode, roundingPrecision, roundingMode, tininessMode\r
+ );\r
+ }\r
+ }\r
+ }\r
+ else {\r
+ for ( functionCode = 1; functionCode < NUM_FUNCTIONS; ++functionCode\r
+ ) {\r
+ timeFunction(\r
+ functionCode, roundingPrecision, roundingMode, tininessMode );\r
+ }\r
+ }\r
+ return EXIT_SUCCESS;\r
+\r
+}\r
+\r
--- /dev/null
+\r
+Documentation for the `timesoftfloat' Program of SoftFloat Release 2b\r
+\r
+John R. Hauser\r
+2002 May 27\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Introduction\r
+\r
+The `timesoftfloat' program evaluates the speed of SoftFloat's floating-\r
+point routines. Each routine can be evaluated for every relevant rounding\r
+mode, tininess mode, and/or rounding precision.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Contents\r
+\r
+ Introduction\r
+ Contents\r
+ Legal Notice\r
+ Executing `timesoftfloat'\r
+ Options\r
+ -help\r
+ -precision32, -precision64, -precision80\r
+ -nearesteven, -tozero, -down, -up\r
+ -tininessbefore, -tininessafter\r
+ Function Sets\r
+\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Legal Notice\r
+\r
+The `timesoftfloat' program was written by John R. Hauser.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort\r
+has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT\r
+TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO\r
+PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL\r
+LOSSES, COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO\r
+FURTHERMORE EFFECTIVELY INDEMNIFY THE AUTHOR, JOHN HAUSER, (possibly via\r
+similar legal warning) AGAINST ALL LOSSES, COSTS, OR OTHER PROBLEMS INCURRED\r
+BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Executing `timesoftfloat'\r
+\r
+The `timesoftfloat' program is intended to be invoked from a command line\r
+interpreter as follows:\r
+\r
+ timesoftfloat [<option>...] <function>\r
+\r
+Here square brackets ([]) indicate optional items, while angled brackets\r
+(<>) denote parameters to be filled in. The `<function>' argument is\r
+the name of the SoftFloat routine to evaluate, such as `float32_add' or\r
+`float64_to_int32'. The allowed options are detailed in the next section,\r
+_Options_. If `timesoftfloat' is executed without any arguments, a summary\r
+of usage is written. It is also possible to evaluate all machine functions\r
+in a single invocation as explained in the section _Function Sets_ later in\r
+this document.\r
+\r
+Ordinarily, a function's speed will be evaulated separately for each of\r
+the four rounding modes, one after the other. If the rounding mode is not\r
+supposed to have any effect on the results of a function--for instance,\r
+some operations do not require rounding--only the nearest/even rounding mode\r
+is timed. In the same way, if a function is affected by the way in which\r
+underflow tininess is detected, `timesoftfloat' times the function both with\r
+tininess detected before rounding and after rounding. For extended double-\r
+precision operations affected by rounding precision control, `timesoftfloat'\r
+also times the function for all three rounding precision modes, one after\r
+the other. Evaluation of a function can be limited to a single rounding\r
+mode, a single tininess mode, and/or a single rounding precision with\r
+appropriate options (see _Options_).\r
+\r
+For each function and mode evaluated, `timesoftfloat' reports the speed of\r
+the function in kops/s, or ``thousands of operations per second''. This\r
+unit of measure differs from the traditional MFLOPS (``millions of floating-\r
+point operations per second'') only in being a factor of 1000 smaller.\r
+(1000 kops/s is exactly 1 MFLOPS.) Speeds are reported in thousands\r
+instead of millions because software floating-point may execute at less than\r
+1 MFLOPS.\r
+\r
+The speeds reported by `timesoftfloat' may be affected somewhat by other\r
+programs executing at the same time as `timesoftfloat'.\r
+\r
+Note that the remainder operations (`float32_rem', `float64_rem',\r
+`floatx80_rem' and `float128_rem') will be markedly slower than other\r
+operations, particularly for extended double precision (`floatx80') and\r
+quadruple precision (`float128'). This is inherent to the remainder\r
+function itself and is not a failing of the SoftFloat implementation.\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Options\r
+\r
+The `timesoftfloat' program accepts several command options. If mutually\r
+contradictory options are given, the last one has priority.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+-help\r
+\r
+The `-help' option causes a summary of program usage to be written, after\r
+which the program exits.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+-precision32, -precision64, -precision80\r
+\r
+For extended double-precision functions affected by rounding precision\r
+control, the `-precision32' option restricts evaluation to only the cases\r
+in which rounding precision is equivalent to single precision. The other\r
+rounding precision options are not timed. Likewise, the `-precision64'\r
+and `-precision80' options fix the rounding precision equivalent to double\r
+precision or extended double precision, respectively. These options are\r
+ignored for functions not affected by rounding precision control.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+-nearesteven, -tozero, -down, -up\r
+\r
+The `-nearesteven' option restricts evaluation to only the cases in which\r
+the rounding mode is nearest/even. The other rounding mode options are\r
+not timed. Likewise, `-tozero' forces rounding toward zero; `-down' forces\r
+rounding down; and `-up' forces rounding up. These options are ignored for\r
+functions that are exact and thus do not round.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+-tininessbefore, -tininessafter\r
+\r
+The `-tininessbefore' option restricts evaluation to only the cases\r
+detecting underflow tininess before rounding. Tininess after rounding\r
+is not timed. Likewise, `-tininessafter' forces underflow tininess to be\r
+detected after rounding only. These options are ignored for functions not\r
+affected by the way in which underflow tininess is detected.\r
+\r
+- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
+\r
+\r
+----------------------------------------------------------------------------\r
+Function Sets\r
+\r
+Just as `timesoftfloat' can test an operation for all four rounding modes in\r
+sequence, multiple operations can also be tested with a single invocation.\r
+Three sets are recognized: `-all1', `-all2', and `-all'. The set `-all1'\r
+comprises all one-operand functions; `-all2' is all two-operand functions;\r
+and `-all' is all functions. A function set can be used in place of a\r
+function name in the command line, as in\r
+\r
+ timesoftfloat [<option>...] -all\r
+\r
+\r
projects / yasm / commitdiff